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1/* Initialize CPU feature data. AArch64 version.
2 This file is part of the GNU C Library.
3 Copyright (C) 2017-2019 Free Software Foundation, Inc.
4
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
9
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
14
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, see
17 <http://www.gnu.org/licenses/>. */
18
19#ifndef _CPU_FEATURES_AARCH64_H
20#define _CPU_FEATURES_AARCH64_H
21
22#include <stdint.h>
23
24#define MIDR_PARTNUM_SHIFT 4
25#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
26#define MIDR_PARTNUM(midr) \
27 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
28#define MIDR_ARCHITECTURE_SHIFT 16
29#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
30#define MIDR_ARCHITECTURE(midr) \
31 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
32#define MIDR_VARIANT_SHIFT 20
33#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
34#define MIDR_VARIANT(midr) \
35 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
36#define MIDR_IMPLEMENTOR_SHIFT 24
37#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT)
38#define MIDR_IMPLEMENTOR(midr) \
39 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
40
41#define IS_THUNDERX(midr) (MIDR_IMPLEMENTOR(midr) == 'C' \
42 && MIDR_PARTNUM(midr) == 0x0a1)
43
44#define IS_THUNDERX2PA(midr) (MIDR_IMPLEMENTOR(midr) == 'B' \
45 && MIDR_PARTNUM(midr) == 0x516)
46#define IS_THUNDERX2(midr) (MIDR_IMPLEMENTOR(midr) == 'C' \
47 && MIDR_PARTNUM(midr) == 0xaf)
48
49#define IS_FALKOR(midr) (MIDR_IMPLEMENTOR(midr) == 'Q' \
50 && MIDR_PARTNUM(midr) == 0xc00)
51
52#define IS_PHECDA(midr) (MIDR_IMPLEMENTOR(midr) == 'h' \
53 && MIDR_PARTNUM(midr) == 0x000)
54#define IS_ARES(midr) (MIDR_IMPLEMENTOR(midr) == 'A' \
55 && MIDR_PARTNUM(midr) == 0xd0c)
56
57#define IS_EMAG(midr) (MIDR_IMPLEMENTOR(midr) == 'P' \
58 && MIDR_PARTNUM(midr) == 0x000)
59
60struct cpu_features
61{
62 uint64_t midr_el1;
63 unsigned zva_size;
64};
65
66#endif /* _CPU_FEATURES_AARCH64_H */
67

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