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| 1 | /* Initialize CPU feature data. AArch64 version. |
|---|---|
| 2 | This file is part of the GNU C Library. |
| 3 | Copyright (C) 2017-2022 Free Software Foundation, Inc. |
| 4 | |
| 5 | The GNU C Library is free software; you can redistribute it and/or |
| 6 | modify it under the terms of the GNU Lesser General Public |
| 7 | License as published by the Free Software Foundation; either |
| 8 | version 2.1 of the License, or (at your option) any later version. |
| 9 | |
| 10 | The GNU C Library is distributed in the hope that it will be useful, |
| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 13 | Lesser General Public License for more details. |
| 14 | |
| 15 | You should have received a copy of the GNU Lesser General Public |
| 16 | License along with the GNU C Library; if not, see |
| 17 | <https://www.gnu.org/licenses/>. */ |
| 18 | |
| 19 | #ifndef _CPU_FEATURES_AARCH64_H |
| 20 | #define _CPU_FEATURES_AARCH64_H |
| 21 | |
| 22 | #include <stdint.h> |
| 23 | #include <stdbool.h> |
| 24 | |
| 25 | #define MIDR_PARTNUM_SHIFT 4 |
| 26 | #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) |
| 27 | #define MIDR_PARTNUM(midr) \ |
| 28 | (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) |
| 29 | #define MIDR_ARCHITECTURE_SHIFT 16 |
| 30 | #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) |
| 31 | #define MIDR_ARCHITECTURE(midr) \ |
| 32 | (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT) |
| 33 | #define MIDR_VARIANT_SHIFT 20 |
| 34 | #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT) |
| 35 | #define MIDR_VARIANT(midr) \ |
| 36 | (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) |
| 37 | #define MIDR_IMPLEMENTOR_SHIFT 24 |
| 38 | #define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT) |
| 39 | #define MIDR_IMPLEMENTOR(midr) \ |
| 40 | (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) |
| 41 | |
| 42 | #define IS_THUNDERX(midr) (MIDR_IMPLEMENTOR(midr) == 'C' \ |
| 43 | && MIDR_PARTNUM(midr) == 0x0a1) |
| 44 | |
| 45 | #define IS_THUNDERX2PA(midr) (MIDR_IMPLEMENTOR(midr) == 'B' \ |
| 46 | && MIDR_PARTNUM(midr) == 0x516) |
| 47 | #define IS_THUNDERX2(midr) (MIDR_IMPLEMENTOR(midr) == 'C' \ |
| 48 | && MIDR_PARTNUM(midr) == 0xaf) |
| 49 | |
| 50 | #define IS_FALKOR(midr) (MIDR_IMPLEMENTOR(midr) == 'Q' \ |
| 51 | && MIDR_PARTNUM(midr) == 0xc00) |
| 52 | |
| 53 | #define IS_PHECDA(midr) (MIDR_IMPLEMENTOR(midr) == 'h' \ |
| 54 | && MIDR_PARTNUM(midr) == 0x000) |
| 55 | #define IS_NEOVERSE_N1(midr) (MIDR_IMPLEMENTOR(midr) == 'A' \ |
| 56 | && MIDR_PARTNUM(midr) == 0xd0c) |
| 57 | #define IS_NEOVERSE_N2(midr) (MIDR_IMPLEMENTOR(midr) == 'A' \ |
| 58 | && MIDR_PARTNUM(midr) == 0xd49) |
| 59 | #define IS_NEOVERSE_V1(midr) (MIDR_IMPLEMENTOR(midr) == 'A' \ |
| 60 | && MIDR_PARTNUM(midr) == 0xd40) |
| 61 | |
| 62 | #define IS_EMAG(midr) (MIDR_IMPLEMENTOR(midr) == 'P' \ |
| 63 | && MIDR_PARTNUM(midr) == 0x000) |
| 64 | |
| 65 | #define IS_KUNPENG920(midr) (MIDR_IMPLEMENTOR(midr) == 'H' \ |
| 66 | && MIDR_PARTNUM(midr) == 0xd01) |
| 67 | |
| 68 | #define IS_A64FX(midr) (MIDR_IMPLEMENTOR(midr) == 'F' \ |
| 69 | && MIDR_PARTNUM(midr) == 0x001) |
| 70 | |
| 71 | struct cpu_features |
| 72 | { |
| 73 | uint64_t midr_el1; |
| 74 | unsigned zva_size; |
| 75 | bool bti; |
| 76 | /* Currently, the GLIBC memory tagging tunable only defines 8 bits. */ |
| 77 | uint8_t mte_state; |
| 78 | bool sve; |
| 79 | }; |
| 80 | |
| 81 | #endif /* _CPU_FEATURES_AARCH64_H */ |
| 82 |
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