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1/* Atomic operations. ARM/Linux version.
2 Copyright (C) 2002-2019 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
4
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
9
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
14
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library. If not, see
17 <http://www.gnu.org/licenses/>. */
18
19#include <stdint.h>
20
21/* If the compiler doesn't provide a primitive, we'll use this macro
22 to get assistance from the kernel. */
23#ifdef __thumb2__
24# define __arm_assisted_full_barrier() \
25 __asm__ __volatile__ \
26 ("movw\tip, #0x0fa0\n\t" \
27 "movt\tip, #0xffff\n\t" \
28 "blx\tip" \
29 : : : "ip", "lr", "cc", "memory");
30#else
31# define __arm_assisted_full_barrier() \
32 __asm__ __volatile__ \
33 ("mov\tip, #0xffff0fff\n\t" \
34 "mov\tlr, pc\n\t" \
35 "add\tpc, ip, #(0xffff0fa0 - 0xffff0fff)" \
36 : : : "ip", "lr", "cc", "memory");
37#endif
38
39/* Atomic compare and exchange. This sequence relies on the kernel to
40 provide a compare and exchange operation which is atomic on the
41 current architecture, either via cleverness on pre-ARMv6 or via
42 ldrex / strex on ARMv6.
43
44 It doesn't matter what register is used for a_oldval2, but we must
45 specify one to work around GCC PR rtl-optimization/21223. Otherwise
46 it may cause a_oldval or a_tmp to be moved to a different register.
47
48 We use the union trick rather than simply using __typeof (...) in the
49 declarations of A_OLDVAL et al because when NEWVAL or OLDVAL is of the
50 form *PTR and PTR has a 'volatile ... *' type, then __typeof (*PTR) has
51 a 'volatile ...' type and this triggers -Wvolatile-register-var to
52 complain about 'register volatile ... asm ("reg")'.
53
54 We use the same union trick in the declaration of A_PTR because when
55 MEM is of the from *PTR and PTR has a 'const ... *' type, then __typeof
56 (*PTR) has a 'const ...' type and this enables the compiler to substitute
57 the variable with its initializer in asm statements, which may cause the
58 corresponding operand to appear in a different register. */
59#ifdef __thumb2__
60/* Thumb-2 has ldrex/strex. However it does not have barrier instructions,
61 so we still need to use the kernel helper. */
62# define __arm_assisted_compare_and_exchange_val_32_acq(mem, newval, oldval) \
63 ({ union { __typeof (mem) a; uint32_t v; } mem_arg = { .a = (mem) }; \
64 union { __typeof (oldval) a; uint32_t v; } oldval_arg = { .a = (oldval) };\
65 union { __typeof (newval) a; uint32_t v; } newval_arg = { .a = (newval) };\
66 register uint32_t a_oldval asm ("r0"); \
67 register uint32_t a_newval asm ("r1") = newval_arg.v; \
68 register uint32_t a_ptr asm ("r2") = mem_arg.v; \
69 register uint32_t a_tmp asm ("r3"); \
70 register uint32_t a_oldval2 asm ("r4") = oldval_arg.v; \
71 __asm__ __volatile__ \
72 ("0:\tldr\t%[tmp],[%[ptr]]\n\t" \
73 "cmp\t%[tmp], %[old2]\n\t" \
74 "bne\t1f\n\t" \
75 "mov\t%[old], %[old2]\n\t" \
76 "movw\t%[tmp], #0x0fc0\n\t" \
77 "movt\t%[tmp], #0xffff\n\t" \
78 "blx\t%[tmp]\n\t" \
79 "bcc\t0b\n\t" \
80 "mov\t%[tmp], %[old2]\n\t" \
81 "1:" \
82 : [old] "=&r" (a_oldval), [tmp] "=&r" (a_tmp) \
83 : [new] "r" (a_newval), [ptr] "r" (a_ptr), \
84 [old2] "r" (a_oldval2) \
85 : "ip", "lr", "cc", "memory"); \
86 (__typeof (oldval)) a_tmp; })
87#else
88# define __arm_assisted_compare_and_exchange_val_32_acq(mem, newval, oldval) \
89 ({ union { __typeof (mem) a; uint32_t v; } mem_arg = { .a = (mem) }; \
90 union { __typeof (oldval) a; uint32_t v; } oldval_arg = { .a = (oldval) };\
91 union { __typeof (newval) a; uint32_t v; } newval_arg = { .a = (newval) };\
92 register uint32_t a_oldval asm ("r0"); \
93 register uint32_t a_newval asm ("r1") = newval_arg.v; \
94 register uint32_t a_ptr asm ("r2") = mem_arg.v; \
95 register uint32_t a_tmp asm ("r3"); \
96 register uint32_t a_oldval2 asm ("r4") = oldval_arg.v; \
97 __asm__ __volatile__ \
98 ("0:\tldr\t%[tmp],[%[ptr]]\n\t" \
99 "cmp\t%[tmp], %[old2]\n\t" \
100 "bne\t1f\n\t" \
101 "mov\t%[old], %[old2]\n\t" \
102 "mov\t%[tmp], #0xffff0fff\n\t" \
103 "mov\tlr, pc\n\t" \
104 "add\tpc, %[tmp], #(0xffff0fc0 - 0xffff0fff)\n\t" \
105 "bcc\t0b\n\t" \
106 "mov\t%[tmp], %[old2]\n\t" \
107 "1:" \
108 : [old] "=&r" (a_oldval), [tmp] "=&r" (a_tmp) \
109 : [new] "r" (a_newval), [ptr] "r" (a_ptr), \
110 [old2] "r" (a_oldval2) \
111 : "ip", "lr", "cc", "memory"); \
112 (__typeof (oldval)) a_tmp; })
113#endif
114
115#include <sysdeps/arm/atomic-machine.h>
116

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