1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_PERF_EVENT_H
3#define _ASM_X86_PERF_EVENT_H
4
5#include <linux/static_call.h>
6
7/*
8 * Performance event hw details:
9 */
10
11#define INTEL_PMC_MAX_GENERIC 32
12#define INTEL_PMC_MAX_FIXED 16
13#define INTEL_PMC_IDX_FIXED 32
14
15#define X86_PMC_IDX_MAX 64
16
17#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
18#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
19
20#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
21#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
22
23#define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
24#define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
25#define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16)
26#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17)
27#define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18)
28#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL (1ULL << 19)
29#define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20)
30#define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21)
31#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22)
32#define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
33#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
34#define ARCH_PERFMON_EVENTSEL_BR_CNTR (1ULL << 35)
35
36#define INTEL_FIXED_BITS_MASK 0xFULL
37#define INTEL_FIXED_BITS_STRIDE 4
38#define INTEL_FIXED_0_KERNEL (1ULL << 0)
39#define INTEL_FIXED_0_USER (1ULL << 1)
40#define INTEL_FIXED_0_ANYTHREAD (1ULL << 2)
41#define INTEL_FIXED_0_ENABLE_PMI (1ULL << 3)
42
43#define HSW_IN_TX (1ULL << 32)
44#define HSW_IN_TX_CHECKPOINTED (1ULL << 33)
45#define ICL_EVENTSEL_ADAPTIVE (1ULL << 34)
46#define ICL_FIXED_0_ADAPTIVE (1ULL << 32)
47
48#define intel_fixed_bits_by_idx(_idx, _bits) \
49 ((_bits) << ((_idx) * INTEL_FIXED_BITS_STRIDE))
50
51#define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36)
52#define AMD64_EVENTSEL_GUESTONLY (1ULL << 40)
53#define AMD64_EVENTSEL_HOSTONLY (1ULL << 41)
54
55#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37
56#define AMD64_EVENTSEL_INT_CORE_SEL_MASK \
57 (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
58
59#define AMD64_EVENTSEL_EVENT \
60 (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
61#define INTEL_ARCH_EVENT_MASK \
62 (ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
63
64#define AMD64_L3_SLICE_SHIFT 48
65#define AMD64_L3_SLICE_MASK \
66 (0xFULL << AMD64_L3_SLICE_SHIFT)
67#define AMD64_L3_SLICEID_MASK \
68 (0x7ULL << AMD64_L3_SLICE_SHIFT)
69
70#define AMD64_L3_THREAD_SHIFT 56
71#define AMD64_L3_THREAD_MASK \
72 (0xFFULL << AMD64_L3_THREAD_SHIFT)
73#define AMD64_L3_F19H_THREAD_MASK \
74 (0x3ULL << AMD64_L3_THREAD_SHIFT)
75
76#define AMD64_L3_EN_ALL_CORES BIT_ULL(47)
77#define AMD64_L3_EN_ALL_SLICES BIT_ULL(46)
78
79#define AMD64_L3_COREID_SHIFT 42
80#define AMD64_L3_COREID_MASK \
81 (0x7ULL << AMD64_L3_COREID_SHIFT)
82
83#define X86_RAW_EVENT_MASK \
84 (ARCH_PERFMON_EVENTSEL_EVENT | \
85 ARCH_PERFMON_EVENTSEL_UMASK | \
86 ARCH_PERFMON_EVENTSEL_EDGE | \
87 ARCH_PERFMON_EVENTSEL_INV | \
88 ARCH_PERFMON_EVENTSEL_CMASK)
89#define X86_ALL_EVENT_FLAGS \
90 (ARCH_PERFMON_EVENTSEL_EDGE | \
91 ARCH_PERFMON_EVENTSEL_INV | \
92 ARCH_PERFMON_EVENTSEL_CMASK | \
93 ARCH_PERFMON_EVENTSEL_ANY | \
94 ARCH_PERFMON_EVENTSEL_PIN_CONTROL | \
95 HSW_IN_TX | \
96 HSW_IN_TX_CHECKPOINTED)
97#define AMD64_RAW_EVENT_MASK \
98 (X86_RAW_EVENT_MASK | \
99 AMD64_EVENTSEL_EVENT)
100#define AMD64_RAW_EVENT_MASK_NB \
101 (AMD64_EVENTSEL_EVENT | \
102 ARCH_PERFMON_EVENTSEL_UMASK)
103
104#define AMD64_PERFMON_V2_EVENTSEL_EVENT_NB \
105 (AMD64_EVENTSEL_EVENT | \
106 GENMASK_ULL(37, 36))
107
108#define AMD64_PERFMON_V2_EVENTSEL_UMASK_NB \
109 (ARCH_PERFMON_EVENTSEL_UMASK | \
110 GENMASK_ULL(27, 24))
111
112#define AMD64_PERFMON_V2_RAW_EVENT_MASK_NB \
113 (AMD64_PERFMON_V2_EVENTSEL_EVENT_NB | \
114 AMD64_PERFMON_V2_EVENTSEL_UMASK_NB)
115
116#define AMD64_PERFMON_V2_ENABLE_UMC BIT_ULL(31)
117#define AMD64_PERFMON_V2_EVENTSEL_EVENT_UMC GENMASK_ULL(7, 0)
118#define AMD64_PERFMON_V2_EVENTSEL_RDWRMASK_UMC GENMASK_ULL(9, 8)
119#define AMD64_PERFMON_V2_RAW_EVENT_MASK_UMC \
120 (AMD64_PERFMON_V2_EVENTSEL_EVENT_UMC | \
121 AMD64_PERFMON_V2_EVENTSEL_RDWRMASK_UMC)
122
123#define AMD64_NUM_COUNTERS 4
124#define AMD64_NUM_COUNTERS_CORE 6
125#define AMD64_NUM_COUNTERS_NB 4
126
127#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
128#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
129#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
130#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
131 (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
132
133#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
134#define ARCH_PERFMON_EVENTS_COUNT 7
135
136#define PEBS_DATACFG_MEMINFO BIT_ULL(0)
137#define PEBS_DATACFG_GP BIT_ULL(1)
138#define PEBS_DATACFG_XMMS BIT_ULL(2)
139#define PEBS_DATACFG_LBRS BIT_ULL(3)
140#define PEBS_DATACFG_LBR_SHIFT 24
141
142/* Steal the highest bit of pebs_data_cfg for SW usage */
143#define PEBS_UPDATE_DS_SW BIT_ULL(63)
144
145/*
146 * Intel "Architectural Performance Monitoring" CPUID
147 * detection/enumeration details:
148 */
149union cpuid10_eax {
150 struct {
151 unsigned int version_id:8;
152 unsigned int num_counters:8;
153 unsigned int bit_width:8;
154 unsigned int mask_length:8;
155 } split;
156 unsigned int full;
157};
158
159union cpuid10_ebx {
160 struct {
161 unsigned int no_unhalted_core_cycles:1;
162 unsigned int no_instructions_retired:1;
163 unsigned int no_unhalted_reference_cycles:1;
164 unsigned int no_llc_reference:1;
165 unsigned int no_llc_misses:1;
166 unsigned int no_branch_instruction_retired:1;
167 unsigned int no_branch_misses_retired:1;
168 } split;
169 unsigned int full;
170};
171
172union cpuid10_edx {
173 struct {
174 unsigned int num_counters_fixed:5;
175 unsigned int bit_width_fixed:8;
176 unsigned int reserved1:2;
177 unsigned int anythread_deprecated:1;
178 unsigned int reserved2:16;
179 } split;
180 unsigned int full;
181};
182
183/*
184 * Intel "Architectural Performance Monitoring extension" CPUID
185 * detection/enumeration details:
186 */
187#define ARCH_PERFMON_EXT_LEAF 0x00000023
188#define ARCH_PERFMON_NUM_COUNTER_LEAF_BIT 0x1
189#define ARCH_PERFMON_NUM_COUNTER_LEAF 0x1
190
191/*
192 * Intel Architectural LBR CPUID detection/enumeration details:
193 */
194union cpuid28_eax {
195 struct {
196 /* Supported LBR depth values */
197 unsigned int lbr_depth_mask:8;
198 unsigned int reserved:22;
199 /* Deep C-state Reset */
200 unsigned int lbr_deep_c_reset:1;
201 /* IP values contain LIP */
202 unsigned int lbr_lip:1;
203 } split;
204 unsigned int full;
205};
206
207union cpuid28_ebx {
208 struct {
209 /* CPL Filtering Supported */
210 unsigned int lbr_cpl:1;
211 /* Branch Filtering Supported */
212 unsigned int lbr_filter:1;
213 /* Call-stack Mode Supported */
214 unsigned int lbr_call_stack:1;
215 } split;
216 unsigned int full;
217};
218
219union cpuid28_ecx {
220 struct {
221 /* Mispredict Bit Supported */
222 unsigned int lbr_mispred:1;
223 /* Timed LBRs Supported */
224 unsigned int lbr_timed_lbr:1;
225 /* Branch Type Field Supported */
226 unsigned int lbr_br_type:1;
227 unsigned int reserved:13;
228 /* Branch counters (Event Logging) Supported */
229 unsigned int lbr_counters:4;
230 } split;
231 unsigned int full;
232};
233
234/*
235 * AMD "Extended Performance Monitoring and Debug" CPUID
236 * detection/enumeration details:
237 */
238union cpuid_0x80000022_ebx {
239 struct {
240 /* Number of Core Performance Counters */
241 unsigned int num_core_pmc:4;
242 /* Number of available LBR Stack Entries */
243 unsigned int lbr_v2_stack_sz:6;
244 /* Number of Data Fabric Counters */
245 unsigned int num_df_pmc:6;
246 /* Number of Unified Memory Controller Counters */
247 unsigned int num_umc_pmc:6;
248 } split;
249 unsigned int full;
250};
251
252struct x86_pmu_capability {
253 int version;
254 int num_counters_gp;
255 int num_counters_fixed;
256 int bit_width_gp;
257 int bit_width_fixed;
258 unsigned int events_mask;
259 int events_mask_len;
260 unsigned int pebs_ept :1;
261};
262
263/*
264 * Fixed-purpose performance events:
265 */
266
267/* RDPMC offset for Fixed PMCs */
268#define INTEL_PMC_FIXED_RDPMC_BASE (1 << 30)
269#define INTEL_PMC_FIXED_RDPMC_METRICS (1 << 29)
270
271/*
272 * All the fixed-mode PMCs are configured via this single MSR:
273 */
274#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
275
276/*
277 * There is no event-code assigned to the fixed-mode PMCs.
278 *
279 * For a fixed-mode PMC, which has an equivalent event on a general-purpose
280 * PMC, the event-code of the equivalent event is used for the fixed-mode PMC,
281 * e.g., Instr_Retired.Any and CPU_CLK_Unhalted.Core.
282 *
283 * For a fixed-mode PMC, which doesn't have an equivalent event, a
284 * pseudo-encoding is used, e.g., CPU_CLK_Unhalted.Ref and TOPDOWN.SLOTS.
285 * The pseudo event-code for a fixed-mode PMC must be 0x00.
286 * The pseudo umask-code is 0xX. The X equals the index of the fixed
287 * counter + 1, e.g., the fixed counter 2 has the pseudo-encoding 0x0300.
288 *
289 * The counts are available in separate MSRs:
290 */
291
292/* Instr_Retired.Any: */
293#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
294#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0)
295
296/* CPU_CLK_Unhalted.Core: */
297#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
298#define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1)
299
300/* CPU_CLK_Unhalted.Ref: event=0x00,umask=0x3 (pseudo-encoding) */
301#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
302#define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2)
303#define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
304
305/* TOPDOWN.SLOTS: event=0x00,umask=0x4 (pseudo-encoding) */
306#define MSR_ARCH_PERFMON_FIXED_CTR3 0x30c
307#define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3)
308#define INTEL_PMC_MSK_FIXED_SLOTS (1ULL << INTEL_PMC_IDX_FIXED_SLOTS)
309
310static inline bool use_fixed_pseudo_encoding(u64 code)
311{
312 return !(code & 0xff);
313}
314
315/*
316 * We model BTS tracing as another fixed-mode PMC.
317 *
318 * We choose the value 47 for the fixed index of BTS, since lower
319 * values are used by actual fixed events and higher values are used
320 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
321 */
322#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 15)
323
324/*
325 * The PERF_METRICS MSR is modeled as several magic fixed-mode PMCs, one for
326 * each TopDown metric event.
327 *
328 * Internally the TopDown metric events are mapped to the FxCtr 3 (SLOTS).
329 */
330#define INTEL_PMC_IDX_METRIC_BASE (INTEL_PMC_IDX_FIXED + 16)
331#define INTEL_PMC_IDX_TD_RETIRING (INTEL_PMC_IDX_METRIC_BASE + 0)
332#define INTEL_PMC_IDX_TD_BAD_SPEC (INTEL_PMC_IDX_METRIC_BASE + 1)
333#define INTEL_PMC_IDX_TD_FE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 2)
334#define INTEL_PMC_IDX_TD_BE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 3)
335#define INTEL_PMC_IDX_TD_HEAVY_OPS (INTEL_PMC_IDX_METRIC_BASE + 4)
336#define INTEL_PMC_IDX_TD_BR_MISPREDICT (INTEL_PMC_IDX_METRIC_BASE + 5)
337#define INTEL_PMC_IDX_TD_FETCH_LAT (INTEL_PMC_IDX_METRIC_BASE + 6)
338#define INTEL_PMC_IDX_TD_MEM_BOUND (INTEL_PMC_IDX_METRIC_BASE + 7)
339#define INTEL_PMC_IDX_METRIC_END INTEL_PMC_IDX_TD_MEM_BOUND
340#define INTEL_PMC_MSK_TOPDOWN ((0xffull << INTEL_PMC_IDX_METRIC_BASE) | \
341 INTEL_PMC_MSK_FIXED_SLOTS)
342
343/*
344 * There is no event-code assigned to the TopDown events.
345 *
346 * For the slots event, use the pseudo code of the fixed counter 3.
347 *
348 * For the metric events, the pseudo event-code is 0x00.
349 * The pseudo umask-code starts from the middle of the pseudo event
350 * space, 0x80.
351 */
352#define INTEL_TD_SLOTS 0x0400 /* TOPDOWN.SLOTS */
353/* Level 1 metrics */
354#define INTEL_TD_METRIC_RETIRING 0x8000 /* Retiring metric */
355#define INTEL_TD_METRIC_BAD_SPEC 0x8100 /* Bad speculation metric */
356#define INTEL_TD_METRIC_FE_BOUND 0x8200 /* FE bound metric */
357#define INTEL_TD_METRIC_BE_BOUND 0x8300 /* BE bound metric */
358/* Level 2 metrics */
359#define INTEL_TD_METRIC_HEAVY_OPS 0x8400 /* Heavy Operations metric */
360#define INTEL_TD_METRIC_BR_MISPREDICT 0x8500 /* Branch Mispredict metric */
361#define INTEL_TD_METRIC_FETCH_LAT 0x8600 /* Fetch Latency metric */
362#define INTEL_TD_METRIC_MEM_BOUND 0x8700 /* Memory bound metric */
363
364#define INTEL_TD_METRIC_MAX INTEL_TD_METRIC_MEM_BOUND
365#define INTEL_TD_METRIC_NUM 8
366
367static inline bool is_metric_idx(int idx)
368{
369 return (unsigned)(idx - INTEL_PMC_IDX_METRIC_BASE) < INTEL_TD_METRIC_NUM;
370}
371
372static inline bool is_topdown_idx(int idx)
373{
374 return is_metric_idx(idx) || idx == INTEL_PMC_IDX_FIXED_SLOTS;
375}
376
377#define INTEL_PMC_OTHER_TOPDOWN_BITS(bit) \
378 (~(0x1ull << bit) & INTEL_PMC_MSK_TOPDOWN)
379
380#define GLOBAL_STATUS_COND_CHG BIT_ULL(63)
381#define GLOBAL_STATUS_BUFFER_OVF_BIT 62
382#define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(GLOBAL_STATUS_BUFFER_OVF_BIT)
383#define GLOBAL_STATUS_UNC_OVF BIT_ULL(61)
384#define GLOBAL_STATUS_ASIF BIT_ULL(60)
385#define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59)
386#define GLOBAL_STATUS_LBRS_FROZEN_BIT 58
387#define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(GLOBAL_STATUS_LBRS_FROZEN_BIT)
388#define GLOBAL_STATUS_TRACE_TOPAPMI_BIT 55
389#define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(GLOBAL_STATUS_TRACE_TOPAPMI_BIT)
390#define GLOBAL_STATUS_PERF_METRICS_OVF_BIT 48
391
392#define GLOBAL_CTRL_EN_PERF_METRICS 48
393/*
394 * We model guest LBR event tracing as another fixed-mode PMC like BTS.
395 *
396 * We choose bit 58 because it's used to indicate LBR stack frozen state
397 * for architectural perfmon v4, also we unconditionally mask that bit in
398 * the handle_pmi_common(), so it'll never be set in the overflow handling.
399 *
400 * With this fake counter assigned, the guest LBR event user (such as KVM),
401 * can program the LBR registers on its own, and we don't actually do anything
402 * with then in the host context.
403 */
404#define INTEL_PMC_IDX_FIXED_VLBR (GLOBAL_STATUS_LBRS_FROZEN_BIT)
405
406/*
407 * Pseudo-encoding the guest LBR event as event=0x00,umask=0x1b,
408 * since it would claim bit 58 which is effectively Fixed26.
409 */
410#define INTEL_FIXED_VLBR_EVENT 0x1b00
411
412/*
413 * Adaptive PEBS v4
414 */
415
416struct pebs_basic {
417 u64 format_size;
418 u64 ip;
419 u64 applicable_counters;
420 u64 tsc;
421};
422
423struct pebs_meminfo {
424 u64 address;
425 u64 aux;
426 u64 latency;
427 u64 tsx_tuning;
428};
429
430struct pebs_gprs {
431 u64 flags, ip, ax, cx, dx, bx, sp, bp, si, di;
432 u64 r8, r9, r10, r11, r12, r13, r14, r15;
433};
434
435struct pebs_xmm {
436 u64 xmm[16*2]; /* two entries for each register */
437};
438
439/*
440 * AMD Extended Performance Monitoring and Debug cpuid feature detection
441 */
442#define EXT_PERFMON_DEBUG_FEATURES 0x80000022
443
444/*
445 * IBS cpuid feature detection
446 */
447
448#define IBS_CPUID_FEATURES 0x8000001b
449
450/*
451 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
452 * bit 0 is used to indicate the existence of IBS.
453 */
454#define IBS_CAPS_AVAIL (1U<<0)
455#define IBS_CAPS_FETCHSAM (1U<<1)
456#define IBS_CAPS_OPSAM (1U<<2)
457#define IBS_CAPS_RDWROPCNT (1U<<3)
458#define IBS_CAPS_OPCNT (1U<<4)
459#define IBS_CAPS_BRNTRGT (1U<<5)
460#define IBS_CAPS_OPCNTEXT (1U<<6)
461#define IBS_CAPS_RIPINVALIDCHK (1U<<7)
462#define IBS_CAPS_OPBRNFUSE (1U<<8)
463#define IBS_CAPS_FETCHCTLEXTD (1U<<9)
464#define IBS_CAPS_OPDATA4 (1U<<10)
465#define IBS_CAPS_ZEN4 (1U<<11)
466
467#define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \
468 | IBS_CAPS_FETCHSAM \
469 | IBS_CAPS_OPSAM)
470
471/*
472 * IBS APIC setup
473 */
474#define IBSCTL 0x1cc
475#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
476#define IBSCTL_LVT_OFFSET_MASK 0x0F
477
478/* IBS fetch bits/masks */
479#define IBS_FETCH_L3MISSONLY (1ULL<<59)
480#define IBS_FETCH_RAND_EN (1ULL<<57)
481#define IBS_FETCH_VAL (1ULL<<49)
482#define IBS_FETCH_ENABLE (1ULL<<48)
483#define IBS_FETCH_CNT 0xFFFF0000ULL
484#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
485
486/*
487 * IBS op bits/masks
488 * The lower 7 bits of the current count are random bits
489 * preloaded by hardware and ignored in software
490 */
491#define IBS_OP_CUR_CNT (0xFFF80ULL<<32)
492#define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32)
493#define IBS_OP_CNT_CTL (1ULL<<19)
494#define IBS_OP_VAL (1ULL<<18)
495#define IBS_OP_ENABLE (1ULL<<17)
496#define IBS_OP_L3MISSONLY (1ULL<<16)
497#define IBS_OP_MAX_CNT 0x0000FFFFULL
498#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
499#define IBS_OP_MAX_CNT_EXT_MASK (0x7FULL<<20) /* separate upper 7 bits */
500#define IBS_RIP_INVALID (1ULL<<38)
501
502#ifdef CONFIG_X86_LOCAL_APIC
503extern u32 get_ibs_caps(void);
504extern int forward_event_to_ibs(struct perf_event *event);
505#else
506static inline u32 get_ibs_caps(void) { return 0; }
507static inline int forward_event_to_ibs(struct perf_event *event) { return -ENOENT; }
508#endif
509
510#ifdef CONFIG_PERF_EVENTS
511extern void perf_events_lapic_init(void);
512
513/*
514 * Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
515 * unused and ABI specified to be 0, so nobody should care what we do with
516 * them.
517 *
518 * EXACT - the IP points to the exact instruction that triggered the
519 * event (HW bugs exempt).
520 * VM - original X86_VM_MASK; see set_linear_ip().
521 */
522#define PERF_EFLAGS_EXACT (1UL << 3)
523#define PERF_EFLAGS_VM (1UL << 5)
524
525struct pt_regs;
526struct x86_perf_regs {
527 struct pt_regs regs;
528 u64 *xmm_regs;
529};
530
531extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
532extern unsigned long perf_misc_flags(struct pt_regs *regs);
533#define perf_misc_flags(regs) perf_misc_flags(regs)
534
535#include <asm/stacktrace.h>
536
537/*
538 * We abuse bit 3 from flags to pass exact information, see perf_misc_flags
539 * and the comment with PERF_EFLAGS_EXACT.
540 */
541#define perf_arch_fetch_caller_regs(regs, __ip) { \
542 (regs)->ip = (__ip); \
543 (regs)->sp = (unsigned long)__builtin_frame_address(0); \
544 (regs)->cs = __KERNEL_CS; \
545 regs->flags = 0; \
546}
547
548struct perf_guest_switch_msr {
549 unsigned msr;
550 u64 host, guest;
551};
552
553struct x86_pmu_lbr {
554 unsigned int nr;
555 unsigned int from;
556 unsigned int to;
557 unsigned int info;
558 bool has_callstack;
559};
560
561extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
562extern u64 perf_get_hw_event_config(int hw_event);
563extern void perf_check_microcode(void);
564extern void perf_clear_dirty_counters(void);
565extern int x86_perf_rdpmc_index(struct perf_event *event);
566#else
567static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
568{
569 memset(cap, 0, sizeof(*cap));
570}
571
572static inline u64 perf_get_hw_event_config(int hw_event)
573{
574 return 0;
575}
576
577static inline void perf_events_lapic_init(void) { }
578static inline void perf_check_microcode(void) { }
579#endif
580
581#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL)
582extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data);
583extern void x86_perf_get_lbr(struct x86_pmu_lbr *lbr);
584#else
585struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data);
586static inline void x86_perf_get_lbr(struct x86_pmu_lbr *lbr)
587{
588 memset(lbr, 0, sizeof(*lbr));
589}
590#endif
591
592#ifdef CONFIG_CPU_SUP_INTEL
593 extern void intel_pt_handle_vmx(int on);
594#else
595static inline void intel_pt_handle_vmx(int on)
596{
597
598}
599#endif
600
601#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
602 extern void amd_pmu_enable_virt(void);
603 extern void amd_pmu_disable_virt(void);
604
605#if defined(CONFIG_PERF_EVENTS_AMD_BRS)
606
607#define PERF_NEEDS_LOPWR_CB 1
608
609/*
610 * architectural low power callback impacts
611 * drivers/acpi/processor_idle.c
612 * drivers/acpi/acpi_pad.c
613 */
614extern void perf_amd_brs_lopwr_cb(bool lopwr_in);
615
616DECLARE_STATIC_CALL(perf_lopwr_cb, perf_amd_brs_lopwr_cb);
617
618static __always_inline void perf_lopwr_cb(bool lopwr_in)
619{
620 static_call_mod(perf_lopwr_cb)(lopwr_in);
621}
622
623#endif /* PERF_NEEDS_LOPWR_CB */
624
625#else
626 static inline void amd_pmu_enable_virt(void) { }
627 static inline void amd_pmu_disable_virt(void) { }
628#endif
629
630#define arch_perf_out_copy_user copy_from_user_nmi
631
632#endif /* _ASM_X86_PERF_EVENT_H */
633

source code of linux/arch/x86/include/asm/perf_event.h