1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Interrupt descriptor table related code |
4 | */ |
5 | #include <linux/interrupt.h> |
6 | |
7 | #include <asm/cpu_entry_area.h> |
8 | #include <asm/set_memory.h> |
9 | #include <asm/traps.h> |
10 | #include <asm/proto.h> |
11 | #include <asm/desc.h> |
12 | #include <asm/hw_irq.h> |
13 | #include <asm/ia32.h> |
14 | #include <asm/idtentry.h> |
15 | |
16 | #define DPL0 0x0 |
17 | #define DPL3 0x3 |
18 | |
19 | #define DEFAULT_STACK 0 |
20 | |
21 | #define G(_vector, _addr, _ist, _type, _dpl, _segment) \ |
22 | { \ |
23 | .vector = _vector, \ |
24 | .bits.ist = _ist, \ |
25 | .bits.type = _type, \ |
26 | .bits.dpl = _dpl, \ |
27 | .bits.p = 1, \ |
28 | .addr = _addr, \ |
29 | .segment = _segment, \ |
30 | } |
31 | |
32 | /* Interrupt gate */ |
33 | #define INTG(_vector, _addr) \ |
34 | G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS) |
35 | |
36 | /* System interrupt gate */ |
37 | #define SYSG(_vector, _addr) \ |
38 | G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS) |
39 | |
40 | #ifdef CONFIG_X86_64 |
41 | /* |
42 | * Interrupt gate with interrupt stack. The _ist index is the index in |
43 | * the tss.ist[] array, but for the descriptor it needs to start at 1. |
44 | */ |
45 | #define ISTG(_vector, _addr, _ist) \ |
46 | G(_vector, _addr, _ist + 1, GATE_INTERRUPT, DPL0, __KERNEL_CS) |
47 | #else |
48 | #define ISTG(_vector, _addr, _ist) INTG(_vector, _addr) |
49 | #endif |
50 | |
51 | /* Task gate */ |
52 | #define TSKG(_vector, _gdt) \ |
53 | G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3) |
54 | |
55 | #define IDT_TABLE_SIZE (IDT_ENTRIES * sizeof(gate_desc)) |
56 | |
57 | static bool idt_setup_done __initdata; |
58 | |
59 | /* |
60 | * Early traps running on the DEFAULT_STACK because the other interrupt |
61 | * stacks work only after cpu_init(). |
62 | */ |
63 | static const __initconst struct idt_data early_idts[] = { |
64 | INTG(X86_TRAP_DB, asm_exc_debug), |
65 | SYSG(X86_TRAP_BP, asm_exc_int3), |
66 | |
67 | #ifdef CONFIG_X86_32 |
68 | /* |
69 | * Not possible on 64-bit. See idt_setup_early_pf() for details. |
70 | */ |
71 | INTG(X86_TRAP_PF, asm_exc_page_fault), |
72 | #endif |
73 | #ifdef CONFIG_INTEL_TDX_GUEST |
74 | INTG(X86_TRAP_VE, asm_exc_virtualization_exception), |
75 | #endif |
76 | }; |
77 | |
78 | /* |
79 | * The default IDT entries which are set up in trap_init() before |
80 | * cpu_init() is invoked. Interrupt stacks cannot be used at that point and |
81 | * the traps which use them are reinitialized with IST after cpu_init() has |
82 | * set up TSS. |
83 | */ |
84 | static const __initconst struct idt_data def_idts[] = { |
85 | INTG(X86_TRAP_DE, asm_exc_divide_error), |
86 | ISTG(X86_TRAP_NMI, asm_exc_nmi, IST_INDEX_NMI), |
87 | INTG(X86_TRAP_BR, asm_exc_bounds), |
88 | INTG(X86_TRAP_UD, asm_exc_invalid_op), |
89 | INTG(X86_TRAP_NM, asm_exc_device_not_available), |
90 | INTG(X86_TRAP_OLD_MF, asm_exc_coproc_segment_overrun), |
91 | INTG(X86_TRAP_TS, asm_exc_invalid_tss), |
92 | INTG(X86_TRAP_NP, asm_exc_segment_not_present), |
93 | INTG(X86_TRAP_SS, asm_exc_stack_segment), |
94 | INTG(X86_TRAP_GP, asm_exc_general_protection), |
95 | INTG(X86_TRAP_SPURIOUS, asm_exc_spurious_interrupt_bug), |
96 | INTG(X86_TRAP_MF, asm_exc_coprocessor_error), |
97 | INTG(X86_TRAP_AC, asm_exc_alignment_check), |
98 | INTG(X86_TRAP_XF, asm_exc_simd_coprocessor_error), |
99 | |
100 | #ifdef CONFIG_X86_32 |
101 | TSKG(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS), |
102 | #else |
103 | ISTG(X86_TRAP_DF, asm_exc_double_fault, IST_INDEX_DF), |
104 | #endif |
105 | ISTG(X86_TRAP_DB, asm_exc_debug, IST_INDEX_DB), |
106 | |
107 | #ifdef CONFIG_X86_MCE |
108 | ISTG(X86_TRAP_MC, asm_exc_machine_check, IST_INDEX_MCE), |
109 | #endif |
110 | |
111 | #ifdef CONFIG_X86_CET |
112 | INTG(X86_TRAP_CP, asm_exc_control_protection), |
113 | #endif |
114 | |
115 | #ifdef CONFIG_AMD_MEM_ENCRYPT |
116 | ISTG(X86_TRAP_VC, asm_exc_vmm_communication, IST_INDEX_VC), |
117 | #endif |
118 | |
119 | SYSG(X86_TRAP_OF, asm_exc_overflow), |
120 | }; |
121 | |
122 | static const struct idt_data ia32_idt[] __initconst = { |
123 | #if defined(CONFIG_IA32_EMULATION) |
124 | SYSG(IA32_SYSCALL_VECTOR, asm_int80_emulation), |
125 | #elif defined(CONFIG_X86_32) |
126 | SYSG(IA32_SYSCALL_VECTOR, entry_INT80_32), |
127 | #endif |
128 | }; |
129 | |
130 | /* |
131 | * The APIC and SMP idt entries |
132 | */ |
133 | static const __initconst struct idt_data apic_idts[] = { |
134 | #ifdef CONFIG_SMP |
135 | INTG(RESCHEDULE_VECTOR, asm_sysvec_reschedule_ipi), |
136 | INTG(CALL_FUNCTION_VECTOR, asm_sysvec_call_function), |
137 | INTG(CALL_FUNCTION_SINGLE_VECTOR, asm_sysvec_call_function_single), |
138 | INTG(REBOOT_VECTOR, asm_sysvec_reboot), |
139 | #endif |
140 | |
141 | #ifdef CONFIG_X86_THERMAL_VECTOR |
142 | INTG(THERMAL_APIC_VECTOR, asm_sysvec_thermal), |
143 | #endif |
144 | |
145 | #ifdef CONFIG_X86_MCE_THRESHOLD |
146 | INTG(THRESHOLD_APIC_VECTOR, asm_sysvec_threshold), |
147 | #endif |
148 | |
149 | #ifdef CONFIG_X86_MCE_AMD |
150 | INTG(DEFERRED_ERROR_VECTOR, asm_sysvec_deferred_error), |
151 | #endif |
152 | |
153 | #ifdef CONFIG_X86_LOCAL_APIC |
154 | INTG(LOCAL_TIMER_VECTOR, asm_sysvec_apic_timer_interrupt), |
155 | INTG(X86_PLATFORM_IPI_VECTOR, asm_sysvec_x86_platform_ipi), |
156 | # if IS_ENABLED(CONFIG_KVM) |
157 | INTG(POSTED_INTR_VECTOR, asm_sysvec_kvm_posted_intr_ipi), |
158 | INTG(POSTED_INTR_WAKEUP_VECTOR, asm_sysvec_kvm_posted_intr_wakeup_ipi), |
159 | INTG(POSTED_INTR_NESTED_VECTOR, asm_sysvec_kvm_posted_intr_nested_ipi), |
160 | # endif |
161 | # ifdef CONFIG_IRQ_WORK |
162 | INTG(IRQ_WORK_VECTOR, asm_sysvec_irq_work), |
163 | # endif |
164 | INTG(SPURIOUS_APIC_VECTOR, asm_sysvec_spurious_apic_interrupt), |
165 | INTG(ERROR_APIC_VECTOR, asm_sysvec_error_interrupt), |
166 | #endif |
167 | }; |
168 | |
169 | /* Must be page-aligned because the real IDT is used in the cpu entry area */ |
170 | static gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss; |
171 | |
172 | static struct desc_ptr idt_descr __ro_after_init = { |
173 | .size = IDT_TABLE_SIZE - 1, |
174 | .address = (unsigned long) idt_table, |
175 | }; |
176 | |
177 | void load_current_idt(void) |
178 | { |
179 | lockdep_assert_irqs_disabled(); |
180 | load_idt(dtr: &idt_descr); |
181 | } |
182 | |
183 | #ifdef CONFIG_X86_F00F_BUG |
184 | bool idt_is_f00f_address(unsigned long address) |
185 | { |
186 | return ((address - idt_descr.address) >> 3) == 6; |
187 | } |
188 | #endif |
189 | |
190 | static __init void |
191 | idt_setup_from_table(gate_desc *idt, const struct idt_data *t, int size, bool sys) |
192 | { |
193 | gate_desc desc; |
194 | |
195 | for (; size > 0; t++, size--) { |
196 | idt_init_desc(gate: &desc, d: t); |
197 | write_idt_entry(dt: idt, entry: t->vector, g: &desc); |
198 | if (sys) |
199 | set_bit(nr: t->vector, addr: system_vectors); |
200 | } |
201 | } |
202 | |
203 | static __init void set_intr_gate(unsigned int n, const void *addr) |
204 | { |
205 | struct idt_data data; |
206 | |
207 | init_idt_data(data: &data, n, addr); |
208 | |
209 | idt_setup_from_table(idt: idt_table, t: &data, size: 1, sys: false); |
210 | } |
211 | |
212 | /** |
213 | * idt_setup_early_traps - Initialize the idt table with early traps |
214 | * |
215 | * On X8664 these traps do not use interrupt stacks as they can't work |
216 | * before cpu_init() is invoked and sets up TSS. The IST variants are |
217 | * installed after that. |
218 | */ |
219 | void __init idt_setup_early_traps(void) |
220 | { |
221 | idt_setup_from_table(idt: idt_table, t: early_idts, ARRAY_SIZE(early_idts), |
222 | sys: true); |
223 | load_idt(dtr: &idt_descr); |
224 | } |
225 | |
226 | /** |
227 | * idt_setup_traps - Initialize the idt table with default traps |
228 | */ |
229 | void __init idt_setup_traps(void) |
230 | { |
231 | idt_setup_from_table(idt: idt_table, t: def_idts, ARRAY_SIZE(def_idts), sys: true); |
232 | |
233 | if (ia32_enabled()) |
234 | idt_setup_from_table(idt: idt_table, t: ia32_idt, ARRAY_SIZE(ia32_idt), sys: true); |
235 | } |
236 | |
237 | #ifdef CONFIG_X86_64 |
238 | /* |
239 | * Early traps running on the DEFAULT_STACK because the other interrupt |
240 | * stacks work only after cpu_init(). |
241 | */ |
242 | static const __initconst struct idt_data early_pf_idts[] = { |
243 | INTG(X86_TRAP_PF, asm_exc_page_fault), |
244 | }; |
245 | |
246 | /** |
247 | * idt_setup_early_pf - Initialize the idt table with early pagefault handler |
248 | * |
249 | * On X8664 this does not use interrupt stacks as they can't work before |
250 | * cpu_init() is invoked and sets up TSS. The IST variant is installed |
251 | * after that. |
252 | * |
253 | * Note, that X86_64 cannot install the real #PF handler in |
254 | * idt_setup_early_traps() because the memory initialization needs the #PF |
255 | * handler from the early_idt_handler_array to initialize the early page |
256 | * tables. |
257 | */ |
258 | void __init idt_setup_early_pf(void) |
259 | { |
260 | idt_setup_from_table(idt: idt_table, t: early_pf_idts, |
261 | ARRAY_SIZE(early_pf_idts), sys: true); |
262 | } |
263 | #endif |
264 | |
265 | static void __init idt_map_in_cea(void) |
266 | { |
267 | /* |
268 | * Set the IDT descriptor to a fixed read-only location in the cpu |
269 | * entry area, so that the "sidt" instruction will not leak the |
270 | * location of the kernel, and to defend the IDT against arbitrary |
271 | * memory write vulnerabilities. |
272 | */ |
273 | cea_set_pte(CPU_ENTRY_AREA_RO_IDT_VADDR, __pa_symbol(idt_table), |
274 | PAGE_KERNEL_RO); |
275 | idt_descr.address = CPU_ENTRY_AREA_RO_IDT; |
276 | } |
277 | |
278 | /** |
279 | * idt_setup_apic_and_irq_gates - Setup APIC/SMP and normal interrupt gates |
280 | */ |
281 | void __init idt_setup_apic_and_irq_gates(void) |
282 | { |
283 | int i = FIRST_EXTERNAL_VECTOR; |
284 | void *entry; |
285 | |
286 | idt_setup_from_table(idt: idt_table, t: apic_idts, ARRAY_SIZE(apic_idts), sys: true); |
287 | |
288 | for_each_clear_bit_from(i, system_vectors, FIRST_SYSTEM_VECTOR) { |
289 | entry = irq_entries_start + IDT_ALIGN * (i - FIRST_EXTERNAL_VECTOR); |
290 | set_intr_gate(n: i, addr: entry); |
291 | } |
292 | |
293 | #ifdef CONFIG_X86_LOCAL_APIC |
294 | for_each_clear_bit_from(i, system_vectors, NR_VECTORS) { |
295 | /* |
296 | * Don't set the non assigned system vectors in the |
297 | * system_vectors bitmap. Otherwise they show up in |
298 | * /proc/interrupts. |
299 | */ |
300 | entry = spurious_entries_start + IDT_ALIGN * (i - FIRST_SYSTEM_VECTOR); |
301 | set_intr_gate(n: i, addr: entry); |
302 | } |
303 | #endif |
304 | /* Map IDT into CPU entry area and reload it. */ |
305 | idt_map_in_cea(); |
306 | load_idt(dtr: &idt_descr); |
307 | |
308 | /* Make the IDT table read only */ |
309 | set_memory_ro(addr: (unsigned long)&idt_table, numpages: 1); |
310 | |
311 | idt_setup_done = true; |
312 | } |
313 | |
314 | /** |
315 | * idt_setup_early_handler - Initializes the idt table with early handlers |
316 | */ |
317 | void __init idt_setup_early_handler(void) |
318 | { |
319 | int i; |
320 | |
321 | for (i = 0; i < NUM_EXCEPTION_VECTORS; i++) |
322 | set_intr_gate(n: i, addr: early_idt_handler_array[i]); |
323 | #ifdef CONFIG_X86_32 |
324 | for ( ; i < NR_VECTORS; i++) |
325 | set_intr_gate(i, early_ignore_irq); |
326 | #endif |
327 | load_idt(dtr: &idt_descr); |
328 | } |
329 | |
330 | /** |
331 | * idt_invalidate - Invalidate interrupt descriptor table |
332 | */ |
333 | void idt_invalidate(void) |
334 | { |
335 | static const struct desc_ptr idt = { .address = 0, .size = 0 }; |
336 | |
337 | load_idt(dtr: &idt); |
338 | } |
339 | |
340 | void __init idt_install_sysvec(unsigned int n, const void *function) |
341 | { |
342 | if (WARN_ON(n < FIRST_SYSTEM_VECTOR)) |
343 | return; |
344 | |
345 | if (WARN_ON(idt_setup_done)) |
346 | return; |
347 | |
348 | if (!WARN_ON(test_and_set_bit(n, system_vectors))) |
349 | set_intr_gate(n, addr: function); |
350 | } |
351 | |