1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ahci.c - AHCI SATA support
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/dma-mapping.h>
26#include <linux/device.h>
27#include <linux/dmi.h>
28#include <linux/gfp.h>
29#include <scsi/scsi_host.h>
30#include <scsi/scsi_cmnd.h>
31#include <linux/libata.h>
32#include <linux/ahci-remap.h>
33#include <linux/io-64-nonatomic-lo-hi.h>
34#include "ahci.h"
35
36#define DRV_NAME "ahci"
37#define DRV_VERSION "3.0"
38
39enum {
40 AHCI_PCI_BAR_STA2X11 = 0,
41 AHCI_PCI_BAR_CAVIUM = 0,
42 AHCI_PCI_BAR_LOONGSON = 0,
43 AHCI_PCI_BAR_ENMOTUS = 2,
44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
45 AHCI_PCI_BAR_STANDARD = 5,
46};
47
48enum board_ids {
49 /* board IDs by feature in alphabetical order */
50 board_ahci,
51 board_ahci_43bit_dma,
52 board_ahci_ign_iferr,
53 board_ahci_no_debounce_delay,
54 board_ahci_no_msi,
55 /*
56 * board_ahci_pcs_quirk is for legacy Intel platforms.
57 * Modern Intel platforms should use board_ahci instead.
58 * (Some modern Intel platforms might have been added with
59 * board_ahci_pcs_quirk, however, we cannot change them to board_ahci
60 * without testing that the platform actually works without the quirk.)
61 */
62 board_ahci_pcs_quirk,
63 board_ahci_pcs_quirk_no_devslp,
64 board_ahci_pcs_quirk_no_sntf,
65 board_ahci_yes_fbs,
66
67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_al,
69 board_ahci_avn,
70 board_ahci_mcp65,
71 board_ahci_mcp77,
72 board_ahci_mcp89,
73 board_ahci_mv,
74 board_ahci_sb600,
75 board_ahci_sb700, /* for SB700 and SB800 */
76 board_ahci_vt8251,
77
78 /* aliases */
79 board_ahci_mcp_linux = board_ahci_mcp65,
80 board_ahci_mcp67 = board_ahci_mcp65,
81 board_ahci_mcp73 = board_ahci_mcp65,
82 board_ahci_mcp79 = board_ahci_mcp77,
83};
84
85static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
86static void ahci_remove_one(struct pci_dev *dev);
87static void ahci_shutdown_one(struct pci_dev *dev);
88static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
89static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
92 unsigned long deadline);
93static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
94static bool is_mcp89_apple(struct pci_dev *pdev);
95static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
96 unsigned long deadline);
97#ifdef CONFIG_PM
98static int ahci_pci_device_runtime_suspend(struct device *dev);
99static int ahci_pci_device_runtime_resume(struct device *dev);
100#ifdef CONFIG_PM_SLEEP
101static int ahci_pci_device_suspend(struct device *dev);
102static int ahci_pci_device_resume(struct device *dev);
103#endif
104#endif /* CONFIG_PM */
105
106static const struct scsi_host_template ahci_sht = {
107 AHCI_SHT("ahci"),
108};
109
110static struct ata_port_operations ahci_vt8251_ops = {
111 .inherits = &ahci_ops,
112 .hardreset = ahci_vt8251_hardreset,
113};
114
115static struct ata_port_operations ahci_p5wdh_ops = {
116 .inherits = &ahci_ops,
117 .hardreset = ahci_p5wdh_hardreset,
118};
119
120static struct ata_port_operations ahci_avn_ops = {
121 .inherits = &ahci_ops,
122 .hardreset = ahci_avn_hardreset,
123};
124
125static const struct ata_port_info ahci_port_info[] = {
126 /* by features */
127 [board_ahci] = {
128 .flags = AHCI_FLAG_COMMON,
129 .pio_mask = ATA_PIO4,
130 .udma_mask = ATA_UDMA6,
131 .port_ops = &ahci_ops,
132 },
133 [board_ahci_43bit_dma] = {
134 AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
139 },
140 [board_ahci_ign_iferr] = {
141 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
142 .flags = AHCI_FLAG_COMMON,
143 .pio_mask = ATA_PIO4,
144 .udma_mask = ATA_UDMA6,
145 .port_ops = &ahci_ops,
146 },
147 [board_ahci_no_debounce_delay] = {
148 .flags = AHCI_FLAG_COMMON,
149 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
153 },
154 [board_ahci_no_msi] = {
155 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
156 .flags = AHCI_FLAG_COMMON,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
160 },
161 [board_ahci_pcs_quirk] = {
162 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK),
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
167 },
168 [board_ahci_pcs_quirk_no_devslp] = {
169 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK |
170 AHCI_HFLAG_NO_DEVSLP),
171 .flags = AHCI_FLAG_COMMON,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
175 },
176 [board_ahci_pcs_quirk_no_sntf] = {
177 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK |
178 AHCI_HFLAG_NO_SNTF),
179 .flags = AHCI_FLAG_COMMON,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_ops,
183 },
184 [board_ahci_yes_fbs] = {
185 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
186 .flags = AHCI_FLAG_COMMON,
187 .pio_mask = ATA_PIO4,
188 .udma_mask = ATA_UDMA6,
189 .port_ops = &ahci_ops,
190 },
191 /* by chipsets */
192 [board_ahci_al] = {
193 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
194 .flags = AHCI_FLAG_COMMON,
195 .pio_mask = ATA_PIO4,
196 .udma_mask = ATA_UDMA6,
197 .port_ops = &ahci_ops,
198 },
199 [board_ahci_avn] = {
200 AHCI_HFLAGS (AHCI_HFLAG_INTEL_PCS_QUIRK),
201 .flags = AHCI_FLAG_COMMON,
202 .pio_mask = ATA_PIO4,
203 .udma_mask = ATA_UDMA6,
204 .port_ops = &ahci_avn_ops,
205 },
206 [board_ahci_mcp65] = {
207 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
208 AHCI_HFLAG_YES_NCQ),
209 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
210 .pio_mask = ATA_PIO4,
211 .udma_mask = ATA_UDMA6,
212 .port_ops = &ahci_ops,
213 },
214 [board_ahci_mcp77] = {
215 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
216 .flags = AHCI_FLAG_COMMON,
217 .pio_mask = ATA_PIO4,
218 .udma_mask = ATA_UDMA6,
219 .port_ops = &ahci_ops,
220 },
221 [board_ahci_mcp89] = {
222 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
223 .flags = AHCI_FLAG_COMMON,
224 .pio_mask = ATA_PIO4,
225 .udma_mask = ATA_UDMA6,
226 .port_ops = &ahci_ops,
227 },
228 [board_ahci_mv] = {
229 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
230 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
231 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
232 .pio_mask = ATA_PIO4,
233 .udma_mask = ATA_UDMA6,
234 .port_ops = &ahci_ops,
235 },
236 [board_ahci_sb600] = {
237 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
238 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
239 AHCI_HFLAG_32BIT_ONLY),
240 .flags = AHCI_FLAG_COMMON,
241 .pio_mask = ATA_PIO4,
242 .udma_mask = ATA_UDMA6,
243 .port_ops = &ahci_pmp_retry_srst_ops,
244 },
245 [board_ahci_sb700] = { /* for SB700 and SB800 */
246 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
247 .flags = AHCI_FLAG_COMMON,
248 .pio_mask = ATA_PIO4,
249 .udma_mask = ATA_UDMA6,
250 .port_ops = &ahci_pmp_retry_srst_ops,
251 },
252 [board_ahci_vt8251] = {
253 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
254 .flags = AHCI_FLAG_COMMON,
255 .pio_mask = ATA_PIO4,
256 .udma_mask = ATA_UDMA6,
257 .port_ops = &ahci_vt8251_ops,
258 },
259};
260
261static const struct pci_device_id ahci_pci_tbl[] = {
262 /* Intel */
263 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci_pcs_quirk }, /* Comet Lake PCH-H RAID */
264 { PCI_VDEVICE(INTEL, 0x2652), board_ahci_pcs_quirk }, /* ICH6 */
265 { PCI_VDEVICE(INTEL, 0x2653), board_ahci_pcs_quirk }, /* ICH6M */
266 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci_pcs_quirk }, /* ICH7 */
267 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci_pcs_quirk }, /* ICH7M */
268 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci_pcs_quirk }, /* ICH7R */
269 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
270 { PCI_VDEVICE(INTEL, 0x2681), board_ahci_pcs_quirk }, /* ESB2 */
271 { PCI_VDEVICE(INTEL, 0x2682), board_ahci_pcs_quirk }, /* ESB2 */
272 { PCI_VDEVICE(INTEL, 0x2683), board_ahci_pcs_quirk }, /* ESB2 */
273 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci_pcs_quirk }, /* ICH7-M DH */
274 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pcs_quirk }, /* ICH8 */
275 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pcs_quirk_no_sntf }, /* ICH8/Lewisburg RAID*/
276 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pcs_quirk }, /* ICH8 */
277 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pcs_quirk }, /* ICH8M */
278 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pcs_quirk }, /* ICH8M */
279 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pcs_quirk }, /* ICH9 */
280 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pcs_quirk }, /* ICH9 */
281 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pcs_quirk }, /* ICH9 */
282 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pcs_quirk }, /* ICH9 */
283 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pcs_quirk }, /* ICH9 */
284 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pcs_quirk }, /* ICH9M */
285 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pcs_quirk }, /* ICH9M */
286 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pcs_quirk }, /* ICH9M */
287 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pcs_quirk }, /* ICH9M */
288 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pcs_quirk }, /* ICH9M */
289 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pcs_quirk }, /* ICH9 */
290 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pcs_quirk }, /* ICH9M */
291 { PCI_VDEVICE(INTEL, 0x502a), board_ahci_pcs_quirk }, /* Tolapai */
292 { PCI_VDEVICE(INTEL, 0x502b), board_ahci_pcs_quirk }, /* Tolapai */
293 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci_pcs_quirk }, /* ICH10 */
294 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci_pcs_quirk }, /* ICH10 */
295 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci_pcs_quirk }, /* ICH10 */
296 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci_pcs_quirk }, /* PCH AHCI */
297 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci_pcs_quirk }, /* PCH AHCI */
298 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci_pcs_quirk }, /* PCH RAID */
299 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci_pcs_quirk }, /* PCH RAID */
300 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_pcs_quirk }, /* PCH M AHCI */
301 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci_pcs_quirk }, /* PCH RAID */
302 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_pcs_quirk }, /* PCH M RAID */
303 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci_pcs_quirk }, /* PCH AHCI */
304 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
311 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
312 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
313 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
316 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
317 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
318 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
319 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
320 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
321 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
322 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
323 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
324 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci_pcs_quirk }, /* CPT AHCI */
325 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_pcs_quirk }, /* CPT M AHCI */
326 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci_pcs_quirk }, /* CPT RAID */
327 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_pcs_quirk }, /* CPT M RAID */
328 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci_pcs_quirk }, /* CPT RAID */
329 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci_pcs_quirk }, /* CPT RAID */
330 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci_pcs_quirk }, /* PBG AHCI */
331 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci_pcs_quirk }, /* PBG RAID */
332 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci_pcs_quirk }, /* PBG RAID */
333 { PCI_VDEVICE(INTEL, 0x2323), board_ahci_pcs_quirk }, /* DH89xxCC AHCI */
334 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci_pcs_quirk }, /* Panther Point AHCI */
335 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_pcs_quirk }, /* Panther M AHCI */
336 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci_pcs_quirk }, /* Panther Point RAID */
337 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci_pcs_quirk }, /* Panther Point RAID */
338 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci_pcs_quirk }, /* Panther Point RAID */
339 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_pcs_quirk }, /* Panther M RAID */
340 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci_pcs_quirk }, /* Panther Point RAID */
341 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci_pcs_quirk }, /* Lynx Point AHCI */
342 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_pcs_quirk }, /* Lynx M AHCI */
343 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci_pcs_quirk }, /* Lynx Point RAID */
344 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_pcs_quirk }, /* Lynx M RAID */
345 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci_pcs_quirk }, /* Lynx Point RAID */
346 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_pcs_quirk }, /* Lynx M RAID */
347 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci_pcs_quirk }, /* Lynx Point RAID */
348 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_pcs_quirk }, /* Lynx M RAID */
349 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_pcs_quirk }, /* Lynx LP AHCI */
350 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_pcs_quirk }, /* Lynx LP AHCI */
351 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_pcs_quirk }, /* Lynx LP RAID */
352 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_pcs_quirk }, /* Lynx LP RAID */
353 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_pcs_quirk }, /* Lynx LP RAID */
354 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_pcs_quirk }, /* Lynx LP RAID */
355 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_pcs_quirk }, /* Lynx LP RAID */
356 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_pcs_quirk }, /* Lynx LP RAID */
357 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_pcs_quirk }, /* Cannon Lake PCH-LP AHCI */
358 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci_pcs_quirk }, /* Avoton AHCI */
359 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci_pcs_quirk }, /* Avoton AHCI */
360 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci_pcs_quirk }, /* Avoton RAID */
361 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci_pcs_quirk }, /* Avoton RAID */
362 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci_pcs_quirk }, /* Avoton RAID */
363 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci_pcs_quirk }, /* Avoton RAID */
364 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci_pcs_quirk }, /* Avoton RAID */
365 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci_pcs_quirk }, /* Avoton RAID */
366 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
367 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
368 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
369 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
370 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
371 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
372 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
373 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
374 { PCI_VDEVICE(INTEL, 0x2823), board_ahci_pcs_quirk }, /* Wellsburg/Lewisburg AHCI*/
375 { PCI_VDEVICE(INTEL, 0x2826), board_ahci_pcs_quirk }, /* *burg SATA0 'RAID' */
376 { PCI_VDEVICE(INTEL, 0x2827), board_ahci_pcs_quirk }, /* *burg SATA1 'RAID' */
377 { PCI_VDEVICE(INTEL, 0x282f), board_ahci_pcs_quirk }, /* *burg SATA2 'RAID' */
378 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
379 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
380 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
381 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci_pcs_quirk }, /* Rocket Lake PCH-H RAID */
382 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci_pcs_quirk }, /* Wellsburg AHCI */
383 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci_pcs_quirk }, /* Wellsburg RAID */
384 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci_pcs_quirk }, /* Wellsburg RAID */
385 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci_pcs_quirk }, /* Wellsburg RAID */
386 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci_pcs_quirk }, /* Wellsburg AHCI */
387 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci_pcs_quirk }, /* Wellsburg RAID */
388 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci_pcs_quirk }, /* Wellsburg RAID */
389 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci_pcs_quirk }, /* Wellsburg RAID */
390 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci_pcs_quirk }, /* Coleto Creek AHCI */
391 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_pcs_quirk }, /* Wildcat LP AHCI */
392 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_pcs_quirk }, /* Wildcat LP RAID */
393 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_pcs_quirk }, /* Wildcat LP RAID */
394 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_pcs_quirk }, /* Wildcat LP RAID */
395 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci_pcs_quirk }, /* 9 Series AHCI */
396 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_pcs_quirk }, /* 9 Series M AHCI */
397 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci_pcs_quirk }, /* 9 Series RAID */
398 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_pcs_quirk }, /* 9 Series M RAID */
399 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci_pcs_quirk }, /* 9 Series RAID */
400 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_pcs_quirk }, /* 9 Series M RAID */
401 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci_pcs_quirk }, /* 9 Series RAID */
402 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_pcs_quirk }, /* 9 Series M RAID */
403 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_pcs_quirk }, /* Sunrise LP AHCI */
404 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_pcs_quirk }, /* Sunrise LP RAID */
405 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_pcs_quirk }, /* Sunrise LP RAID */
406 { PCI_VDEVICE(INTEL, 0xa102), board_ahci_pcs_quirk }, /* Sunrise Point-H AHCI */
407 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_pcs_quirk }, /* Sunrise M AHCI */
408 { PCI_VDEVICE(INTEL, 0xa105), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
409 { PCI_VDEVICE(INTEL, 0xa106), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
410 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_pcs_quirk }, /* Sunrise M RAID */
411 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci_pcs_quirk }, /* Sunrise Point-H RAID */
412 { PCI_VDEVICE(INTEL, 0xa182), board_ahci_pcs_quirk }, /* Lewisburg AHCI*/
413 { PCI_VDEVICE(INTEL, 0xa186), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
414 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
415 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
416 { PCI_VDEVICE(INTEL, 0xa202), board_ahci_pcs_quirk }, /* Lewisburg AHCI*/
417 { PCI_VDEVICE(INTEL, 0xa206), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
418 { PCI_VDEVICE(INTEL, 0xa252), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
419 { PCI_VDEVICE(INTEL, 0xa256), board_ahci_pcs_quirk }, /* Lewisburg RAID*/
420 { PCI_VDEVICE(INTEL, 0xa356), board_ahci_pcs_quirk }, /* Cannon Lake PCH-H RAID */
421 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci_pcs_quirk }, /* Comet Lake-H RAID */
422 { PCI_VDEVICE(INTEL, 0xa386), board_ahci_pcs_quirk }, /* Comet Lake PCH-V RAID */
423 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_pcs_quirk }, /* Bay Trail AHCI */
424 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_pcs_quirk_no_devslp }, /* Bay Trail AHCI */
425 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_pcs_quirk }, /* Cherry Tr. AHCI */
426 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_pcs_quirk }, /* ApolloLake AHCI */
427 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_pcs_quirk }, /* Ice Lake LP AHCI */
428 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_pcs_quirk }, /* Comet Lake PCH-U AHCI */
429 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_pcs_quirk }, /* Comet Lake PCH RAID */
430 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
431 { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_pcs_quirk }, /* Elkhart Lake AHCI */
432 { PCI_VDEVICE(INTEL, 0x7ae2), board_ahci_pcs_quirk }, /* Alder Lake-P AHCI */
433
434 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
435 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
436 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
437 /* JMicron 362B and 362C have an AHCI function with IDE class code */
438 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
439 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
440 /* May need to update quirk_jmicron_async_suspend() for additions */
441
442 /* ATI */
443 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
444 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
445 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
446 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
447 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
448 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
449 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
450
451 /* Amazon's Annapurna Labs support */
452 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
453 .class = PCI_CLASS_STORAGE_SATA_AHCI,
454 .class_mask = 0xffffff,
455 board_ahci_al },
456 /* AMD */
457 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
458 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
459 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
460 { PCI_VDEVICE(AMD, 0x7901), board_ahci }, /* AMD Green Sardine */
461 /* AMD is using RAID class only for ahci controllers */
462 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
463 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
464
465 /* Dell S140/S150 */
466 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
467 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci_pcs_quirk },
468
469 /* VIA */
470 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
471 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
472
473 /* NVIDIA */
474 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
475 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
476 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
477 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
478 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
479 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
480 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
481 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
482 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
483 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
484 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
485 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
486 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
487 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
488 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
489 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
490 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
491 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
492 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
493 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
494 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
495 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
496 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
497 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
498 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
499 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
500 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
501 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
502 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
503 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
504 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
505 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
506 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
507 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
508 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
509 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
510 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
511 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
512 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
513 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
514 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
515 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
516 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
517 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
518 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
519 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
520 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
521 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
522 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
523 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
524 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
525 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
526 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
527 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
528 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
529 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
530 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
531 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
532 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
533 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
534 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
535 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
536 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
537 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
538 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
539 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
540 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
541 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
542 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
543 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
544 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
545 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
546 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
547 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
548 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
549 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
550 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
551 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
552 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
553 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
554 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
555 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
556 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
557 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
558
559 /* SiS */
560 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
561 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
562 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
563
564 /* ST Microelectronics */
565 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
566
567 /* Marvell */
568 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
569 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
570 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
571 .class = PCI_CLASS_STORAGE_SATA_AHCI,
572 .class_mask = 0xffffff,
573 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
574 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
575 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
576 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
577 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
578 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
579 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
580 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
581 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
582 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
583 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
584 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
585 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
586 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
587 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
588 .driver_data = board_ahci_yes_fbs },
589 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
590 .driver_data = board_ahci_yes_fbs },
591 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
592 .driver_data = board_ahci_yes_fbs },
593 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
594 .driver_data = board_ahci_yes_fbs },
595 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
596 .driver_data = board_ahci_no_debounce_delay },
597 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
598 .driver_data = board_ahci_yes_fbs },
599 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
600 .driver_data = board_ahci_yes_fbs },
601
602 /* Promise */
603 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
604 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
605
606 /* ASMedia */
607 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci_43bit_dma }, /* ASM1060 */
608 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci_43bit_dma }, /* ASM1060 */
609 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci_43bit_dma }, /* ASM1061 */
610 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci_43bit_dma }, /* ASM1061/1062 */
611 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci_43bit_dma }, /* ASM1061R */
612 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci_43bit_dma }, /* ASM1062R */
613 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci_43bit_dma }, /* ASM1062+JMB575 */
614 { PCI_VDEVICE(ASMEDIA, 0x1062), board_ahci }, /* ASM1062A */
615 { PCI_VDEVICE(ASMEDIA, 0x1064), board_ahci }, /* ASM1064 */
616 { PCI_VDEVICE(ASMEDIA, 0x1164), board_ahci }, /* ASM1164 */
617 { PCI_VDEVICE(ASMEDIA, 0x1165), board_ahci }, /* ASM1165 */
618 { PCI_VDEVICE(ASMEDIA, 0x1166), board_ahci }, /* ASM1166 */
619
620 /*
621 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
622 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
623 */
624 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_no_msi },
625 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_no_msi },
626
627 /* Enmotus */
628 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
629
630 /* Loongson */
631 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
632
633 /* Generic, PCI class code for AHCI */
634 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
635 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
636
637 { } /* terminate list */
638};
639
640static const struct dev_pm_ops ahci_pci_pm_ops = {
641 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
642 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
643 ahci_pci_device_runtime_resume, NULL)
644};
645
646static struct pci_driver ahci_pci_driver = {
647 .name = DRV_NAME,
648 .id_table = ahci_pci_tbl,
649 .probe = ahci_init_one,
650 .remove = ahci_remove_one,
651 .shutdown = ahci_shutdown_one,
652 .driver = {
653 .pm = &ahci_pci_pm_ops,
654 },
655};
656
657#if IS_ENABLED(CONFIG_PATA_MARVELL)
658static int marvell_enable;
659#else
660static int marvell_enable = 1;
661#endif
662module_param(marvell_enable, int, 0644);
663MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
664
665static int mobile_lpm_policy = -1;
666module_param(mobile_lpm_policy, int, 0644);
667MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
668
669static char *ahci_mask_port_map;
670module_param_named(mask_port_map, ahci_mask_port_map, charp, 0444);
671MODULE_PARM_DESC(mask_port_map,
672 "32-bits port map masks to ignore controllers ports. "
673 "Valid values are: "
674 "\"<mask>\" to apply the same mask to all AHCI controller "
675 "devices, and \"<pci_dev>=<mask>,<pci_dev>=<mask>,...\" to "
676 "specify different masks for the controllers specified, "
677 "where <pci_dev> is the PCI ID of an AHCI controller in the "
678 "form \"domain:bus:dev.func\"");
679
680static void ahci_apply_port_map_mask(struct device *dev,
681 struct ahci_host_priv *hpriv, char *mask_s)
682{
683 unsigned int mask;
684
685 if (kstrtouint(s: mask_s, base: 0, res: &mask)) {
686 dev_err(dev, "Invalid port map mask\n");
687 return;
688 }
689
690 hpriv->mask_port_map = mask;
691}
692
693static void ahci_get_port_map_mask(struct device *dev,
694 struct ahci_host_priv *hpriv)
695{
696 char *param, *end, *str, *mask_s;
697 char *name;
698
699 if (!strlen(ahci_mask_port_map))
700 return;
701
702 str = kstrdup(s: ahci_mask_port_map, GFP_KERNEL);
703 if (!str)
704 return;
705
706 /* Handle single mask case */
707 if (!strchr(str, '=')) {
708 ahci_apply_port_map_mask(dev, hpriv, mask_s: str);
709 goto free;
710 }
711
712 /*
713 * Mask list case: parse the parameter to apply the mask only if
714 * the device name matches.
715 */
716 param = str;
717 end = param + strlen(param);
718 while (param && param < end && *param) {
719 name = param;
720 param = strchr(name, '=');
721 if (!param)
722 break;
723
724 *param = '\0';
725 param++;
726 if (param >= end)
727 break;
728
729 if (strcmp(dev_name(dev), name) != 0) {
730 param = strchr(param, ',');
731 if (param)
732 param++;
733 continue;
734 }
735
736 mask_s = param;
737 param = strchr(mask_s, ',');
738 if (param) {
739 *param = '\0';
740 param++;
741 }
742
743 ahci_apply_port_map_mask(dev, hpriv, mask_s);
744 }
745
746free:
747 kfree(objp: str);
748}
749
750static void ahci_pci_save_initial_config(struct pci_dev *pdev,
751 struct ahci_host_priv *hpriv)
752{
753 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
754 dev_info(&pdev->dev, "JMB361 has only one port\n");
755 hpriv->saved_port_map = 1;
756 }
757
758 /*
759 * Temporary Marvell 6145 hack: PATA port presence
760 * is asserted through the standard AHCI port
761 * presence register, as bit 4 (counting from 0)
762 */
763 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
764 if (pdev->device == 0x6121)
765 hpriv->mask_port_map = 0x3;
766 else
767 hpriv->mask_port_map = 0xf;
768 dev_info(&pdev->dev,
769 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
770 }
771
772 /* Handle port map masks passed as module parameter. */
773 if (ahci_mask_port_map)
774 ahci_get_port_map_mask(dev: &pdev->dev, hpriv);
775
776 ahci_save_initial_config(dev: &pdev->dev, hpriv);
777}
778
779static int ahci_pci_reset_controller(struct ata_host *host)
780{
781 struct pci_dev *pdev = to_pci_dev(host->dev);
782 struct ahci_host_priv *hpriv = host->private_data;
783 int rc;
784
785 rc = ahci_reset_controller(host);
786 if (rc)
787 return rc;
788
789 /*
790 * If platform firmware failed to enable ports, try to enable
791 * them here.
792 */
793 ahci_intel_pcs_quirk(pdev, hpriv);
794
795 return 0;
796}
797
798static void ahci_pci_init_controller(struct ata_host *host)
799{
800 struct ahci_host_priv *hpriv = host->private_data;
801 struct pci_dev *pdev = to_pci_dev(host->dev);
802 void __iomem *port_mmio;
803 u32 tmp;
804 int mv;
805
806 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
807 if (pdev->device == 0x6121)
808 mv = 2;
809 else
810 mv = 4;
811 port_mmio = __ahci_port_base(hpriv, port_no: mv);
812
813 writel(val: 0, addr: port_mmio + PORT_IRQ_MASK);
814
815 /* clear port IRQ */
816 tmp = readl(addr: port_mmio + PORT_IRQ_STAT);
817 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
818 if (tmp)
819 writel(val: tmp, addr: port_mmio + PORT_IRQ_STAT);
820 }
821
822 ahci_init_controller(host);
823}
824
825static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
826 unsigned long deadline)
827{
828 struct ata_port *ap = link->ap;
829 struct ahci_host_priv *hpriv = ap->host->private_data;
830 bool online;
831 int rc;
832
833 hpriv->stop_engine(ap);
834
835 rc = sata_link_hardreset(link, timing: sata_ehc_deb_timing(ehc: &link->eh_context),
836 deadline, online: &online, NULL);
837
838 hpriv->start_engine(ap);
839
840 /* vt8251 doesn't clear BSY on signature FIS reception,
841 * request follow-up softreset.
842 */
843 return online ? -EAGAIN : rc;
844}
845
846static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
847 unsigned long deadline)
848{
849 struct ata_port *ap = link->ap;
850 struct ahci_port_priv *pp = ap->private_data;
851 struct ahci_host_priv *hpriv = ap->host->private_data;
852 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
853 struct ata_taskfile tf;
854 bool online;
855 int rc;
856
857 hpriv->stop_engine(ap);
858
859 /* clear D2H reception area to properly wait for D2H FIS */
860 ata_tf_init(dev: link->device, tf: &tf);
861 tf.status = ATA_BUSY;
862 ata_tf_to_fis(tf: &tf, pmp: 0, is_cmd: 0, fis: d2h_fis);
863
864 rc = sata_link_hardreset(link, timing: sata_ehc_deb_timing(ehc: &link->eh_context),
865 deadline, online: &online, NULL);
866
867 hpriv->start_engine(ap);
868
869 /* The pseudo configuration device on SIMG4726 attached to
870 * ASUS P5W-DH Deluxe doesn't send signature FIS after
871 * hardreset if no device is attached to the first downstream
872 * port && the pseudo device locks up on SRST w/ PMP==0. To
873 * work around this, wait for !BSY only briefly. If BSY isn't
874 * cleared, perform CLO and proceed to IDENTIFY (achieved by
875 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
876 *
877 * Wait for two seconds. Devices attached to downstream port
878 * which can't process the following IDENTIFY after this will
879 * have to be reset again. For most cases, this should
880 * suffice while making probing snappish enough.
881 */
882 if (online) {
883 rc = ata_wait_after_reset(link, deadline: jiffies + 2 * HZ,
884 check_ready: ahci_check_ready);
885 if (rc)
886 ahci_kick_engine(ap);
887 }
888 return rc;
889}
890
891/*
892 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
893 *
894 * It has been observed with some SSDs that the timing of events in the
895 * link synchronization phase can leave the port in a state that can not
896 * be recovered by a SATA-hard-reset alone. The failing signature is
897 * SStatus.DET stuck at 1 ("Device presence detected but Phy
898 * communication not established"). It was found that unloading and
899 * reloading the driver when this problem occurs allows the drive
900 * connection to be recovered (DET advanced to 0x3). The critical
901 * component of reloading the driver is that the port state machines are
902 * reset by bouncing "port enable" in the AHCI PCS configuration
903 * register. So, reproduce that effect by bouncing a port whenever we
904 * see DET==1 after a reset.
905 */
906static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
907 unsigned long deadline)
908{
909 const unsigned int *timing = sata_ehc_deb_timing(ehc: &link->eh_context);
910 struct ata_port *ap = link->ap;
911 struct ahci_port_priv *pp = ap->private_data;
912 struct ahci_host_priv *hpriv = ap->host->private_data;
913 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
914 unsigned long tmo = deadline - jiffies;
915 struct ata_taskfile tf;
916 bool online;
917 int rc, i;
918
919 hpriv->stop_engine(ap);
920
921 for (i = 0; i < 2; i++) {
922 u16 val;
923 u32 sstatus;
924 int port = ap->port_no;
925 struct ata_host *host = ap->host;
926 struct pci_dev *pdev = to_pci_dev(host->dev);
927
928 /* clear D2H reception area to properly wait for D2H FIS */
929 ata_tf_init(dev: link->device, tf: &tf);
930 tf.status = ATA_BUSY;
931 ata_tf_to_fis(tf: &tf, pmp: 0, is_cmd: 0, fis: d2h_fis);
932
933 rc = sata_link_hardreset(link, timing, deadline, online: &online,
934 check_ready: ahci_check_ready);
935
936 if (sata_scr_read(link, reg: SCR_STATUS, val: &sstatus) != 0 ||
937 (sstatus & 0xf) != 1)
938 break;
939
940 ata_link_info(link, "avn bounce port%d\n", port);
941
942 pci_read_config_word(dev: pdev, where: 0x92, val: &val);
943 val &= ~(1 << port);
944 pci_write_config_word(dev: pdev, where: 0x92, val);
945 ata_msleep(ap, msecs: 1000);
946 val |= 1 << port;
947 pci_write_config_word(dev: pdev, where: 0x92, val);
948 deadline += tmo;
949 }
950
951 hpriv->start_engine(ap);
952
953 if (online)
954 *class = ahci_dev_classify(ap);
955
956 return rc;
957}
958
959
960#ifdef CONFIG_PM
961static void ahci_pci_disable_interrupts(struct ata_host *host)
962{
963 struct ahci_host_priv *hpriv = host->private_data;
964 void __iomem *mmio = hpriv->mmio;
965 u32 ctl;
966
967 /* AHCI spec rev1.1 section 8.3.3:
968 * Software must disable interrupts prior to requesting a
969 * transition of the HBA to D3 state.
970 */
971 ctl = readl(addr: mmio + HOST_CTL);
972 ctl &= ~HOST_IRQ_EN;
973 writel(val: ctl, addr: mmio + HOST_CTL);
974 readl(addr: mmio + HOST_CTL); /* flush */
975}
976
977static int ahci_pci_device_runtime_suspend(struct device *dev)
978{
979 struct pci_dev *pdev = to_pci_dev(dev);
980 struct ata_host *host = pci_get_drvdata(pdev);
981
982 ahci_pci_disable_interrupts(host);
983 return 0;
984}
985
986static int ahci_pci_device_runtime_resume(struct device *dev)
987{
988 struct pci_dev *pdev = to_pci_dev(dev);
989 struct ata_host *host = pci_get_drvdata(pdev);
990 int rc;
991
992 rc = ahci_pci_reset_controller(host);
993 if (rc)
994 return rc;
995 ahci_pci_init_controller(host);
996 return 0;
997}
998
999#ifdef CONFIG_PM_SLEEP
1000static int ahci_pci_device_suspend(struct device *dev)
1001{
1002 struct pci_dev *pdev = to_pci_dev(dev);
1003 struct ata_host *host = pci_get_drvdata(pdev);
1004 struct ahci_host_priv *hpriv = host->private_data;
1005
1006 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
1007 dev_err(&pdev->dev,
1008 "BIOS update required for suspend/resume\n");
1009 return -EIO;
1010 }
1011
1012 ahci_pci_disable_interrupts(host);
1013 ata_host_suspend(host, PMSG_SUSPEND);
1014 return 0;
1015}
1016
1017static int ahci_pci_device_resume(struct device *dev)
1018{
1019 struct pci_dev *pdev = to_pci_dev(dev);
1020 struct ata_host *host = pci_get_drvdata(pdev);
1021 int rc;
1022
1023 /* Apple BIOS helpfully mangles the registers on resume */
1024 if (is_mcp89_apple(pdev))
1025 ahci_mcp89_apple_enable(pdev);
1026
1027 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1028 rc = ahci_pci_reset_controller(host);
1029 if (rc)
1030 return rc;
1031
1032 ahci_pci_init_controller(host);
1033 }
1034
1035 ata_host_resume(host);
1036
1037 return 0;
1038}
1039#endif
1040
1041#endif /* CONFIG_PM */
1042
1043static int ahci_configure_dma_masks(struct pci_dev *pdev,
1044 struct ahci_host_priv *hpriv)
1045{
1046 int dma_bits;
1047 int rc;
1048
1049 if (hpriv->cap & HOST_CAP_64) {
1050 dma_bits = 64;
1051 if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY)
1052 dma_bits = 43;
1053 } else {
1054 dma_bits = 32;
1055 }
1056
1057 /*
1058 * If the device fixup already set the dma_mask to some non-standard
1059 * value, don't extend it here. This happens on STA2X11, for example.
1060 *
1061 * XXX: manipulating the DMA mask from platform code is completely
1062 * bogus, platform code should use dev->bus_dma_limit instead..
1063 */
1064 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
1065 return 0;
1066
1067 rc = dma_set_mask_and_coherent(dev: &pdev->dev, DMA_BIT_MASK(dma_bits));
1068 if (rc)
1069 dev_err(&pdev->dev, "DMA enable failed\n");
1070 return rc;
1071}
1072
1073static void ahci_pci_print_info(struct ata_host *host)
1074{
1075 struct pci_dev *pdev = to_pci_dev(host->dev);
1076 u16 cc;
1077 const char *scc_s;
1078
1079 pci_read_config_word(dev: pdev, where: 0x0a, val: &cc);
1080 if (cc == PCI_CLASS_STORAGE_IDE)
1081 scc_s = "IDE";
1082 else if (cc == PCI_CLASS_STORAGE_SATA)
1083 scc_s = "SATA";
1084 else if (cc == PCI_CLASS_STORAGE_RAID)
1085 scc_s = "RAID";
1086 else
1087 scc_s = "unknown";
1088
1089 ahci_print_info(host, scc_s);
1090}
1091
1092/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
1093 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
1094 * support PMP and the 4726 either directly exports the device
1095 * attached to the first downstream port or acts as a hardware storage
1096 * controller and emulate a single ATA device (can be RAID 0/1 or some
1097 * other configuration).
1098 *
1099 * When there's no device attached to the first downstream port of the
1100 * 4726, "Config Disk" appears, which is a pseudo ATA device to
1101 * configure the 4726. However, ATA emulation of the device is very
1102 * lame. It doesn't send signature D2H Reg FIS after the initial
1103 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
1104 *
1105 * The following function works around the problem by always using
1106 * hardreset on the port and not depending on receiving signature FIS
1107 * afterward. If signature FIS isn't received soon, ATA class is
1108 * assumed without follow-up softreset.
1109 */
1110static void ahci_p5wdh_workaround(struct ata_host *host)
1111{
1112 static const struct dmi_system_id sysids[] = {
1113 {
1114 .ident = "P5W DH Deluxe",
1115 .matches = {
1116 DMI_MATCH(DMI_SYS_VENDOR,
1117 "ASUSTEK COMPUTER INC"),
1118 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1119 },
1120 },
1121 { }
1122 };
1123 struct pci_dev *pdev = to_pci_dev(host->dev);
1124
1125 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1126 dmi_check_system(list: sysids)) {
1127 struct ata_port *ap = host->ports[1];
1128
1129 dev_info(&pdev->dev,
1130 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1131
1132 ap->ops = &ahci_p5wdh_ops;
1133 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1134 }
1135}
1136
1137/*
1138 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1139 * booting in BIOS compatibility mode. We restore the registers but not ID.
1140 */
1141static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1142{
1143 u32 val;
1144
1145 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1146
1147 pci_read_config_dword(dev: pdev, where: 0xf8, val: &val);
1148 val |= 1 << 0x1b;
1149 /* the following changes the device ID, but appears not to affect function */
1150 /* val = (val & ~0xf0000000) | 0x80000000; */
1151 pci_write_config_dword(dev: pdev, where: 0xf8, val);
1152
1153 pci_read_config_dword(dev: pdev, where: 0x54c, val: &val);
1154 val |= 1 << 0xc;
1155 pci_write_config_dword(dev: pdev, where: 0x54c, val);
1156
1157 pci_read_config_dword(dev: pdev, where: 0x4a4, val: &val);
1158 val &= 0xff;
1159 val |= 0x01060100;
1160 pci_write_config_dword(dev: pdev, where: 0x4a4, val);
1161
1162 pci_read_config_dword(dev: pdev, where: 0x54c, val: &val);
1163 val &= ~(1 << 0xc);
1164 pci_write_config_dword(dev: pdev, where: 0x54c, val);
1165
1166 pci_read_config_dword(dev: pdev, where: 0xf8, val: &val);
1167 val &= ~(1 << 0x1b);
1168 pci_write_config_dword(dev: pdev, where: 0xf8, val);
1169}
1170
1171static bool is_mcp89_apple(struct pci_dev *pdev)
1172{
1173 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1174 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1175 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1176 pdev->subsystem_device == 0xcb89;
1177}
1178
1179/* only some SB600 ahci controllers can do 64bit DMA */
1180static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1181{
1182 static const struct dmi_system_id sysids[] = {
1183 /*
1184 * The oldest version known to be broken is 0901 and
1185 * working is 1501 which was released on 2007-10-26.
1186 * Enable 64bit DMA on 1501 and anything newer.
1187 *
1188 * Please read bko#9412 for more info.
1189 */
1190 {
1191 .ident = "ASUS M2A-VM",
1192 .matches = {
1193 DMI_MATCH(DMI_BOARD_VENDOR,
1194 "ASUSTeK Computer INC."),
1195 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1196 },
1197 .driver_data = "20071026", /* yyyymmdd */
1198 },
1199 /*
1200 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1201 * support 64bit DMA.
1202 *
1203 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1204 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1205 * This spelling mistake was fixed in BIOS version 1.5, so
1206 * 1.5 and later have the Manufacturer as
1207 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1208 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1209 *
1210 * BIOS versions earlier than 1.9 had a Board Product Name
1211 * DMI field of "MS-7376". This was changed to be
1212 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1213 * match on DMI_BOARD_NAME of "MS-7376".
1214 */
1215 {
1216 .ident = "MSI K9A2 Platinum",
1217 .matches = {
1218 DMI_MATCH(DMI_BOARD_VENDOR,
1219 "MICRO-STAR INTER"),
1220 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1221 },
1222 },
1223 /*
1224 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1225 * 64bit DMA.
1226 *
1227 * This board also had the typo mentioned above in the
1228 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1229 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1230 */
1231 {
1232 .ident = "MSI K9AGM2",
1233 .matches = {
1234 DMI_MATCH(DMI_BOARD_VENDOR,
1235 "MICRO-STAR INTER"),
1236 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1237 },
1238 },
1239 /*
1240 * All BIOS versions for the Asus M3A support 64bit DMA.
1241 * (all release versions from 0301 to 1206 were tested)
1242 */
1243 {
1244 .ident = "ASUS M3A",
1245 .matches = {
1246 DMI_MATCH(DMI_BOARD_VENDOR,
1247 "ASUSTeK Computer INC."),
1248 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1249 },
1250 },
1251 { }
1252 };
1253 const struct dmi_system_id *match;
1254 int year, month, date;
1255 char buf[9];
1256
1257 match = dmi_first_match(list: sysids);
1258 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1259 !match)
1260 return false;
1261
1262 if (!match->driver_data)
1263 goto enable_64bit;
1264
1265 dmi_get_date(field: DMI_BIOS_DATE, yearp: &year, monthp: &month, dayp: &date);
1266 snprintf(buf, size: sizeof(buf), fmt: "%04d%02d%02d", year, month, date);
1267
1268 if (strcmp(buf, match->driver_data) >= 0)
1269 goto enable_64bit;
1270 else {
1271 dev_warn(&pdev->dev,
1272 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1273 match->ident);
1274 return false;
1275 }
1276
1277enable_64bit:
1278 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1279 return true;
1280}
1281
1282static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1283{
1284 static const struct dmi_system_id broken_systems[] = {
1285 {
1286 .ident = "HP Compaq nx6310",
1287 .matches = {
1288 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1289 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1290 },
1291 /* PCI slot number of the controller */
1292 .driver_data = (void *)0x1FUL,
1293 },
1294 {
1295 .ident = "HP Compaq 6720s",
1296 .matches = {
1297 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1298 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1299 },
1300 /* PCI slot number of the controller */
1301 .driver_data = (void *)0x1FUL,
1302 },
1303
1304 { } /* terminate list */
1305 };
1306 const struct dmi_system_id *dmi = dmi_first_match(list: broken_systems);
1307
1308 if (dmi) {
1309 unsigned long slot = (unsigned long)dmi->driver_data;
1310 /* apply the quirk only to on-board controllers */
1311 return slot == PCI_SLOT(pdev->devfn);
1312 }
1313
1314 return false;
1315}
1316
1317static bool ahci_broken_suspend(struct pci_dev *pdev)
1318{
1319 static const struct dmi_system_id sysids[] = {
1320 /*
1321 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1322 * to the harddisk doesn't become online after
1323 * resuming from STR. Warn and fail suspend.
1324 *
1325 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1326 *
1327 * Use dates instead of versions to match as HP is
1328 * apparently recycling both product and version
1329 * strings.
1330 *
1331 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1332 */
1333 {
1334 .ident = "dv4",
1335 .matches = {
1336 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1337 DMI_MATCH(DMI_PRODUCT_NAME,
1338 "HP Pavilion dv4 Notebook PC"),
1339 },
1340 .driver_data = "20090105", /* F.30 */
1341 },
1342 {
1343 .ident = "dv5",
1344 .matches = {
1345 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1346 DMI_MATCH(DMI_PRODUCT_NAME,
1347 "HP Pavilion dv5 Notebook PC"),
1348 },
1349 .driver_data = "20090506", /* F.16 */
1350 },
1351 {
1352 .ident = "dv6",
1353 .matches = {
1354 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1355 DMI_MATCH(DMI_PRODUCT_NAME,
1356 "HP Pavilion dv6 Notebook PC"),
1357 },
1358 .driver_data = "20090423", /* F.21 */
1359 },
1360 {
1361 .ident = "HDX18",
1362 .matches = {
1363 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1364 DMI_MATCH(DMI_PRODUCT_NAME,
1365 "HP HDX18 Notebook PC"),
1366 },
1367 .driver_data = "20090430", /* F.23 */
1368 },
1369 /*
1370 * Acer eMachines G725 has the same problem. BIOS
1371 * V1.03 is known to be broken. V3.04 is known to
1372 * work. Between, there are V1.06, V2.06 and V3.03
1373 * that we don't have much idea about. For now,
1374 * blacklist anything older than V3.04.
1375 *
1376 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1377 */
1378 {
1379 .ident = "G725",
1380 .matches = {
1381 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1382 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1383 },
1384 .driver_data = "20091216", /* V3.04 */
1385 },
1386 { } /* terminate list */
1387 };
1388 const struct dmi_system_id *dmi = dmi_first_match(list: sysids);
1389 int year, month, date;
1390 char buf[9];
1391
1392 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1393 return false;
1394
1395 dmi_get_date(field: DMI_BIOS_DATE, yearp: &year, monthp: &month, dayp: &date);
1396 snprintf(buf, size: sizeof(buf), fmt: "%04d%02d%02d", year, month, date);
1397
1398 return strcmp(buf, dmi->driver_data) < 0;
1399}
1400
1401static bool ahci_broken_lpm(struct pci_dev *pdev)
1402{
1403 static const struct dmi_system_id sysids[] = {
1404 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1405 {
1406 .matches = {
1407 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1408 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1409 },
1410 .driver_data = "20180406", /* 1.31 */
1411 },
1412 {
1413 .matches = {
1414 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1415 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1416 },
1417 .driver_data = "20180420", /* 1.28 */
1418 },
1419 {
1420 .matches = {
1421 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1422 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1423 },
1424 .driver_data = "20180315", /* 1.33 */
1425 },
1426 {
1427 .matches = {
1428 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1429 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1430 },
1431 /*
1432 * Note date based on release notes, 2.35 has been
1433 * reported to be good, but I've been unable to get
1434 * a hold of the reporter to get the DMI BIOS date.
1435 * TODO: fix this.
1436 */
1437 .driver_data = "20180310", /* 2.35 */
1438 },
1439 { } /* terminate list */
1440 };
1441 const struct dmi_system_id *dmi = dmi_first_match(list: sysids);
1442 int year, month, date;
1443 char buf[9];
1444
1445 if (!dmi)
1446 return false;
1447
1448 dmi_get_date(field: DMI_BIOS_DATE, yearp: &year, monthp: &month, dayp: &date);
1449 snprintf(buf, size: sizeof(buf), fmt: "%04d%02d%02d", year, month, date);
1450
1451 return strcmp(buf, dmi->driver_data) < 0;
1452}
1453
1454static bool ahci_broken_online(struct pci_dev *pdev)
1455{
1456#define ENCODE_BUSDEVFN(bus, slot, func) \
1457 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1458 static const struct dmi_system_id sysids[] = {
1459 /*
1460 * There are several gigabyte boards which use
1461 * SIMG5723s configured as hardware RAID. Certain
1462 * 5723 firmware revisions shipped there keep the link
1463 * online but fail to answer properly to SRST or
1464 * IDENTIFY when no device is attached downstream
1465 * causing libata to retry quite a few times leading
1466 * to excessive detection delay.
1467 *
1468 * As these firmwares respond to the second reset try
1469 * with invalid device signature, considering unknown
1470 * sig as offline works around the problem acceptably.
1471 */
1472 {
1473 .ident = "EP45-DQ6",
1474 .matches = {
1475 DMI_MATCH(DMI_BOARD_VENDOR,
1476 "Gigabyte Technology Co., Ltd."),
1477 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1478 },
1479 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1480 },
1481 {
1482 .ident = "EP45-DS5",
1483 .matches = {
1484 DMI_MATCH(DMI_BOARD_VENDOR,
1485 "Gigabyte Technology Co., Ltd."),
1486 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1487 },
1488 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1489 },
1490 { } /* terminate list */
1491 };
1492#undef ENCODE_BUSDEVFN
1493 const struct dmi_system_id *dmi = dmi_first_match(list: sysids);
1494 unsigned int val;
1495
1496 if (!dmi)
1497 return false;
1498
1499 val = (unsigned long)dmi->driver_data;
1500
1501 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1502}
1503
1504#ifdef CONFIG_ATA_ACPI
1505static void ahci_gtf_filter_workaround(struct ata_host *host)
1506{
1507 static const struct dmi_system_id sysids[] = {
1508 /*
1509 * Aspire 3810T issues a bunch of SATA enable commands
1510 * via _GTF including an invalid one and one which is
1511 * rejected by the device. Among the successful ones
1512 * is FPDMA non-zero offset enable which when enabled
1513 * only on the drive side leads to NCQ command
1514 * failures. Filter it out.
1515 */
1516 {
1517 .ident = "Aspire 3810T",
1518 .matches = {
1519 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1520 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1521 },
1522 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1523 },
1524 { }
1525 };
1526 const struct dmi_system_id *dmi = dmi_first_match(list: sysids);
1527 unsigned int filter;
1528 int i;
1529
1530 if (!dmi)
1531 return;
1532
1533 filter = (unsigned long)dmi->driver_data;
1534 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1535 filter, dmi->ident);
1536
1537 for (i = 0; i < host->n_ports; i++) {
1538 struct ata_port *ap = host->ports[i];
1539 struct ata_link *link;
1540 struct ata_device *dev;
1541
1542 ata_for_each_link(link, ap, EDGE)
1543 ata_for_each_dev(dev, link, ALL)
1544 dev->gtf_filter |= filter;
1545 }
1546}
1547#else
1548static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1549{}
1550#endif
1551
1552/*
1553 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1554 * as DUMMY, or detected but eventually get a "link down" and never get up
1555 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1556 * port_map may hold a value of 0x00.
1557 *
1558 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1559 * and can significantly reduce the occurrence of the problem.
1560 *
1561 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1562 */
1563static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1564 struct pci_dev *pdev)
1565{
1566 static const struct dmi_system_id sysids[] = {
1567 {
1568 .ident = "Acer Switch Alpha 12",
1569 .matches = {
1570 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1571 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1572 },
1573 },
1574 { }
1575 };
1576
1577 if (dmi_check_system(list: sysids)) {
1578 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1579 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1580 hpriv->port_map = 0x7;
1581 hpriv->cap = 0xC734FF02;
1582 }
1583 }
1584}
1585
1586#ifdef CONFIG_ARM64
1587/*
1588 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1589 * Workaround is to make sure all pending IRQs are served before leaving
1590 * handler.
1591 */
1592static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1593{
1594 struct ata_host *host = dev_instance;
1595 struct ahci_host_priv *hpriv;
1596 unsigned int rc = 0;
1597 void __iomem *mmio;
1598 u32 irq_stat, irq_masked;
1599 unsigned int handled = 1;
1600
1601 hpriv = host->private_data;
1602 mmio = hpriv->mmio;
1603 irq_stat = readl(mmio + HOST_IRQ_STAT);
1604 if (!irq_stat)
1605 return IRQ_NONE;
1606
1607 do {
1608 irq_masked = irq_stat & hpriv->port_map;
1609 spin_lock(&host->lock);
1610 rc = ahci_handle_port_intr(host, irq_masked);
1611 if (!rc)
1612 handled = 0;
1613 writel(irq_stat, mmio + HOST_IRQ_STAT);
1614 irq_stat = readl(mmio + HOST_IRQ_STAT);
1615 spin_unlock(&host->lock);
1616 } while (irq_stat);
1617
1618 return IRQ_RETVAL(handled);
1619}
1620#endif
1621
1622static void ahci_remap_check(struct pci_dev *pdev, int bar,
1623 struct ahci_host_priv *hpriv)
1624{
1625 int i;
1626 u32 cap;
1627
1628 /*
1629 * Check if this device might have remapped nvme devices.
1630 */
1631 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1632 pci_resource_len(pdev, bar) < SZ_512K ||
1633 bar != AHCI_PCI_BAR_STANDARD ||
1634 !(readl(addr: hpriv->mmio + AHCI_VSCAP) & 1))
1635 return;
1636
1637 cap = readq(addr: hpriv->mmio + AHCI_REMAP_CAP);
1638 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1639 if ((cap & (1 << i)) == 0)
1640 continue;
1641 if (readl(addr: hpriv->mmio + ahci_remap_dcc(i))
1642 != PCI_CLASS_STORAGE_EXPRESS)
1643 continue;
1644
1645 /* We've found a remapped device */
1646 hpriv->remapped_nvme++;
1647 }
1648
1649 if (!hpriv->remapped_nvme)
1650 return;
1651
1652 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1653 hpriv->remapped_nvme);
1654 dev_warn(&pdev->dev,
1655 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1656
1657 /*
1658 * Don't rely on the msi-x capability in the remap case,
1659 * share the legacy interrupt across ahci and remapped devices.
1660 */
1661 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1662}
1663
1664static int ahci_get_irq_vector(struct ata_host *host, int port)
1665{
1666 return pci_irq_vector(to_pci_dev(host->dev), nr: port);
1667}
1668
1669static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1670 struct ahci_host_priv *hpriv)
1671{
1672 int nvec;
1673
1674 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1675 return -ENODEV;
1676
1677 /*
1678 * If number of MSIs is less than number of ports then Sharing Last
1679 * Message mode could be enforced. In this case assume that advantage
1680 * of multipe MSIs is negated and use single MSI mode instead.
1681 */
1682 if (n_ports > 1) {
1683 nvec = pci_alloc_irq_vectors(dev: pdev, min_vecs: n_ports, INT_MAX,
1684 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1685 if (nvec > 0) {
1686 if (!(readl(addr: hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1687 hpriv->get_irq_vector = ahci_get_irq_vector;
1688 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1689 return nvec;
1690 }
1691
1692 /*
1693 * Fallback to single MSI mode if the controller
1694 * enforced MRSM mode.
1695 */
1696 printk(KERN_INFO
1697 "ahci: MRSM is on, fallback to single MSI\n");
1698 pci_free_irq_vectors(dev: pdev);
1699 }
1700 }
1701
1702 /*
1703 * If the host is not capable of supporting per-port vectors, fall
1704 * back to single MSI before finally attempting single MSI-X.
1705 */
1706 nvec = pci_alloc_irq_vectors(dev: pdev, min_vecs: 1, max_vecs: 1, PCI_IRQ_MSI);
1707 if (nvec == 1)
1708 return nvec;
1709 return pci_alloc_irq_vectors(dev: pdev, min_vecs: 1, max_vecs: 1, PCI_IRQ_MSIX);
1710}
1711
1712static void ahci_mark_external_port(struct ata_port *ap)
1713{
1714 struct ahci_host_priv *hpriv = ap->host->private_data;
1715 void __iomem *port_mmio = ahci_port_base(ap);
1716 u32 tmp;
1717
1718 /* mark external ports (hotplug-capable, eSATA) */
1719 tmp = readl(addr: port_mmio + PORT_CMD);
1720 if (((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) ||
1721 (tmp & PORT_CMD_HPCP))
1722 ap->pflags |= ATA_PFLAG_EXTERNAL;
1723}
1724
1725static void ahci_update_initial_lpm_policy(struct ata_port *ap)
1726{
1727 struct ahci_host_priv *hpriv = ap->host->private_data;
1728 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1729
1730 /*
1731 * AHCI contains a known incompatibility between LPM and hot-plug
1732 * removal events, see 7.3.1 Hot Plug Removal Detection and Power
1733 * Management Interaction in AHCI 1.3.1. Therefore, do not enable
1734 * LPM if the port advertises itself as an external port.
1735 */
1736 if (ap->pflags & ATA_PFLAG_EXTERNAL)
1737 return;
1738
1739 /* user modified policy via module param */
1740 if (mobile_lpm_policy != -1) {
1741 policy = mobile_lpm_policy;
1742 goto update_policy;
1743 }
1744
1745 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) {
1746 if (hpriv->cap & HOST_CAP_PART)
1747 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1748 else if (hpriv->cap & HOST_CAP_SSC)
1749 policy = ATA_LPM_MIN_POWER;
1750 }
1751
1752update_policy:
1753 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1754 ap->target_lpm_policy = policy;
1755}
1756
1757static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1758{
1759 u16 tmp16;
1760
1761 if (!(hpriv->flags & AHCI_HFLAG_INTEL_PCS_QUIRK))
1762 return;
1763
1764 /*
1765 * port_map is determined from PORTS_IMPL PCI register which is
1766 * implemented as write or write-once register. If the register
1767 * isn't programmed, ahci automatically generates it from number
1768 * of ports, which is good enough for PCS programming. It is
1769 * otherwise expected that platform firmware enables the ports
1770 * before the OS boots.
1771 */
1772 pci_read_config_word(dev: pdev, where: PCS_6, val: &tmp16);
1773 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1774 tmp16 |= hpriv->port_map;
1775 pci_write_config_word(dev: pdev, where: PCS_6, val: tmp16);
1776 }
1777}
1778
1779static ssize_t remapped_nvme_show(struct device *dev,
1780 struct device_attribute *attr,
1781 char *buf)
1782{
1783 struct ata_host *host = dev_get_drvdata(dev);
1784 struct ahci_host_priv *hpriv = host->private_data;
1785
1786 return sysfs_emit(buf, fmt: "%u\n", hpriv->remapped_nvme);
1787}
1788
1789static DEVICE_ATTR_RO(remapped_nvme);
1790
1791static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1792{
1793 unsigned int board_id = ent->driver_data;
1794 struct ata_port_info pi = ahci_port_info[board_id];
1795 const struct ata_port_info *ppi[] = { &pi, NULL };
1796 struct device *dev = &pdev->dev;
1797 struct ahci_host_priv *hpriv;
1798 struct ata_host *host;
1799 int n_ports, i, rc;
1800 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1801
1802 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1803
1804 ata_print_version_once(&pdev->dev, DRV_VERSION);
1805
1806 /* The AHCI driver can only drive the SATA ports, the PATA driver
1807 can drive them all so if both drivers are selected make sure
1808 AHCI stays out of the way */
1809 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1810 return -ENODEV;
1811
1812 /* Apple BIOS on MCP89 prevents us using AHCI */
1813 if (is_mcp89_apple(pdev))
1814 ahci_mcp89_apple_enable(pdev);
1815
1816 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1817 * At the moment, we can only use the AHCI mode. Let the users know
1818 * that for SAS drives they're out of luck.
1819 */
1820 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1821 dev_info(&pdev->dev,
1822 "PDC42819 can only drive SATA devices with this driver\n");
1823
1824 /* Some devices use non-standard BARs */
1825 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1826 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1827 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1828 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1829 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1830 if (pdev->device == 0xa01c)
1831 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1832 if (pdev->device == 0xa084)
1833 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1834 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1835 if (pdev->device == 0x7a08)
1836 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1837 }
1838
1839 /* acquire resources */
1840 rc = pcim_enable_device(pdev);
1841 if (rc)
1842 return rc;
1843
1844 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1845 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1846 u8 map;
1847
1848 /* ICH6s share the same PCI ID for both piix and ahci
1849 * modes. Enabling ahci mode while MAP indicates
1850 * combined mode is a bad idea. Yield to ata_piix.
1851 */
1852 pci_read_config_byte(dev: pdev, where: ICH_MAP, val: &map);
1853 if (map & 0x3) {
1854 dev_info(&pdev->dev,
1855 "controller is in combined mode, can't enable AHCI mode\n");
1856 return -ENODEV;
1857 }
1858 }
1859
1860 /* AHCI controllers often implement SFF compatible interface.
1861 * Grab all PCI BARs just in case.
1862 */
1863 rc = pcim_iomap_regions_request_all(pdev, mask: 1 << ahci_pci_bar, DRV_NAME);
1864 if (rc == -EBUSY)
1865 pcim_pin_device(pdev);
1866 if (rc)
1867 return rc;
1868
1869 hpriv = devm_kzalloc(dev, size: sizeof(*hpriv), GFP_KERNEL);
1870 if (!hpriv)
1871 return -ENOMEM;
1872 hpriv->flags |= (unsigned long)pi.private_data;
1873
1874 /* MCP65 revision A1 and A2 can't do MSI */
1875 if (board_id == board_ahci_mcp65 &&
1876 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1877 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1878
1879 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1880 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1881 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1882
1883 /* only some SB600s can do 64bit DMA */
1884 if (ahci_sb600_enable_64bit(pdev))
1885 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1886
1887 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1888
1889 /* detect remapped nvme devices */
1890 ahci_remap_check(pdev, bar: ahci_pci_bar, hpriv);
1891
1892 sysfs_add_file_to_group(kobj: &pdev->dev.kobj,
1893 attr: &dev_attr_remapped_nvme.attr,
1894 NULL);
1895
1896#ifdef CONFIG_ARM64
1897 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1898 pdev->device == 0xa235 &&
1899 pdev->revision < 0x30)
1900 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1901
1902 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1903 hpriv->irq_handler = ahci_thunderx_irq_handler;
1904#endif
1905
1906 /* save initial config */
1907 ahci_pci_save_initial_config(pdev, hpriv);
1908
1909 /* prepare host */
1910 if (hpriv->cap & HOST_CAP_NCQ) {
1911 pi.flags |= ATA_FLAG_NCQ;
1912 /*
1913 * Auto-activate optimization is supposed to be
1914 * supported on all AHCI controllers indicating NCQ
1915 * capability, but it seems to be broken on some
1916 * chipsets including NVIDIAs.
1917 */
1918 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1919 pi.flags |= ATA_FLAG_FPDMA_AA;
1920
1921 /*
1922 * All AHCI controllers should be forward-compatible
1923 * with the new auxiliary field. This code should be
1924 * conditionalized if any buggy AHCI controllers are
1925 * encountered.
1926 */
1927 pi.flags |= ATA_FLAG_FPDMA_AUX;
1928 }
1929
1930 if (hpriv->cap & HOST_CAP_PMP)
1931 pi.flags |= ATA_FLAG_PMP;
1932
1933 ahci_set_em_messages(hpriv, pi: &pi);
1934
1935 if (ahci_broken_system_poweroff(pdev)) {
1936 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1937 dev_info(&pdev->dev,
1938 "quirky BIOS, skipping spindown on poweroff\n");
1939 }
1940
1941 if (ahci_broken_lpm(pdev)) {
1942 pi.flags |= ATA_FLAG_NO_LPM;
1943 dev_warn(&pdev->dev,
1944 "BIOS update required for Link Power Management support\n");
1945 }
1946
1947 if (ahci_broken_suspend(pdev)) {
1948 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1949 dev_warn(&pdev->dev,
1950 "BIOS update required for suspend/resume\n");
1951 }
1952
1953 if (ahci_broken_online(pdev)) {
1954 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1955 dev_info(&pdev->dev,
1956 "online status unreliable, applying workaround\n");
1957 }
1958
1959
1960 /* Acer SA5-271 workaround modifies private_data */
1961 acer_sa5_271_workaround(hpriv, pdev);
1962
1963 /* CAP.NP sometimes indicate the index of the last enabled
1964 * port, at other times, that of the last possible port, so
1965 * determining the maximum port number requires looking at
1966 * both CAP.NP and port_map.
1967 */
1968 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1969
1970 host = ata_host_alloc_pinfo(dev: &pdev->dev, ppi, n_ports);
1971 if (!host)
1972 return -ENOMEM;
1973 host->private_data = hpriv;
1974
1975 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1976 /* legacy intx interrupts */
1977 pci_intx(dev: pdev, enable: 1);
1978 }
1979 hpriv->irq = pci_irq_vector(dev: pdev, nr: 0);
1980
1981 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1982 host->flags |= ATA_HOST_PARALLEL_SCAN;
1983 else
1984 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1985
1986 if (!(hpriv->cap & HOST_CAP_PART))
1987 host->flags |= ATA_HOST_NO_PART;
1988
1989 if (!(hpriv->cap & HOST_CAP_SSC))
1990 host->flags |= ATA_HOST_NO_SSC;
1991
1992 if (!(hpriv->cap2 & HOST_CAP2_SDS))
1993 host->flags |= ATA_HOST_NO_DEVSLP;
1994
1995 if (pi.flags & ATA_FLAG_EM)
1996 ahci_reset_em(host);
1997
1998 for (i = 0; i < host->n_ports; i++) {
1999 struct ata_port *ap = host->ports[i];
2000
2001 ata_port_pbar_desc(ap, bar: ahci_pci_bar, offset: -1, name: "abar");
2002 ata_port_pbar_desc(ap, bar: ahci_pci_bar,
2003 offset: 0x100 + ap->port_no * 0x80, name: "port");
2004
2005 /* set enclosure management message type */
2006 if (ap->flags & ATA_FLAG_EM)
2007 ap->em_message_type = hpriv->em_msg_type;
2008
2009 ahci_mark_external_port(ap);
2010
2011 ahci_update_initial_lpm_policy(ap);
2012
2013 /* disabled/not-implemented port */
2014 if (!(hpriv->port_map & (1 << i)))
2015 ap->ops = &ata_dummy_port_ops;
2016 }
2017
2018 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2019 ahci_p5wdh_workaround(host);
2020
2021 /* apply gtf filter quirk */
2022 ahci_gtf_filter_workaround(host);
2023
2024 /* initialize adapter */
2025 rc = ahci_configure_dma_masks(pdev, hpriv);
2026 if (rc)
2027 return rc;
2028
2029 rc = ahci_pci_reset_controller(host);
2030 if (rc)
2031 return rc;
2032
2033 ahci_pci_init_controller(host);
2034 ahci_pci_print_info(host);
2035
2036 pci_set_master(dev: pdev);
2037
2038 rc = ahci_host_activate(host, sht: &ahci_sht);
2039 if (rc)
2040 return rc;
2041
2042 pm_runtime_put_noidle(dev: &pdev->dev);
2043 return 0;
2044}
2045
2046static void ahci_shutdown_one(struct pci_dev *pdev)
2047{
2048 ata_pci_shutdown_one(pdev);
2049}
2050
2051static void ahci_remove_one(struct pci_dev *pdev)
2052{
2053 sysfs_remove_file_from_group(kobj: &pdev->dev.kobj,
2054 attr: &dev_attr_remapped_nvme.attr,
2055 NULL);
2056 pm_runtime_get_noresume(dev: &pdev->dev);
2057 ata_pci_remove_one(pdev);
2058}
2059
2060module_pci_driver(ahci_pci_driver);
2061
2062MODULE_AUTHOR("Jeff Garzik");
2063MODULE_DESCRIPTION("AHCI SATA low-level driver");
2064MODULE_LICENSE("GPL");
2065MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2066MODULE_VERSION(DRV_VERSION);
2067

source code of linux/drivers/ata/ahci.c