1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Driver for STM32 Independent Watchdog |
4 | * |
5 | * Copyright (C) STMicroelectronics 2017 |
6 | * Author: Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics. |
7 | * |
8 | * This driver is based on tegra_wdt.c |
9 | * |
10 | */ |
11 | |
12 | #include <linux/clk.h> |
13 | #include <linux/delay.h> |
14 | #include <linux/interrupt.h> |
15 | #include <linux/io.h> |
16 | #include <linux/iopoll.h> |
17 | #include <linux/kernel.h> |
18 | #include <linux/module.h> |
19 | #include <linux/of.h> |
20 | #include <linux/platform_device.h> |
21 | #include <linux/watchdog.h> |
22 | |
23 | #define DEFAULT_TIMEOUT 10 |
24 | |
25 | /* IWDG registers */ |
26 | #define IWDG_KR 0x00 /* Key register */ |
27 | #define IWDG_PR 0x04 /* Prescaler Register */ |
28 | #define IWDG_RLR 0x08 /* ReLoad Register */ |
29 | #define IWDG_SR 0x0C /* Status Register */ |
30 | #define IWDG_WINR 0x10 /* Windows Register */ |
31 | |
32 | /* IWDG_KR register bit mask */ |
33 | #define KR_KEY_RELOAD 0xAAAA /* reload counter enable */ |
34 | #define KR_KEY_ENABLE 0xCCCC /* peripheral enable */ |
35 | #define KR_KEY_EWA 0x5555 /* write access enable */ |
36 | #define KR_KEY_DWA 0x0000 /* write access disable */ |
37 | |
38 | /* IWDG_PR register */ |
39 | #define PR_SHIFT 2 |
40 | #define PR_MIN BIT(PR_SHIFT) |
41 | |
42 | /* IWDG_RLR register values */ |
43 | #define RLR_MIN 0x2 /* min value recommended */ |
44 | #define RLR_MAX GENMASK(11, 0) /* max value of reload register */ |
45 | |
46 | /* IWDG_SR register bit mask */ |
47 | #define SR_PVU BIT(0) /* Watchdog prescaler value update */ |
48 | #define SR_RVU BIT(1) /* Watchdog counter reload value update */ |
49 | |
50 | /* set timeout to 100000 us */ |
51 | #define TIMEOUT_US 100000 |
52 | #define SLEEP_US 1000 |
53 | |
54 | struct stm32_iwdg_data { |
55 | bool has_pclk; |
56 | u32 max_prescaler; |
57 | }; |
58 | |
59 | static const struct stm32_iwdg_data stm32_iwdg_data = { |
60 | .has_pclk = false, |
61 | .max_prescaler = 256, |
62 | }; |
63 | |
64 | static const struct stm32_iwdg_data stm32mp1_iwdg_data = { |
65 | .has_pclk = true, |
66 | .max_prescaler = 1024, |
67 | }; |
68 | |
69 | struct stm32_iwdg { |
70 | struct watchdog_device wdd; |
71 | const struct stm32_iwdg_data *data; |
72 | void __iomem *regs; |
73 | struct clk *clk_lsi; |
74 | struct clk *clk_pclk; |
75 | unsigned int rate; |
76 | }; |
77 | |
78 | static inline u32 reg_read(void __iomem *base, u32 reg) |
79 | { |
80 | return readl_relaxed(base + reg); |
81 | } |
82 | |
83 | static inline void reg_write(void __iomem *base, u32 reg, u32 val) |
84 | { |
85 | writel_relaxed(val, base + reg); |
86 | } |
87 | |
88 | static int stm32_iwdg_start(struct watchdog_device *wdd) |
89 | { |
90 | struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd); |
91 | u32 tout, presc, iwdg_rlr, iwdg_pr, iwdg_sr; |
92 | int ret; |
93 | |
94 | dev_dbg(wdd->parent, "%s\n" , __func__); |
95 | |
96 | tout = clamp_t(unsigned int, wdd->timeout, |
97 | wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000); |
98 | |
99 | presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1); |
100 | |
101 | /* The prescaler is align on power of 2 and start at 2 ^ PR_SHIFT. */ |
102 | presc = roundup_pow_of_two(presc); |
103 | iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT; |
104 | iwdg_rlr = ((tout * wdt->rate) / presc) - 1; |
105 | |
106 | /* enable write access */ |
107 | reg_write(base: wdt->regs, IWDG_KR, KR_KEY_EWA); |
108 | |
109 | /* set prescaler & reload registers */ |
110 | reg_write(base: wdt->regs, IWDG_PR, val: iwdg_pr); |
111 | reg_write(base: wdt->regs, IWDG_RLR, val: iwdg_rlr); |
112 | reg_write(base: wdt->regs, IWDG_KR, KR_KEY_ENABLE); |
113 | |
114 | /* wait for the registers to be updated (max 100ms) */ |
115 | ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr, |
116 | !(iwdg_sr & (SR_PVU | SR_RVU)), |
117 | SLEEP_US, TIMEOUT_US); |
118 | if (ret) { |
119 | dev_err(wdd->parent, "Fail to set prescaler, reload regs\n" ); |
120 | return ret; |
121 | } |
122 | |
123 | /* reload watchdog */ |
124 | reg_write(base: wdt->regs, IWDG_KR, KR_KEY_RELOAD); |
125 | |
126 | return 0; |
127 | } |
128 | |
129 | static int stm32_iwdg_ping(struct watchdog_device *wdd) |
130 | { |
131 | struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd); |
132 | |
133 | dev_dbg(wdd->parent, "%s\n" , __func__); |
134 | |
135 | /* reload watchdog */ |
136 | reg_write(base: wdt->regs, IWDG_KR, KR_KEY_RELOAD); |
137 | |
138 | return 0; |
139 | } |
140 | |
141 | static int stm32_iwdg_set_timeout(struct watchdog_device *wdd, |
142 | unsigned int timeout) |
143 | { |
144 | dev_dbg(wdd->parent, "%s timeout: %d sec\n" , __func__, timeout); |
145 | |
146 | wdd->timeout = timeout; |
147 | |
148 | if (watchdog_active(wdd)) |
149 | return stm32_iwdg_start(wdd); |
150 | |
151 | return 0; |
152 | } |
153 | |
154 | static void stm32_clk_disable_unprepare(void *data) |
155 | { |
156 | clk_disable_unprepare(clk: data); |
157 | } |
158 | |
159 | static int stm32_iwdg_clk_init(struct platform_device *pdev, |
160 | struct stm32_iwdg *wdt) |
161 | { |
162 | struct device *dev = &pdev->dev; |
163 | u32 ret; |
164 | |
165 | wdt->clk_lsi = devm_clk_get(dev, id: "lsi" ); |
166 | if (IS_ERR(ptr: wdt->clk_lsi)) |
167 | return dev_err_probe(dev, err: PTR_ERR(ptr: wdt->clk_lsi), fmt: "Unable to get lsi clock\n" ); |
168 | |
169 | /* optional peripheral clock */ |
170 | if (wdt->data->has_pclk) { |
171 | wdt->clk_pclk = devm_clk_get(dev, id: "pclk" ); |
172 | if (IS_ERR(ptr: wdt->clk_pclk)) |
173 | return dev_err_probe(dev, err: PTR_ERR(ptr: wdt->clk_pclk), |
174 | fmt: "Unable to get pclk clock\n" ); |
175 | |
176 | ret = clk_prepare_enable(clk: wdt->clk_pclk); |
177 | if (ret) { |
178 | dev_err(dev, "Unable to prepare pclk clock\n" ); |
179 | return ret; |
180 | } |
181 | ret = devm_add_action_or_reset(dev, |
182 | stm32_clk_disable_unprepare, |
183 | wdt->clk_pclk); |
184 | if (ret) |
185 | return ret; |
186 | } |
187 | |
188 | ret = clk_prepare_enable(clk: wdt->clk_lsi); |
189 | if (ret) { |
190 | dev_err(dev, "Unable to prepare lsi clock\n" ); |
191 | return ret; |
192 | } |
193 | ret = devm_add_action_or_reset(dev, stm32_clk_disable_unprepare, |
194 | wdt->clk_lsi); |
195 | if (ret) |
196 | return ret; |
197 | |
198 | wdt->rate = clk_get_rate(clk: wdt->clk_lsi); |
199 | |
200 | return 0; |
201 | } |
202 | |
203 | static const struct watchdog_info stm32_iwdg_info = { |
204 | .options = WDIOF_SETTIMEOUT | |
205 | WDIOF_MAGICCLOSE | |
206 | WDIOF_KEEPALIVEPING, |
207 | .identity = "STM32 Independent Watchdog" , |
208 | }; |
209 | |
210 | static const struct watchdog_ops stm32_iwdg_ops = { |
211 | .owner = THIS_MODULE, |
212 | .start = stm32_iwdg_start, |
213 | .ping = stm32_iwdg_ping, |
214 | .set_timeout = stm32_iwdg_set_timeout, |
215 | }; |
216 | |
217 | static const struct of_device_id stm32_iwdg_of_match[] = { |
218 | { .compatible = "st,stm32-iwdg" , .data = &stm32_iwdg_data }, |
219 | { .compatible = "st,stm32mp1-iwdg" , .data = &stm32mp1_iwdg_data }, |
220 | { /* end node */ } |
221 | }; |
222 | MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match); |
223 | |
224 | static int stm32_iwdg_probe(struct platform_device *pdev) |
225 | { |
226 | struct device *dev = &pdev->dev; |
227 | struct watchdog_device *wdd; |
228 | struct stm32_iwdg *wdt; |
229 | int ret; |
230 | |
231 | wdt = devm_kzalloc(dev, size: sizeof(*wdt), GFP_KERNEL); |
232 | if (!wdt) |
233 | return -ENOMEM; |
234 | |
235 | wdt->data = of_device_get_match_data(dev: &pdev->dev); |
236 | if (!wdt->data) |
237 | return -ENODEV; |
238 | |
239 | /* This is the timer base. */ |
240 | wdt->regs = devm_platform_ioremap_resource(pdev, index: 0); |
241 | if (IS_ERR(ptr: wdt->regs)) |
242 | return PTR_ERR(ptr: wdt->regs); |
243 | |
244 | ret = stm32_iwdg_clk_init(pdev, wdt); |
245 | if (ret) |
246 | return ret; |
247 | |
248 | /* Initialize struct watchdog_device. */ |
249 | wdd = &wdt->wdd; |
250 | wdd->parent = dev; |
251 | wdd->info = &stm32_iwdg_info; |
252 | wdd->ops = &stm32_iwdg_ops; |
253 | wdd->timeout = DEFAULT_TIMEOUT; |
254 | wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate); |
255 | wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler * |
256 | 1000) / wdt->rate; |
257 | |
258 | watchdog_set_drvdata(wdd, data: wdt); |
259 | watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT); |
260 | watchdog_init_timeout(wdd, timeout_parm: 0, dev); |
261 | |
262 | /* |
263 | * In case of CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is set |
264 | * (Means U-Boot/bootloaders leaves the watchdog running) |
265 | * When we get here we should make a decision to prevent |
266 | * any side effects before user space daemon will take care of it. |
267 | * The best option, taking into consideration that there is no |
268 | * way to read values back from hardware, is to enforce watchdog |
269 | * being run with deterministic values. |
270 | */ |
271 | if (IS_ENABLED(CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED)) { |
272 | ret = stm32_iwdg_start(wdd); |
273 | if (ret) |
274 | return ret; |
275 | |
276 | /* Make sure the watchdog is serviced */ |
277 | set_bit(WDOG_HW_RUNNING, addr: &wdd->status); |
278 | } |
279 | |
280 | ret = devm_watchdog_register_device(dev, wdd); |
281 | if (ret) |
282 | return ret; |
283 | |
284 | platform_set_drvdata(pdev, data: wdt); |
285 | |
286 | return 0; |
287 | } |
288 | |
289 | static struct platform_driver stm32_iwdg_driver = { |
290 | .probe = stm32_iwdg_probe, |
291 | .driver = { |
292 | .name = "iwdg" , |
293 | .of_match_table = stm32_iwdg_of_match, |
294 | }, |
295 | }; |
296 | module_platform_driver(stm32_iwdg_driver); |
297 | |
298 | MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>" ); |
299 | MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver" ); |
300 | MODULE_LICENSE("GPL v2" ); |
301 | |