| 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2021 MediaTek Inc. |
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| 4 | * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef _DT_BINDINGS_CLK_MT8195_H |
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| 8 | #define _DT_BINDINGS_CLK_MT8195_H |
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| 9 | |
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| 10 | /* TOPCKGEN */ |
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| 11 | |
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| 12 | #define CLK_TOP_AXI 0 |
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| 13 | #define CLK_TOP_SPM 1 |
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| 14 | #define CLK_TOP_SCP 2 |
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| 15 | #define CLK_TOP_BUS_AXIMEM 3 |
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| 16 | #define CLK_TOP_VPP 4 |
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| 17 | #define CLK_TOP_ETHDR 5 |
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| 18 | #define CLK_TOP_IPE 6 |
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| 19 | #define CLK_TOP_CAM 7 |
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| 20 | #define CLK_TOP_CCU 8 |
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| 21 | #define CLK_TOP_IMG 9 |
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| 22 | #define CLK_TOP_CAMTM 10 |
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| 23 | #define CLK_TOP_DSP 11 |
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| 24 | #define CLK_TOP_DSP1 12 |
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| 25 | #define CLK_TOP_DSP2 13 |
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| 26 | #define CLK_TOP_DSP3 14 |
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| 27 | #define CLK_TOP_DSP4 15 |
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| 28 | #define CLK_TOP_DSP5 16 |
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| 29 | #define CLK_TOP_DSP6 17 |
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| 30 | #define CLK_TOP_DSP7 18 |
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| 31 | #define CLK_TOP_IPU_IF 19 |
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| 32 | #define CLK_TOP_MFG_CORE_TMP 20 |
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| 33 | #define CLK_TOP_CAMTG 21 |
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| 34 | #define CLK_TOP_CAMTG2 22 |
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| 35 | #define CLK_TOP_CAMTG3 23 |
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| 36 | #define CLK_TOP_CAMTG4 24 |
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| 37 | #define CLK_TOP_CAMTG5 25 |
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| 38 | #define CLK_TOP_UART 26 |
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| 39 | #define CLK_TOP_SPI 27 |
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| 40 | #define CLK_TOP_SPIS 28 |
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| 41 | #define CLK_TOP_MSDC50_0_HCLK 29 |
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| 42 | #define CLK_TOP_MSDC50_0 30 |
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| 43 | #define CLK_TOP_MSDC30_1 31 |
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| 44 | #define CLK_TOP_MSDC30_2 32 |
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| 45 | #define CLK_TOP_INTDIR 33 |
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| 46 | #define CLK_TOP_AUD_INTBUS 34 |
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| 47 | #define CLK_TOP_AUDIO_H 35 |
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| 48 | #define CLK_TOP_PWRAP_ULPOSC 36 |
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| 49 | #define CLK_TOP_ATB 37 |
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| 50 | #define CLK_TOP_PWRMCU 38 |
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| 51 | #define CLK_TOP_DP 39 |
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| 52 | #define CLK_TOP_EDP 40 |
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| 53 | #define CLK_TOP_DPI 41 |
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| 54 | #define CLK_TOP_DISP_PWM0 42 |
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| 55 | #define CLK_TOP_DISP_PWM1 43 |
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| 56 | #define CLK_TOP_USB_TOP 44 |
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| 57 | #define CLK_TOP_SSUSB_XHCI 45 |
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| 58 | #define CLK_TOP_USB_TOP_1P 46 |
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| 59 | #define CLK_TOP_SSUSB_XHCI_1P 47 |
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| 60 | #define CLK_TOP_USB_TOP_2P 48 |
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| 61 | #define CLK_TOP_SSUSB_XHCI_2P 49 |
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| 62 | #define CLK_TOP_USB_TOP_3P 50 |
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| 63 | #define CLK_TOP_SSUSB_XHCI_3P 51 |
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| 64 | #define CLK_TOP_I2C 52 |
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| 65 | #define CLK_TOP_SENINF 53 |
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| 66 | #define CLK_TOP_SENINF1 54 |
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| 67 | #define CLK_TOP_SENINF2 55 |
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| 68 | #define CLK_TOP_SENINF3 56 |
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| 69 | #define CLK_TOP_GCPU 57 |
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| 70 | #define CLK_TOP_DXCC 58 |
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| 71 | #define CLK_TOP_DPMAIF_MAIN 59 |
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| 72 | #define CLK_TOP_AES_UFSFDE 60 |
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| 73 | #define CLK_TOP_UFS 61 |
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| 74 | #define CLK_TOP_UFS_TICK1US 62 |
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| 75 | #define CLK_TOP_UFS_MP_SAP_CFG 63 |
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| 76 | #define CLK_TOP_VENC 64 |
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| 77 | #define CLK_TOP_VDEC 65 |
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| 78 | #define CLK_TOP_PWM 66 |
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| 79 | #define CLK_TOP_MCUPM 67 |
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| 80 | #define CLK_TOP_SPMI_P_MST 68 |
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| 81 | #define CLK_TOP_SPMI_M_MST 69 |
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| 82 | #define CLK_TOP_DVFSRC 70 |
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| 83 | #define CLK_TOP_TL 71 |
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| 84 | #define CLK_TOP_TL_P1 72 |
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| 85 | #define CLK_TOP_AES_MSDCFDE 73 |
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| 86 | #define CLK_TOP_DSI_OCC 74 |
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| 87 | #define CLK_TOP_WPE_VPP 75 |
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| 88 | #define CLK_TOP_HDCP 76 |
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| 89 | #define CLK_TOP_HDCP_24M 77 |
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| 90 | #define CLK_TOP_HD20_DACR_REF_CLK 78 |
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| 91 | #define CLK_TOP_HD20_HDCP_CCLK 79 |
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| 92 | #define CLK_TOP_HDMI_XTAL 80 |
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| 93 | #define CLK_TOP_HDMI_APB 81 |
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| 94 | #define CLK_TOP_SNPS_ETH_250M 82 |
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| 95 | #define CLK_TOP_SNPS_ETH_62P4M_PTP 83 |
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| 96 | #define CLK_TOP_SNPS_ETH_50M_RMII 84 |
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| 97 | #define CLK_TOP_DGI_OUT 85 |
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| 98 | #define CLK_TOP_NNA0 86 |
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| 99 | #define CLK_TOP_NNA1 87 |
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| 100 | #define CLK_TOP_ADSP 88 |
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| 101 | #define CLK_TOP_ASM_H 89 |
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| 102 | #define CLK_TOP_ASM_M 90 |
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| 103 | #define CLK_TOP_ASM_L 91 |
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| 104 | #define CLK_TOP_APLL1 92 |
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| 105 | #define CLK_TOP_APLL2 93 |
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| 106 | #define CLK_TOP_APLL3 94 |
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| 107 | #define CLK_TOP_APLL4 95 |
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| 108 | #define CLK_TOP_APLL5 96 |
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| 109 | #define CLK_TOP_I2SO1_MCK 97 |
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| 110 | #define CLK_TOP_I2SO2_MCK 98 |
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| 111 | #define CLK_TOP_I2SI1_MCK 99 |
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| 112 | #define CLK_TOP_I2SI2_MCK 100 |
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| 113 | #define CLK_TOP_DPTX_MCK 101 |
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| 114 | #define CLK_TOP_AUD_IEC_CLK 102 |
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| 115 | #define CLK_TOP_A1SYS_HP 103 |
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| 116 | #define CLK_TOP_A2SYS_HF 104 |
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| 117 | #define CLK_TOP_A3SYS_HF 105 |
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| 118 | #define CLK_TOP_A4SYS_HF 106 |
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| 119 | #define CLK_TOP_SPINFI_BCLK 107 |
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| 120 | #define CLK_TOP_NFI1X 108 |
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| 121 | #define CLK_TOP_ECC 109 |
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| 122 | #define CLK_TOP_AUDIO_LOCAL_BUS 110 |
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| 123 | #define CLK_TOP_SPINOR 111 |
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| 124 | #define CLK_TOP_DVIO_DGI_REF 112 |
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| 125 | #define CLK_TOP_ULPOSC 113 |
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| 126 | #define CLK_TOP_ULPOSC_CORE 114 |
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| 127 | #define CLK_TOP_SRCK 115 |
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| 128 | #define CLK_TOP_MFG_CK_FAST_REF 116 |
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| 129 | #define CLK_TOP_CLK26M_D2 117 |
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| 130 | #define CLK_TOP_CLK26M_D52 118 |
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| 131 | #define CLK_TOP_IN_DGI 119 |
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| 132 | #define CLK_TOP_IN_DGI_D2 120 |
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| 133 | #define CLK_TOP_IN_DGI_D4 121 |
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| 134 | #define CLK_TOP_IN_DGI_D6 122 |
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| 135 | #define CLK_TOP_IN_DGI_D8 123 |
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| 136 | #define CLK_TOP_MAINPLL_D3 124 |
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| 137 | #define CLK_TOP_MAINPLL_D4 125 |
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| 138 | #define CLK_TOP_MAINPLL_D4_D2 126 |
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| 139 | #define CLK_TOP_MAINPLL_D4_D4 127 |
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| 140 | #define CLK_TOP_MAINPLL_D4_D8 128 |
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| 141 | #define CLK_TOP_MAINPLL_D5 129 |
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| 142 | #define CLK_TOP_MAINPLL_D5_D2 130 |
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| 143 | #define CLK_TOP_MAINPLL_D5_D4 131 |
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| 144 | #define CLK_TOP_MAINPLL_D5_D8 132 |
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| 145 | #define CLK_TOP_MAINPLL_D6 133 |
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| 146 | #define CLK_TOP_MAINPLL_D6_D2 134 |
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| 147 | #define CLK_TOP_MAINPLL_D6_D4 135 |
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| 148 | #define CLK_TOP_MAINPLL_D6_D8 136 |
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| 149 | #define CLK_TOP_MAINPLL_D7 137 |
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| 150 | #define CLK_TOP_MAINPLL_D7_D2 138 |
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| 151 | #define CLK_TOP_MAINPLL_D7_D4 139 |
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| 152 | #define CLK_TOP_MAINPLL_D7_D8 140 |
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| 153 | #define CLK_TOP_MAINPLL_D9 141 |
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| 154 | #define CLK_TOP_UNIVPLL_D2 142 |
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| 155 | #define CLK_TOP_UNIVPLL_D3 143 |
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| 156 | #define CLK_TOP_UNIVPLL_D4 144 |
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| 157 | #define CLK_TOP_UNIVPLL_D4_D2 145 |
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| 158 | #define CLK_TOP_UNIVPLL_D4_D4 146 |
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| 159 | #define CLK_TOP_UNIVPLL_D4_D8 147 |
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| 160 | #define CLK_TOP_UNIVPLL_D5 148 |
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| 161 | #define CLK_TOP_UNIVPLL_D5_D2 149 |
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| 162 | #define CLK_TOP_UNIVPLL_D5_D4 150 |
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| 163 | #define CLK_TOP_UNIVPLL_D5_D8 151 |
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| 164 | #define CLK_TOP_UNIVPLL_D6 152 |
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| 165 | #define CLK_TOP_UNIVPLL_D6_D2 153 |
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| 166 | #define CLK_TOP_UNIVPLL_D6_D4 154 |
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| 167 | #define CLK_TOP_UNIVPLL_D6_D8 155 |
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| 168 | #define CLK_TOP_UNIVPLL_D6_D16 156 |
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| 169 | #define CLK_TOP_UNIVPLL_D7 157 |
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| 170 | #define CLK_TOP_UNIVPLL_192M 158 |
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| 171 | #define CLK_TOP_UNIVPLL_192M_D4 159 |
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| 172 | #define CLK_TOP_UNIVPLL_192M_D8 160 |
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| 173 | #define CLK_TOP_UNIVPLL_192M_D16 161 |
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| 174 | #define CLK_TOP_UNIVPLL_192M_D32 162 |
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| 175 | #define CLK_TOP_APLL1_D3 163 |
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| 176 | #define CLK_TOP_APLL1_D4 164 |
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| 177 | #define CLK_TOP_APLL2_D3 165 |
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| 178 | #define CLK_TOP_APLL2_D4 166 |
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| 179 | #define CLK_TOP_APLL3_D4 167 |
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| 180 | #define CLK_TOP_APLL4_D4 168 |
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| 181 | #define CLK_TOP_APLL5_D4 169 |
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| 182 | #define CLK_TOP_HDMIRX_APLL_D3 170 |
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| 183 | #define CLK_TOP_HDMIRX_APLL_D4 171 |
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| 184 | #define CLK_TOP_HDMIRX_APLL_D6 172 |
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| 185 | #define CLK_TOP_MMPLL_D4 173 |
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| 186 | #define CLK_TOP_MMPLL_D4_D2 174 |
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| 187 | #define CLK_TOP_MMPLL_D4_D4 175 |
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| 188 | #define CLK_TOP_MMPLL_D5 176 |
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| 189 | #define CLK_TOP_MMPLL_D5_D2 177 |
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| 190 | #define CLK_TOP_MMPLL_D5_D4 178 |
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| 191 | #define CLK_TOP_MMPLL_D6 179 |
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| 192 | #define CLK_TOP_MMPLL_D6_D2 180 |
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| 193 | #define CLK_TOP_MMPLL_D7 181 |
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| 194 | #define CLK_TOP_MMPLL_D9 182 |
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| 195 | #define CLK_TOP_TVDPLL1_D2 183 |
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| 196 | #define CLK_TOP_TVDPLL1_D4 184 |
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| 197 | #define CLK_TOP_TVDPLL1_D8 185 |
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| 198 | #define CLK_TOP_TVDPLL1_D16 186 |
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| 199 | #define CLK_TOP_TVDPLL2_D2 187 |
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| 200 | #define CLK_TOP_TVDPLL2_D4 188 |
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| 201 | #define CLK_TOP_TVDPLL2_D8 189 |
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| 202 | #define CLK_TOP_TVDPLL2_D16 190 |
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| 203 | #define CLK_TOP_MSDCPLL_D2 191 |
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| 204 | #define CLK_TOP_MSDCPLL_D4 192 |
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| 205 | #define CLK_TOP_MSDCPLL_D16 193 |
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| 206 | #define CLK_TOP_ETHPLL_D2 194 |
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| 207 | #define CLK_TOP_ETHPLL_D8 195 |
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| 208 | #define CLK_TOP_ETHPLL_D10 196 |
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| 209 | #define CLK_TOP_DGIPLL_D2 197 |
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| 210 | #define CLK_TOP_ULPOSC1 198 |
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| 211 | #define CLK_TOP_ULPOSC1_D2 199 |
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| 212 | #define CLK_TOP_ULPOSC1_D4 200 |
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| 213 | #define CLK_TOP_ULPOSC1_D7 201 |
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| 214 | #define CLK_TOP_ULPOSC1_D8 202 |
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| 215 | #define CLK_TOP_ULPOSC1_D10 203 |
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| 216 | #define CLK_TOP_ULPOSC1_D16 204 |
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| 217 | #define CLK_TOP_ULPOSC2 205 |
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| 218 | #define CLK_TOP_ADSPPLL_D2 206 |
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| 219 | #define CLK_TOP_ADSPPLL_D4 207 |
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| 220 | #define CLK_TOP_ADSPPLL_D8 208 |
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| 221 | #define CLK_TOP_MEM_466M 209 |
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| 222 | #define CLK_TOP_MPHONE_SLAVE_B 210 |
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| 223 | #define CLK_TOP_PEXTP_PIPE 211 |
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| 224 | #define CLK_TOP_UFS_RX_SYMBOL 212 |
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| 225 | #define CLK_TOP_UFS_TX_SYMBOL 213 |
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| 226 | #define CLK_TOP_SSUSB_U3PHY_P1_P_P0 214 |
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| 227 | #define CLK_TOP_UFS_RX_SYMBOL1 215 |
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| 228 | #define CLK_TOP_FPC 216 |
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| 229 | #define CLK_TOP_HDMIRX_P 217 |
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| 230 | #define CLK_TOP_APLL12_DIV0 218 |
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| 231 | #define CLK_TOP_APLL12_DIV1 219 |
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| 232 | #define CLK_TOP_APLL12_DIV2 220 |
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| 233 | #define CLK_TOP_APLL12_DIV3 221 |
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| 234 | #define CLK_TOP_APLL12_DIV4 222 |
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| 235 | #define CLK_TOP_APLL12_DIV9 223 |
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| 236 | #define CLK_TOP_CFG_VPP0 224 |
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| 237 | #define CLK_TOP_CFG_VPP1 225 |
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| 238 | #define CLK_TOP_CFG_VDO0 226 |
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| 239 | #define CLK_TOP_CFG_VDO1 227 |
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| 240 | #define CLK_TOP_CFG_UNIPLL_SES 228 |
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| 241 | #define CLK_TOP_CFG_26M_VPP0 229 |
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| 242 | #define CLK_TOP_CFG_26M_VPP1 230 |
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| 243 | #define CLK_TOP_CFG_26M_AUD 231 |
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| 244 | #define CLK_TOP_CFG_AXI_EAST 232 |
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| 245 | #define CLK_TOP_CFG_AXI_EAST_NORTH 233 |
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| 246 | #define CLK_TOP_CFG_AXI_NORTH 234 |
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| 247 | #define CLK_TOP_CFG_AXI_SOUTH 235 |
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| 248 | #define CLK_TOP_CFG_EXT_TEST 236 |
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| 249 | #define CLK_TOP_SSUSB_REF 237 |
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| 250 | #define CLK_TOP_SSUSB_PHY_REF 238 |
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| 251 | #define CLK_TOP_SSUSB_P1_REF 239 |
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| 252 | #define CLK_TOP_SSUSB_PHY_P1_REF 240 |
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| 253 | #define CLK_TOP_SSUSB_P2_REF 241 |
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| 254 | #define CLK_TOP_SSUSB_PHY_P2_REF 242 |
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| 255 | #define CLK_TOP_SSUSB_P3_REF 243 |
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| 256 | #define CLK_TOP_SSUSB_PHY_P3_REF 244 |
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| 257 | #define CLK_TOP_NR_CLK 245 |
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| 258 | |
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| 259 | /* INFRACFG_AO */ |
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| 260 | |
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| 261 | #define CLK_INFRA_AO_PMIC_TMR 0 |
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| 262 | #define CLK_INFRA_AO_PMIC_AP 1 |
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| 263 | #define CLK_INFRA_AO_PMIC_MD 2 |
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| 264 | #define CLK_INFRA_AO_PMIC_CONN 3 |
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| 265 | #define CLK_INFRA_AO_SEJ 4 |
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| 266 | #define CLK_INFRA_AO_APXGPT 5 |
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| 267 | #define CLK_INFRA_AO_GCE 6 |
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| 268 | #define CLK_INFRA_AO_GCE2 7 |
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| 269 | #define CLK_INFRA_AO_THERM 8 |
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| 270 | #define CLK_INFRA_AO_PWM_H 9 |
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| 271 | #define CLK_INFRA_AO_PWM1 10 |
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| 272 | #define CLK_INFRA_AO_PWM2 11 |
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| 273 | #define CLK_INFRA_AO_PWM3 12 |
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| 274 | #define CLK_INFRA_AO_PWM4 13 |
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| 275 | #define CLK_INFRA_AO_PWM 14 |
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| 276 | #define CLK_INFRA_AO_UART0 15 |
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| 277 | #define CLK_INFRA_AO_UART1 16 |
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| 278 | #define CLK_INFRA_AO_UART2 17 |
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| 279 | #define CLK_INFRA_AO_UART3 18 |
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| 280 | #define CLK_INFRA_AO_UART4 19 |
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| 281 | #define CLK_INFRA_AO_GCE_26M 20 |
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| 282 | #define CLK_INFRA_AO_CQ_DMA_FPC 21 |
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| 283 | #define CLK_INFRA_AO_UART5 22 |
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| 284 | #define CLK_INFRA_AO_HDMI_26M 23 |
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| 285 | #define CLK_INFRA_AO_SPI0 24 |
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| 286 | #define CLK_INFRA_AO_MSDC0 25 |
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| 287 | #define CLK_INFRA_AO_MSDC1 26 |
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| 288 | #define CLK_INFRA_AO_CG1_MSDC2 27 |
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| 289 | #define CLK_INFRA_AO_MSDC0_SRC 28 |
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| 290 | #define CLK_INFRA_AO_TRNG 29 |
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| 291 | #define CLK_INFRA_AO_AUXADC 30 |
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| 292 | #define CLK_INFRA_AO_CPUM 31 |
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| 293 | #define CLK_INFRA_AO_HDMI_32K 32 |
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| 294 | #define CLK_INFRA_AO_CEC_66M_H 33 |
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| 295 | #define CLK_INFRA_AO_IRRX 34 |
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| 296 | #define CLK_INFRA_AO_PCIE_TL_26M 35 |
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| 297 | #define CLK_INFRA_AO_MSDC1_SRC 36 |
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| 298 | #define CLK_INFRA_AO_CEC_66M_B 37 |
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| 299 | #define CLK_INFRA_AO_PCIE_TL_96M 38 |
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| 300 | #define CLK_INFRA_AO_DEVICE_APC 39 |
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| 301 | #define CLK_INFRA_AO_ECC_66M_H 40 |
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| 302 | #define CLK_INFRA_AO_DEBUGSYS 41 |
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| 303 | #define CLK_INFRA_AO_AUDIO 42 |
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| 304 | #define CLK_INFRA_AO_PCIE_TL_32K 43 |
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| 305 | #define CLK_INFRA_AO_DBG_TRACE 44 |
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| 306 | #define CLK_INFRA_AO_DRAMC_F26M 45 |
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| 307 | #define CLK_INFRA_AO_IRTX 46 |
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| 308 | #define CLK_INFRA_AO_SSUSB 47 |
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| 309 | #define CLK_INFRA_AO_DISP_PWM 48 |
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| 310 | #define CLK_INFRA_AO_CLDMA_B 49 |
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| 311 | #define CLK_INFRA_AO_AUDIO_26M_B 50 |
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| 312 | #define CLK_INFRA_AO_SPI1 51 |
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| 313 | #define CLK_INFRA_AO_SPI2 52 |
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| 314 | #define CLK_INFRA_AO_SPI3 53 |
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| 315 | #define CLK_INFRA_AO_UNIPRO_SYS 54 |
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| 316 | #define CLK_INFRA_AO_UNIPRO_TICK 55 |
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| 317 | #define CLK_INFRA_AO_UFS_MP_SAP_B 56 |
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| 318 | #define CLK_INFRA_AO_PWRMCU 57 |
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| 319 | #define CLK_INFRA_AO_PWRMCU_BUS_H 58 |
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| 320 | #define CLK_INFRA_AO_APDMA_B 59 |
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| 321 | #define CLK_INFRA_AO_SPI4 60 |
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| 322 | #define CLK_INFRA_AO_SPI5 61 |
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| 323 | #define CLK_INFRA_AO_CQ_DMA 62 |
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| 324 | #define CLK_INFRA_AO_AES_UFSFDE 63 |
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| 325 | #define CLK_INFRA_AO_AES 64 |
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| 326 | #define CLK_INFRA_AO_UFS_TICK 65 |
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| 327 | #define CLK_INFRA_AO_SSUSB_XHCI 66 |
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| 328 | #define CLK_INFRA_AO_MSDC0_SELF 67 |
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| 329 | #define CLK_INFRA_AO_MSDC1_SELF 68 |
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| 330 | #define CLK_INFRA_AO_MSDC2_SELF 69 |
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| 331 | #define CLK_INFRA_AO_I2S_DMA 70 |
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| 332 | #define CLK_INFRA_AO_AP_MSDC0 71 |
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| 333 | #define CLK_INFRA_AO_MD_MSDC0 72 |
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| 334 | #define CLK_INFRA_AO_CG3_MSDC2 73 |
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| 335 | #define CLK_INFRA_AO_GCPU 74 |
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| 336 | #define CLK_INFRA_AO_PCIE_PERI_26M 75 |
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| 337 | #define CLK_INFRA_AO_GCPU_66M_B 76 |
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| 338 | #define CLK_INFRA_AO_GCPU_133M_B 77 |
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| 339 | #define CLK_INFRA_AO_DISP_PWM1 78 |
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| 340 | #define CLK_INFRA_AO_FBIST2FPC 79 |
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| 341 | #define CLK_INFRA_AO_DEVICE_APC_SYNC 80 |
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| 342 | #define CLK_INFRA_AO_PCIE_P1_PERI_26M 81 |
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| 343 | #define CLK_INFRA_AO_SPIS0 82 |
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| 344 | #define CLK_INFRA_AO_SPIS1 83 |
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| 345 | #define CLK_INFRA_AO_133M_M_PERI 84 |
|---|
| 346 | #define CLK_INFRA_AO_66M_M_PERI 85 |
|---|
| 347 | #define CLK_INFRA_AO_PCIE_PL_P_250M_P0 86 |
|---|
| 348 | #define CLK_INFRA_AO_PCIE_PL_P_250M_P1 87 |
|---|
| 349 | #define CLK_INFRA_AO_PCIE_P1_TL_96M 88 |
|---|
| 350 | #define CLK_INFRA_AO_AES_MSDCFDE_0P 89 |
|---|
| 351 | #define CLK_INFRA_AO_UFS_TX_SYMBOL 90 |
|---|
| 352 | #define CLK_INFRA_AO_UFS_RX_SYMBOL 91 |
|---|
| 353 | #define CLK_INFRA_AO_UFS_RX_SYMBOL1 92 |
|---|
| 354 | #define CLK_INFRA_AO_PERI_UFS_MEM_SUB 93 |
|---|
| 355 | #define CLK_INFRA_AO_NR_CLK 94 |
|---|
| 356 | |
|---|
| 357 | /* APMIXEDSYS */ |
|---|
| 358 | |
|---|
| 359 | #define CLK_APMIXED_NNAPLL 0 |
|---|
| 360 | #define CLK_APMIXED_RESPLL 1 |
|---|
| 361 | #define CLK_APMIXED_ETHPLL 2 |
|---|
| 362 | #define CLK_APMIXED_MSDCPLL 3 |
|---|
| 363 | #define CLK_APMIXED_TVDPLL1 4 |
|---|
| 364 | #define CLK_APMIXED_TVDPLL2 5 |
|---|
| 365 | #define CLK_APMIXED_MMPLL 6 |
|---|
| 366 | #define CLK_APMIXED_MAINPLL 7 |
|---|
| 367 | #define CLK_APMIXED_VDECPLL 8 |
|---|
| 368 | #define CLK_APMIXED_IMGPLL 9 |
|---|
| 369 | #define CLK_APMIXED_UNIVPLL 10 |
|---|
| 370 | #define CLK_APMIXED_HDMIPLL1 11 |
|---|
| 371 | #define CLK_APMIXED_HDMIPLL2 12 |
|---|
| 372 | #define CLK_APMIXED_HDMIRX_APLL 13 |
|---|
| 373 | #define CLK_APMIXED_USB1PLL 14 |
|---|
| 374 | #define CLK_APMIXED_ADSPPLL 15 |
|---|
| 375 | #define CLK_APMIXED_APLL1 16 |
|---|
| 376 | #define CLK_APMIXED_APLL2 17 |
|---|
| 377 | #define CLK_APMIXED_APLL3 18 |
|---|
| 378 | #define CLK_APMIXED_APLL4 19 |
|---|
| 379 | #define CLK_APMIXED_APLL5 20 |
|---|
| 380 | #define CLK_APMIXED_MFGPLL 21 |
|---|
| 381 | #define CLK_APMIXED_DGIPLL 22 |
|---|
| 382 | #define CLK_APMIXED_PLL_SSUSB26M 23 |
|---|
| 383 | #define CLK_APMIXED_NR_CLK 24 |
|---|
| 384 | |
|---|
| 385 | /* SCP_ADSP */ |
|---|
| 386 | |
|---|
| 387 | #define CLK_SCP_ADSP_AUDIODSP 0 |
|---|
| 388 | #define CLK_SCP_ADSP_NR_CLK 1 |
|---|
| 389 | |
|---|
| 390 | /* PERICFG_AO */ |
|---|
| 391 | |
|---|
| 392 | #define CLK_PERI_AO_ETHERNET 0 |
|---|
| 393 | #define CLK_PERI_AO_ETHERNET_BUS 1 |
|---|
| 394 | #define CLK_PERI_AO_FLASHIF_BUS 2 |
|---|
| 395 | #define CLK_PERI_AO_FLASHIF_FLASH 3 |
|---|
| 396 | #define CLK_PERI_AO_SSUSB_1P_BUS 4 |
|---|
| 397 | #define CLK_PERI_AO_SSUSB_1P_XHCI 5 |
|---|
| 398 | #define CLK_PERI_AO_SSUSB_2P_BUS 6 |
|---|
| 399 | #define CLK_PERI_AO_SSUSB_2P_XHCI 7 |
|---|
| 400 | #define CLK_PERI_AO_SSUSB_3P_BUS 8 |
|---|
| 401 | #define CLK_PERI_AO_SSUSB_3P_XHCI 9 |
|---|
| 402 | #define CLK_PERI_AO_SPINFI 10 |
|---|
| 403 | #define CLK_PERI_AO_ETHERNET_MAC 11 |
|---|
| 404 | #define CLK_PERI_AO_NFI_H 12 |
|---|
| 405 | #define CLK_PERI_AO_FNFI1X 13 |
|---|
| 406 | #define CLK_PERI_AO_PCIE_P0_MEM 14 |
|---|
| 407 | #define CLK_PERI_AO_PCIE_P1_MEM 15 |
|---|
| 408 | #define CLK_PERI_AO_NR_CLK 16 |
|---|
| 409 | |
|---|
| 410 | /* IMP_IIC_WRAP_S */ |
|---|
| 411 | |
|---|
| 412 | #define CLK_IMP_IIC_WRAP_S_I2C5 0 |
|---|
| 413 | #define CLK_IMP_IIC_WRAP_S_I2C6 1 |
|---|
| 414 | #define CLK_IMP_IIC_WRAP_S_I2C7 2 |
|---|
| 415 | #define CLK_IMP_IIC_WRAP_S_NR_CLK 3 |
|---|
| 416 | |
|---|
| 417 | /* IMP_IIC_WRAP_W */ |
|---|
| 418 | |
|---|
| 419 | #define CLK_IMP_IIC_WRAP_W_I2C0 0 |
|---|
| 420 | #define CLK_IMP_IIC_WRAP_W_I2C1 1 |
|---|
| 421 | #define CLK_IMP_IIC_WRAP_W_I2C2 2 |
|---|
| 422 | #define CLK_IMP_IIC_WRAP_W_I2C3 3 |
|---|
| 423 | #define CLK_IMP_IIC_WRAP_W_I2C4 4 |
|---|
| 424 | #define CLK_IMP_IIC_WRAP_W_NR_CLK 5 |
|---|
| 425 | |
|---|
| 426 | /* MFGCFG */ |
|---|
| 427 | |
|---|
| 428 | #define CLK_MFG_BG3D 0 |
|---|
| 429 | #define CLK_MFG_NR_CLK 1 |
|---|
| 430 | |
|---|
| 431 | /* VPPSYS0 */ |
|---|
| 432 | |
|---|
| 433 | #define CLK_VPP0_MDP_FG 0 |
|---|
| 434 | #define CLK_VPP0_STITCH 1 |
|---|
| 435 | #define CLK_VPP0_PADDING 2 |
|---|
| 436 | #define CLK_VPP0_MDP_TCC 3 |
|---|
| 437 | #define CLK_VPP0_WARP0_ASYNC_TX 4 |
|---|
| 438 | #define CLK_VPP0_WARP1_ASYNC_TX 5 |
|---|
| 439 | #define CLK_VPP0_MUTEX 6 |
|---|
| 440 | #define CLK_VPP0_VPP02VPP1_RELAY 7 |
|---|
| 441 | #define CLK_VPP0_VPP12VPP0_ASYNC 8 |
|---|
| 442 | #define CLK_VPP0_MMSYSRAM_TOP 9 |
|---|
| 443 | #define CLK_VPP0_MDP_AAL 10 |
|---|
| 444 | #define CLK_VPP0_MDP_RSZ 11 |
|---|
| 445 | #define CLK_VPP0_SMI_COMMON 12 |
|---|
| 446 | #define CLK_VPP0_GALS_VDO0_LARB0 13 |
|---|
| 447 | #define CLK_VPP0_GALS_VDO0_LARB1 14 |
|---|
| 448 | #define CLK_VPP0_GALS_VENCSYS 15 |
|---|
| 449 | #define CLK_VPP0_GALS_VENCSYS_CORE1 16 |
|---|
| 450 | #define CLK_VPP0_GALS_INFRA 17 |
|---|
| 451 | #define CLK_VPP0_GALS_CAMSYS 18 |
|---|
| 452 | #define CLK_VPP0_GALS_VPP1_LARB5 19 |
|---|
| 453 | #define CLK_VPP0_GALS_VPP1_LARB6 20 |
|---|
| 454 | #define CLK_VPP0_SMI_REORDER 21 |
|---|
| 455 | #define CLK_VPP0_SMI_IOMMU 22 |
|---|
| 456 | #define CLK_VPP0_GALS_IMGSYS_CAMSYS 23 |
|---|
| 457 | #define CLK_VPP0_MDP_RDMA 24 |
|---|
| 458 | #define CLK_VPP0_MDP_WROT 25 |
|---|
| 459 | #define CLK_VPP0_GALS_EMI0_EMI1 26 |
|---|
| 460 | #define CLK_VPP0_SMI_SUB_COMMON_REORDER 27 |
|---|
| 461 | #define CLK_VPP0_SMI_RSI 28 |
|---|
| 462 | #define CLK_VPP0_SMI_COMMON_LARB4 29 |
|---|
| 463 | #define CLK_VPP0_GALS_VDEC_VDEC_CORE1 30 |
|---|
| 464 | #define CLK_VPP0_GALS_VPP1_WPE 31 |
|---|
| 465 | #define CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1 32 |
|---|
| 466 | #define CLK_VPP0_FAKE_ENG 33 |
|---|
| 467 | #define CLK_VPP0_MDP_HDR 34 |
|---|
| 468 | #define CLK_VPP0_MDP_TDSHP 35 |
|---|
| 469 | #define CLK_VPP0_MDP_COLOR 36 |
|---|
| 470 | #define CLK_VPP0_MDP_OVL 37 |
|---|
| 471 | #define CLK_VPP0_WARP0_RELAY 38 |
|---|
| 472 | #define CLK_VPP0_WARP0_MDP_DL_ASYNC 39 |
|---|
| 473 | #define CLK_VPP0_WARP1_RELAY 40 |
|---|
| 474 | #define CLK_VPP0_WARP1_MDP_DL_ASYNC 41 |
|---|
| 475 | #define CLK_VPP0_NR_CLK 42 |
|---|
| 476 | |
|---|
| 477 | /* WPESYS */ |
|---|
| 478 | |
|---|
| 479 | #define CLK_WPE_VPP0 0 |
|---|
| 480 | #define CLK_WPE_VPP1 1 |
|---|
| 481 | #define CLK_WPE_SMI_LARB7 2 |
|---|
| 482 | #define CLK_WPE_SMI_LARB8 3 |
|---|
| 483 | #define CLK_WPE_EVENT_TX 4 |
|---|
| 484 | #define CLK_WPE_SMI_LARB7_P 5 |
|---|
| 485 | #define CLK_WPE_SMI_LARB8_P 6 |
|---|
| 486 | #define CLK_WPE_NR_CLK 7 |
|---|
| 487 | |
|---|
| 488 | /* WPESYS_VPP0 */ |
|---|
| 489 | |
|---|
| 490 | #define CLK_WPE_VPP0_VECI 0 |
|---|
| 491 | #define CLK_WPE_VPP0_VEC2I 1 |
|---|
| 492 | #define CLK_WPE_VPP0_VEC3I 2 |
|---|
| 493 | #define CLK_WPE_VPP0_WPEO 3 |
|---|
| 494 | #define CLK_WPE_VPP0_MSKO 4 |
|---|
| 495 | #define CLK_WPE_VPP0_VGEN 5 |
|---|
| 496 | #define CLK_WPE_VPP0_EXT 6 |
|---|
| 497 | #define CLK_WPE_VPP0_VFC 7 |
|---|
| 498 | #define CLK_WPE_VPP0_CACH0_TOP 8 |
|---|
| 499 | #define CLK_WPE_VPP0_CACH0_DMA 9 |
|---|
| 500 | #define CLK_WPE_VPP0_CACH1_TOP 10 |
|---|
| 501 | #define CLK_WPE_VPP0_CACH1_DMA 11 |
|---|
| 502 | #define CLK_WPE_VPP0_CACH2_TOP 12 |
|---|
| 503 | #define CLK_WPE_VPP0_CACH2_DMA 13 |
|---|
| 504 | #define CLK_WPE_VPP0_CACH3_TOP 14 |
|---|
| 505 | #define CLK_WPE_VPP0_CACH3_DMA 15 |
|---|
| 506 | #define CLK_WPE_VPP0_PSP 16 |
|---|
| 507 | #define CLK_WPE_VPP0_PSP2 17 |
|---|
| 508 | #define CLK_WPE_VPP0_SYNC 18 |
|---|
| 509 | #define CLK_WPE_VPP0_C24 19 |
|---|
| 510 | #define CLK_WPE_VPP0_MDP_CROP 20 |
|---|
| 511 | #define CLK_WPE_VPP0_ISP_CROP 21 |
|---|
| 512 | #define CLK_WPE_VPP0_TOP 22 |
|---|
| 513 | #define CLK_WPE_VPP0_NR_CLK 23 |
|---|
| 514 | |
|---|
| 515 | /* WPESYS_VPP1 */ |
|---|
| 516 | |
|---|
| 517 | #define CLK_WPE_VPP1_VECI 0 |
|---|
| 518 | #define CLK_WPE_VPP1_VEC2I 1 |
|---|
| 519 | #define CLK_WPE_VPP1_VEC3I 2 |
|---|
| 520 | #define CLK_WPE_VPP1_WPEO 3 |
|---|
| 521 | #define CLK_WPE_VPP1_MSKO 4 |
|---|
| 522 | #define CLK_WPE_VPP1_VGEN 5 |
|---|
| 523 | #define CLK_WPE_VPP1_EXT 6 |
|---|
| 524 | #define CLK_WPE_VPP1_VFC 7 |
|---|
| 525 | #define CLK_WPE_VPP1_CACH0_TOP 8 |
|---|
| 526 | #define CLK_WPE_VPP1_CACH0_DMA 9 |
|---|
| 527 | #define CLK_WPE_VPP1_CACH1_TOP 10 |
|---|
| 528 | #define CLK_WPE_VPP1_CACH1_DMA 11 |
|---|
| 529 | #define CLK_WPE_VPP1_CACH2_TOP 12 |
|---|
| 530 | #define CLK_WPE_VPP1_CACH2_DMA 13 |
|---|
| 531 | #define CLK_WPE_VPP1_CACH3_TOP 14 |
|---|
| 532 | #define CLK_WPE_VPP1_CACH3_DMA 15 |
|---|
| 533 | #define CLK_WPE_VPP1_PSP 16 |
|---|
| 534 | #define CLK_WPE_VPP1_PSP2 17 |
|---|
| 535 | #define CLK_WPE_VPP1_SYNC 18 |
|---|
| 536 | #define CLK_WPE_VPP1_C24 19 |
|---|
| 537 | #define CLK_WPE_VPP1_MDP_CROP 20 |
|---|
| 538 | #define CLK_WPE_VPP1_ISP_CROP 21 |
|---|
| 539 | #define CLK_WPE_VPP1_TOP 22 |
|---|
| 540 | #define CLK_WPE_VPP1_NR_CLK 23 |
|---|
| 541 | |
|---|
| 542 | /* VPPSYS1 */ |
|---|
| 543 | |
|---|
| 544 | #define CLK_VPP1_SVPP1_MDP_OVL 0 |
|---|
| 545 | #define CLK_VPP1_SVPP1_MDP_TCC 1 |
|---|
| 546 | #define CLK_VPP1_SVPP1_MDP_WROT 2 |
|---|
| 547 | #define CLK_VPP1_SVPP1_VPP_PAD 3 |
|---|
| 548 | #define CLK_VPP1_SVPP2_MDP_WROT 4 |
|---|
| 549 | #define CLK_VPP1_SVPP2_VPP_PAD 5 |
|---|
| 550 | #define CLK_VPP1_SVPP3_MDP_WROT 6 |
|---|
| 551 | #define CLK_VPP1_SVPP3_VPP_PAD 7 |
|---|
| 552 | #define CLK_VPP1_SVPP1_MDP_RDMA 8 |
|---|
| 553 | #define CLK_VPP1_SVPP1_MDP_FG 9 |
|---|
| 554 | #define CLK_VPP1_SVPP2_MDP_RDMA 10 |
|---|
| 555 | #define CLK_VPP1_SVPP2_MDP_FG 11 |
|---|
| 556 | #define CLK_VPP1_SVPP3_MDP_RDMA 12 |
|---|
| 557 | #define CLK_VPP1_SVPP3_MDP_FG 13 |
|---|
| 558 | #define CLK_VPP1_VPP_SPLIT 14 |
|---|
| 559 | #define CLK_VPP1_SVPP2_VDO0_DL_RELAY 15 |
|---|
| 560 | #define CLK_VPP1_SVPP1_MDP_TDSHP 16 |
|---|
| 561 | #define CLK_VPP1_SVPP1_MDP_COLOR 17 |
|---|
| 562 | #define CLK_VPP1_SVPP3_VDO1_DL_RELAY 18 |
|---|
| 563 | #define CLK_VPP1_SVPP2_VPP_MERGE 19 |
|---|
| 564 | #define CLK_VPP1_SVPP2_MDP_COLOR 20 |
|---|
| 565 | #define CLK_VPP1_VPPSYS1_GALS 21 |
|---|
| 566 | #define CLK_VPP1_SVPP3_VPP_MERGE 22 |
|---|
| 567 | #define CLK_VPP1_SVPP3_MDP_COLOR 23 |
|---|
| 568 | #define CLK_VPP1_VPPSYS1_LARB 24 |
|---|
| 569 | #define CLK_VPP1_SVPP1_MDP_RSZ 25 |
|---|
| 570 | #define CLK_VPP1_SVPP1_MDP_HDR 26 |
|---|
| 571 | #define CLK_VPP1_SVPP1_MDP_AAL 27 |
|---|
| 572 | #define CLK_VPP1_SVPP2_MDP_HDR 28 |
|---|
| 573 | #define CLK_VPP1_SVPP2_MDP_AAL 29 |
|---|
| 574 | #define CLK_VPP1_DL_ASYNC 30 |
|---|
| 575 | #define CLK_VPP1_LARB5_FAKE_ENG 31 |
|---|
| 576 | #define CLK_VPP1_SVPP3_MDP_HDR 32 |
|---|
| 577 | #define CLK_VPP1_SVPP3_MDP_AAL 33 |
|---|
| 578 | #define CLK_VPP1_SVPP2_VDO1_DL_RELAY 34 |
|---|
| 579 | #define CLK_VPP1_LARB6_FAKE_ENG 35 |
|---|
| 580 | #define CLK_VPP1_SVPP2_MDP_RSZ 36 |
|---|
| 581 | #define CLK_VPP1_SVPP3_MDP_RSZ 37 |
|---|
| 582 | #define CLK_VPP1_SVPP3_VDO0_DL_RELAY 38 |
|---|
| 583 | #define CLK_VPP1_DISP_MUTEX 39 |
|---|
| 584 | #define CLK_VPP1_SVPP2_MDP_TDSHP 40 |
|---|
| 585 | #define CLK_VPP1_SVPP3_MDP_TDSHP 41 |
|---|
| 586 | #define CLK_VPP1_VPP0_DL1_RELAY 42 |
|---|
| 587 | #define CLK_VPP1_HDMI_META 43 |
|---|
| 588 | #define CLK_VPP1_VPP_SPLIT_HDMI 44 |
|---|
| 589 | #define CLK_VPP1_DGI_IN 45 |
|---|
| 590 | #define CLK_VPP1_DGI_OUT 46 |
|---|
| 591 | #define CLK_VPP1_VPP_SPLIT_DGI 47 |
|---|
| 592 | #define CLK_VPP1_VPP0_DL_ASYNC 48 |
|---|
| 593 | #define CLK_VPP1_VPP0_DL_RELAY 49 |
|---|
| 594 | #define CLK_VPP1_VPP_SPLIT_26M 50 |
|---|
| 595 | #define CLK_VPP1_NR_CLK 51 |
|---|
| 596 | |
|---|
| 597 | /* IMGSYS */ |
|---|
| 598 | |
|---|
| 599 | #define CLK_IMG_LARB9 0 |
|---|
| 600 | #define CLK_IMG_TRAW0 1 |
|---|
| 601 | #define CLK_IMG_TRAW1 2 |
|---|
| 602 | #define CLK_IMG_TRAW2 3 |
|---|
| 603 | #define CLK_IMG_TRAW3 4 |
|---|
| 604 | #define CLK_IMG_DIP0 5 |
|---|
| 605 | #define CLK_IMG_WPE0 6 |
|---|
| 606 | #define CLK_IMG_IPE 7 |
|---|
| 607 | #define CLK_IMG_DIP1 8 |
|---|
| 608 | #define CLK_IMG_WPE1 9 |
|---|
| 609 | #define CLK_IMG_GALS 10 |
|---|
| 610 | #define CLK_IMG_NR_CLK 11 |
|---|
| 611 | |
|---|
| 612 | /* IMGSYS1_DIP_TOP */ |
|---|
| 613 | |
|---|
| 614 | #define CLK_IMG1_DIP_TOP_LARB10 0 |
|---|
| 615 | #define CLK_IMG1_DIP_TOP_DIP_TOP 1 |
|---|
| 616 | #define CLK_IMG1_DIP_TOP_NR_CLK 2 |
|---|
| 617 | |
|---|
| 618 | /* IMGSYS1_DIP_NR */ |
|---|
| 619 | |
|---|
| 620 | #define CLK_IMG1_DIP_NR_RESERVE 0 |
|---|
| 621 | #define CLK_IMG1_DIP_NR_DIP_NR 1 |
|---|
| 622 | #define CLK_IMG1_DIP_NR_NR_CLK 2 |
|---|
| 623 | |
|---|
| 624 | /* IMGSYS1_WPE */ |
|---|
| 625 | |
|---|
| 626 | #define CLK_IMG1_WPE_LARB11 0 |
|---|
| 627 | #define CLK_IMG1_WPE_WPE 1 |
|---|
| 628 | #define CLK_IMG1_WPE_NR_CLK 2 |
|---|
| 629 | |
|---|
| 630 | /* IPESYS */ |
|---|
| 631 | |
|---|
| 632 | #define CLK_IPE_DPE 0 |
|---|
| 633 | #define CLK_IPE_FDVT 1 |
|---|
| 634 | #define CLK_IPE_ME 2 |
|---|
| 635 | #define CLK_IPE_TOP 3 |
|---|
| 636 | #define CLK_IPE_SMI_LARB12 4 |
|---|
| 637 | #define CLK_IPE_NR_CLK 5 |
|---|
| 638 | |
|---|
| 639 | /* CAMSYS */ |
|---|
| 640 | |
|---|
| 641 | #define CLK_CAM_LARB13 0 |
|---|
| 642 | #define CLK_CAM_LARB14 1 |
|---|
| 643 | #define CLK_CAM_MAIN_CAM 2 |
|---|
| 644 | #define CLK_CAM_MAIN_CAMTG 3 |
|---|
| 645 | #define CLK_CAM_SENINF 4 |
|---|
| 646 | #define CLK_CAM_GCAMSVA 5 |
|---|
| 647 | #define CLK_CAM_GCAMSVB 6 |
|---|
| 648 | #define CLK_CAM_GCAMSVC 7 |
|---|
| 649 | #define CLK_CAM_SCAMSA 8 |
|---|
| 650 | #define CLK_CAM_SCAMSB 9 |
|---|
| 651 | #define CLK_CAM_CAMSV_TOP 10 |
|---|
| 652 | #define CLK_CAM_CAMSV_CQ 11 |
|---|
| 653 | #define CLK_CAM_ADL 12 |
|---|
| 654 | #define CLK_CAM_ASG 13 |
|---|
| 655 | #define CLK_CAM_PDA 14 |
|---|
| 656 | #define CLK_CAM_FAKE_ENG 15 |
|---|
| 657 | #define CLK_CAM_MAIN_MRAW0 16 |
|---|
| 658 | #define CLK_CAM_MAIN_MRAW1 17 |
|---|
| 659 | #define CLK_CAM_MAIN_MRAW2 18 |
|---|
| 660 | #define CLK_CAM_MAIN_MRAW3 19 |
|---|
| 661 | #define CLK_CAM_CAM2MM0_GALS 20 |
|---|
| 662 | #define CLK_CAM_CAM2MM1_GALS 21 |
|---|
| 663 | #define CLK_CAM_CAM2SYS_GALS 22 |
|---|
| 664 | #define CLK_CAM_NR_CLK 23 |
|---|
| 665 | |
|---|
| 666 | /* CAMSYS_RAWA */ |
|---|
| 667 | |
|---|
| 668 | #define CLK_CAM_RAWA_LARBX 0 |
|---|
| 669 | #define CLK_CAM_RAWA_CAM 1 |
|---|
| 670 | #define CLK_CAM_RAWA_CAMTG 2 |
|---|
| 671 | #define CLK_CAM_RAWA_NR_CLK 3 |
|---|
| 672 | |
|---|
| 673 | /* CAMSYS_YUVA */ |
|---|
| 674 | |
|---|
| 675 | #define CLK_CAM_YUVA_LARBX 0 |
|---|
| 676 | #define CLK_CAM_YUVA_CAM 1 |
|---|
| 677 | #define CLK_CAM_YUVA_CAMTG 2 |
|---|
| 678 | #define CLK_CAM_YUVA_NR_CLK 3 |
|---|
| 679 | |
|---|
| 680 | /* CAMSYS_RAWB */ |
|---|
| 681 | |
|---|
| 682 | #define CLK_CAM_RAWB_LARBX 0 |
|---|
| 683 | #define CLK_CAM_RAWB_CAM 1 |
|---|
| 684 | #define CLK_CAM_RAWB_CAMTG 2 |
|---|
| 685 | #define CLK_CAM_RAWB_NR_CLK 3 |
|---|
| 686 | |
|---|
| 687 | /* CAMSYS_YUVB */ |
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| 688 | |
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| 689 | #define CLK_CAM_YUVB_LARBX 0 |
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| 690 | #define CLK_CAM_YUVB_CAM 1 |
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| 691 | #define CLK_CAM_YUVB_CAMTG 2 |
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| 692 | #define CLK_CAM_YUVB_NR_CLK 3 |
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| 693 | |
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| 694 | /* CAMSYS_MRAW */ |
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| 695 | |
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| 696 | #define CLK_CAM_MRAW_LARBX 0 |
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| 697 | #define CLK_CAM_MRAW_CAMTG 1 |
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| 698 | #define CLK_CAM_MRAW_MRAW0 2 |
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| 699 | #define CLK_CAM_MRAW_MRAW1 3 |
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| 700 | #define CLK_CAM_MRAW_MRAW2 4 |
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| 701 | #define CLK_CAM_MRAW_MRAW3 5 |
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| 702 | #define CLK_CAM_MRAW_NR_CLK 6 |
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| 703 | |
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| 704 | /* CCUSYS */ |
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| 705 | |
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| 706 | #define CLK_CCU_LARB18 0 |
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| 707 | #define CLK_CCU_AHB 1 |
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| 708 | #define CLK_CCU_CCU0 2 |
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| 709 | #define CLK_CCU_CCU1 3 |
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| 710 | #define CLK_CCU_NR_CLK 4 |
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| 711 | |
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| 712 | /* VDECSYS_SOC */ |
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| 713 | |
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| 714 | #define CLK_VDEC_SOC_LARB1 0 |
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| 715 | #define CLK_VDEC_SOC_LAT 1 |
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| 716 | #define CLK_VDEC_SOC_VDEC 2 |
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| 717 | #define CLK_VDEC_SOC_NR_CLK 3 |
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| 718 | |
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| 719 | /* VDECSYS */ |
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| 720 | |
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| 721 | #define CLK_VDEC_LARB1 0 |
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| 722 | #define CLK_VDEC_LAT 1 |
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| 723 | #define CLK_VDEC_VDEC 2 |
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| 724 | #define CLK_VDEC_NR_CLK 3 |
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| 725 | |
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| 726 | /* VDECSYS_CORE1 */ |
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| 727 | |
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| 728 | #define CLK_VDEC_CORE1_LARB1 0 |
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| 729 | #define CLK_VDEC_CORE1_LAT 1 |
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| 730 | #define CLK_VDEC_CORE1_VDEC 2 |
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| 731 | #define CLK_VDEC_CORE1_NR_CLK 3 |
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| 732 | |
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| 733 | /* APUSYS_PLL */ |
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| 734 | |
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| 735 | #define CLK_APUSYS_PLL_APUPLL 0 |
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| 736 | #define CLK_APUSYS_PLL_NPUPLL 1 |
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| 737 | #define CLK_APUSYS_PLL_APUPLL1 2 |
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| 738 | #define CLK_APUSYS_PLL_APUPLL2 3 |
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| 739 | #define CLK_APUSYS_PLL_NR_CLK 4 |
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| 740 | |
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| 741 | /* VENCSYS */ |
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| 742 | |
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| 743 | #define CLK_VENC_LARB 0 |
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| 744 | #define CLK_VENC_VENC 1 |
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| 745 | #define CLK_VENC_JPGENC 2 |
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| 746 | #define CLK_VENC_JPGDEC 3 |
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| 747 | #define CLK_VENC_JPGDEC_C1 4 |
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| 748 | #define CLK_VENC_GALS 5 |
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| 749 | #define CLK_VENC_NR_CLK 6 |
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| 750 | |
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| 751 | /* VENCSYS_CORE1 */ |
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| 752 | |
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| 753 | #define CLK_VENC_CORE1_LARB 0 |
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| 754 | #define CLK_VENC_CORE1_VENC 1 |
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| 755 | #define CLK_VENC_CORE1_JPGENC 2 |
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| 756 | #define CLK_VENC_CORE1_JPGDEC 3 |
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| 757 | #define CLK_VENC_CORE1_JPGDEC_C1 4 |
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| 758 | #define CLK_VENC_CORE1_GALS 5 |
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| 759 | #define CLK_VENC_CORE1_NR_CLK 6 |
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| 760 | |
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| 761 | /* VDOSYS0 */ |
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| 762 | |
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| 763 | #define CLK_VDO0_DISP_OVL0 0 |
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| 764 | #define CLK_VDO0_DISP_COLOR0 1 |
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| 765 | #define CLK_VDO0_DISP_COLOR1 2 |
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| 766 | #define CLK_VDO0_DISP_CCORR0 3 |
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| 767 | #define CLK_VDO0_DISP_CCORR1 4 |
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| 768 | #define CLK_VDO0_DISP_AAL0 5 |
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| 769 | #define CLK_VDO0_DISP_AAL1 6 |
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| 770 | #define CLK_VDO0_DISP_GAMMA0 7 |
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| 771 | #define CLK_VDO0_DISP_GAMMA1 8 |
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| 772 | #define CLK_VDO0_DISP_DITHER0 9 |
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| 773 | #define CLK_VDO0_DISP_DITHER1 10 |
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| 774 | #define CLK_VDO0_DISP_OVL1 11 |
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| 775 | #define CLK_VDO0_DISP_WDMA0 12 |
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| 776 | #define CLK_VDO0_DISP_WDMA1 13 |
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| 777 | #define CLK_VDO0_DISP_RDMA0 14 |
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| 778 | #define CLK_VDO0_DISP_RDMA1 15 |
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| 779 | #define CLK_VDO0_DSI0 16 |
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| 780 | #define CLK_VDO0_DSI1 17 |
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| 781 | #define CLK_VDO0_DSC_WRAP0 18 |
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| 782 | #define CLK_VDO0_VPP_MERGE0 19 |
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| 783 | #define CLK_VDO0_DP_INTF0 20 |
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| 784 | #define CLK_VDO0_DISP_MUTEX0 21 |
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| 785 | #define CLK_VDO0_DISP_IL_ROT0 22 |
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| 786 | #define CLK_VDO0_APB_BUS 23 |
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| 787 | #define CLK_VDO0_FAKE_ENG0 24 |
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| 788 | #define CLK_VDO0_FAKE_ENG1 25 |
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| 789 | #define CLK_VDO0_DL_ASYNC0 26 |
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| 790 | #define CLK_VDO0_DL_ASYNC1 27 |
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| 791 | #define CLK_VDO0_DL_ASYNC2 28 |
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| 792 | #define CLK_VDO0_DL_ASYNC3 29 |
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| 793 | #define CLK_VDO0_DL_ASYNC4 30 |
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| 794 | #define CLK_VDO0_DISP_MONITOR0 31 |
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| 795 | #define CLK_VDO0_DISP_MONITOR1 32 |
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| 796 | #define CLK_VDO0_DISP_MONITOR2 33 |
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| 797 | #define CLK_VDO0_DISP_MONITOR3 34 |
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| 798 | #define CLK_VDO0_DISP_MONITOR4 35 |
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| 799 | #define CLK_VDO0_SMI_GALS 36 |
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| 800 | #define CLK_VDO0_SMI_COMMON 37 |
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| 801 | #define CLK_VDO0_SMI_EMI 38 |
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| 802 | #define CLK_VDO0_SMI_IOMMU 39 |
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| 803 | #define CLK_VDO0_SMI_LARB 40 |
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| 804 | #define CLK_VDO0_SMI_RSI 41 |
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| 805 | #define CLK_VDO0_DSI0_DSI 42 |
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| 806 | #define CLK_VDO0_DSI1_DSI 43 |
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| 807 | #define CLK_VDO0_DP_INTF0_DP_INTF 44 |
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| 808 | #define CLK_VDO0_NR_CLK 45 |
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| 809 | |
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| 810 | /* VDOSYS1 */ |
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| 811 | |
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| 812 | #define CLK_VDO1_SMI_LARB2 0 |
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| 813 | #define CLK_VDO1_SMI_LARB3 1 |
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| 814 | #define CLK_VDO1_GALS 2 |
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| 815 | #define CLK_VDO1_FAKE_ENG0 3 |
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| 816 | #define CLK_VDO1_FAKE_ENG 4 |
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| 817 | #define CLK_VDO1_MDP_RDMA0 5 |
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| 818 | #define CLK_VDO1_MDP_RDMA1 6 |
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| 819 | #define CLK_VDO1_MDP_RDMA2 7 |
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| 820 | #define CLK_VDO1_MDP_RDMA3 8 |
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| 821 | #define CLK_VDO1_VPP_MERGE0 9 |
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| 822 | #define CLK_VDO1_VPP_MERGE1 10 |
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| 823 | #define CLK_VDO1_VPP_MERGE2 11 |
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| 824 | #define CLK_VDO1_VPP_MERGE3 12 |
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| 825 | #define CLK_VDO1_VPP_MERGE4 13 |
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| 826 | #define CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC 14 |
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| 827 | #define CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC 15 |
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| 828 | #define CLK_VDO1_DISP_MUTEX 16 |
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| 829 | #define CLK_VDO1_MDP_RDMA4 17 |
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| 830 | #define CLK_VDO1_MDP_RDMA5 18 |
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| 831 | #define CLK_VDO1_MDP_RDMA6 19 |
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| 832 | #define CLK_VDO1_MDP_RDMA7 20 |
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| 833 | #define CLK_VDO1_DP_INTF0_MM 21 |
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| 834 | #define CLK_VDO1_DPI0_MM 22 |
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| 835 | #define CLK_VDO1_DPI1_MM 23 |
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| 836 | #define CLK_VDO1_DISP_MONITOR 24 |
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| 837 | #define CLK_VDO1_MERGE0_DL_ASYNC 25 |
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| 838 | #define CLK_VDO1_MERGE1_DL_ASYNC 26 |
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| 839 | #define CLK_VDO1_MERGE2_DL_ASYNC 27 |
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| 840 | #define CLK_VDO1_MERGE3_DL_ASYNC 28 |
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| 841 | #define CLK_VDO1_MERGE4_DL_ASYNC 29 |
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| 842 | #define CLK_VDO1_VDO0_DSC_TO_VDO1_DL_ASYNC 30 |
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| 843 | #define CLK_VDO1_VDO0_MERGE_TO_VDO1_DL_ASYNC 31 |
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| 844 | #define CLK_VDO1_HDR_VDO_FE0 32 |
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| 845 | #define CLK_VDO1_HDR_GFX_FE0 33 |
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| 846 | #define CLK_VDO1_HDR_VDO_BE 34 |
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| 847 | #define CLK_VDO1_HDR_VDO_FE1 35 |
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| 848 | #define CLK_VDO1_HDR_GFX_FE1 36 |
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| 849 | #define CLK_VDO1_DISP_MIXER 37 |
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| 850 | #define CLK_VDO1_HDR_VDO_FE0_DL_ASYNC 38 |
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| 851 | #define CLK_VDO1_HDR_VDO_FE1_DL_ASYNC 39 |
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| 852 | #define CLK_VDO1_HDR_GFX_FE0_DL_ASYNC 40 |
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| 853 | #define CLK_VDO1_HDR_GFX_FE1_DL_ASYNC 41 |
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| 854 | #define CLK_VDO1_HDR_VDO_BE_DL_ASYNC 42 |
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| 855 | #define CLK_VDO1_DPI0 43 |
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| 856 | #define CLK_VDO1_DISP_MONITOR_DPI0 44 |
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| 857 | #define CLK_VDO1_DPI1 45 |
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| 858 | #define CLK_VDO1_DISP_MONITOR_DPI1 46 |
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| 859 | #define CLK_VDO1_DPINTF 47 |
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| 860 | #define CLK_VDO1_DISP_MONITOR_DPINTF 48 |
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| 861 | #define CLK_VDO1_26M_SLOW 49 |
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| 862 | #define CLK_VDO1_DPI1_HDMI 50 |
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| 863 | #define CLK_VDO1_NR_CLK 51 |
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| 864 | |
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| 865 | |
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| 866 | #endif /* _DT_BINDINGS_CLK_MT8195_H */ |
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| 867 | |
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