1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ |
2 | /* |
3 | * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. |
4 | * Copyright (c) 2023, Linaro Limited |
5 | */ |
6 | |
7 | #ifndef _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H |
8 | #define _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H |
9 | |
10 | /* GPU_CC clocks */ |
11 | #define GPU_CC_PLL0 0 |
12 | #define GPU_CC_PLL1 1 |
13 | #define GPU_CC_AHB_CLK 2 |
14 | #define GPU_CC_CB_CLK 3 |
15 | #define GPU_CC_CRC_AHB_CLK 4 |
16 | #define GPU_CC_CX_FF_CLK 5 |
17 | #define GPU_CC_CX_GMU_CLK 6 |
18 | #define GPU_CC_CX_SNOC_DVM_CLK 7 |
19 | #define GPU_CC_CXO_AON_CLK 8 |
20 | #define GPU_CC_CXO_CLK 9 |
21 | #define GPU_CC_DEMET_CLK 10 |
22 | #define GPU_CC_DEMET_DIV_CLK_SRC 11 |
23 | #define GPU_CC_FF_CLK_SRC 12 |
24 | #define GPU_CC_GMU_CLK_SRC 13 |
25 | #define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 |
26 | #define GPU_CC_HUB_AHB_DIV_CLK_SRC 15 |
27 | #define GPU_CC_HUB_AON_CLK 16 |
28 | #define GPU_CC_HUB_CLK_SRC 17 |
29 | #define GPU_CC_HUB_CX_INT_CLK 18 |
30 | #define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 19 |
31 | #define GPU_CC_MEMNOC_GFX_CLK 20 |
32 | #define GPU_CC_SLEEP_CLK 21 |
33 | #define GPU_CC_XO_CLK_SRC 22 |
34 | |
35 | /* GPU_CC resets */ |
36 | #define GPUCC_GPU_CC_ACD_BCR 0 |
37 | #define GPUCC_GPU_CC_CB_BCR 1 |
38 | #define GPUCC_GPU_CC_CX_BCR 2 |
39 | #define GPUCC_GPU_CC_FAST_HUB_BCR 3 |
40 | #define GPUCC_GPU_CC_FF_BCR 4 |
41 | #define GPUCC_GPU_CC_GFX3D_AON_BCR 5 |
42 | #define GPUCC_GPU_CC_GMU_BCR 6 |
43 | #define GPUCC_GPU_CC_GX_BCR 7 |
44 | #define GPUCC_GPU_CC_XO_BCR 8 |
45 | |
46 | /* GPU_CC power domains */ |
47 | #define GPU_CC_CX_GDSC 0 |
48 | #define GPU_CC_GX_GDSC 1 |
49 | |
50 | #endif /* _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H */ |
51 | |