1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (c) 2021, The Linux Foundation. All rights reserved. |
4 | * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> |
5 | */ |
6 | |
7 | #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6375_H |
8 | #define _DT_BINDINGS_CLK_QCOM_GCC_SM6375_H |
9 | |
10 | /* Clocks */ |
11 | #define GPLL0 0 |
12 | #define GPLL0_OUT_EVEN 1 |
13 | #define GPLL0_OUT_ODD 2 |
14 | #define GPLL1 3 |
15 | #define GPLL10 4 |
16 | #define GPLL11 5 |
17 | #define GPLL3 6 |
18 | #define GPLL3_OUT_EVEN 7 |
19 | #define GPLL4 8 |
20 | #define GPLL5 9 |
21 | #define GPLL6 10 |
22 | #define GPLL6_OUT_EVEN 11 |
23 | #define GPLL7 12 |
24 | #define GPLL8 13 |
25 | #define GPLL8_OUT_EVEN 14 |
26 | #define GPLL9 15 |
27 | #define GPLL9_OUT_MAIN 16 |
28 | #define GCC_AHB2PHY_CSI_CLK 17 |
29 | #define GCC_AHB2PHY_USB_CLK 18 |
30 | #define GCC_BIMC_GPU_AXI_CLK 19 |
31 | #define GCC_BOOT_ROM_AHB_CLK 20 |
32 | #define GCC_CAM_THROTTLE_NRT_CLK 21 |
33 | #define GCC_CAM_THROTTLE_RT_CLK 22 |
34 | #define GCC_CAMERA_AHB_CLK 23 |
35 | #define GCC_CAMERA_XO_CLK 24 |
36 | #define GCC_CAMSS_AXI_CLK 25 |
37 | #define GCC_CAMSS_AXI_CLK_SRC 26 |
38 | #define GCC_CAMSS_CAMNOC_ATB_CLK 27 |
39 | #define GCC_CAMSS_CAMNOC_NTS_XO_CLK 28 |
40 | #define GCC_CAMSS_CCI_0_CLK 29 |
41 | #define GCC_CAMSS_CCI_0_CLK_SRC 30 |
42 | #define GCC_CAMSS_CCI_1_CLK 31 |
43 | #define GCC_CAMSS_CCI_1_CLK_SRC 32 |
44 | #define GCC_CAMSS_CPHY_0_CLK 33 |
45 | #define GCC_CAMSS_CPHY_1_CLK 34 |
46 | #define GCC_CAMSS_CPHY_2_CLK 35 |
47 | #define GCC_CAMSS_CPHY_3_CLK 36 |
48 | #define GCC_CAMSS_CSI0PHYTIMER_CLK 37 |
49 | #define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 38 |
50 | #define GCC_CAMSS_CSI1PHYTIMER_CLK 39 |
51 | #define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 40 |
52 | #define GCC_CAMSS_CSI2PHYTIMER_CLK 41 |
53 | #define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 42 |
54 | #define GCC_CAMSS_CSI3PHYTIMER_CLK 43 |
55 | #define GCC_CAMSS_CSI3PHYTIMER_CLK_SRC 44 |
56 | #define GCC_CAMSS_MCLK0_CLK 45 |
57 | #define GCC_CAMSS_MCLK0_CLK_SRC 46 |
58 | #define GCC_CAMSS_MCLK1_CLK 47 |
59 | #define GCC_CAMSS_MCLK1_CLK_SRC 48 |
60 | #define GCC_CAMSS_MCLK2_CLK 49 |
61 | #define GCC_CAMSS_MCLK2_CLK_SRC 50 |
62 | #define GCC_CAMSS_MCLK3_CLK 51 |
63 | #define GCC_CAMSS_MCLK3_CLK_SRC 52 |
64 | #define GCC_CAMSS_MCLK4_CLK 53 |
65 | #define GCC_CAMSS_MCLK4_CLK_SRC 54 |
66 | #define GCC_CAMSS_NRT_AXI_CLK 55 |
67 | #define GCC_CAMSS_OPE_AHB_CLK 56 |
68 | #define GCC_CAMSS_OPE_AHB_CLK_SRC 57 |
69 | #define GCC_CAMSS_OPE_CLK 58 |
70 | #define GCC_CAMSS_OPE_CLK_SRC 59 |
71 | #define GCC_CAMSS_RT_AXI_CLK 60 |
72 | #define GCC_CAMSS_TFE_0_CLK 61 |
73 | #define GCC_CAMSS_TFE_0_CLK_SRC 62 |
74 | #define GCC_CAMSS_TFE_0_CPHY_RX_CLK 63 |
75 | #define GCC_CAMSS_TFE_0_CSID_CLK 64 |
76 | #define GCC_CAMSS_TFE_0_CSID_CLK_SRC 65 |
77 | #define GCC_CAMSS_TFE_1_CLK 66 |
78 | #define GCC_CAMSS_TFE_1_CLK_SRC 67 |
79 | #define GCC_CAMSS_TFE_1_CPHY_RX_CLK 68 |
80 | #define GCC_CAMSS_TFE_1_CSID_CLK 69 |
81 | #define GCC_CAMSS_TFE_1_CSID_CLK_SRC 70 |
82 | #define GCC_CAMSS_TFE_2_CLK 71 |
83 | #define GCC_CAMSS_TFE_2_CLK_SRC 72 |
84 | #define GCC_CAMSS_TFE_2_CPHY_RX_CLK 73 |
85 | #define GCC_CAMSS_TFE_2_CSID_CLK 74 |
86 | #define GCC_CAMSS_TFE_2_CSID_CLK_SRC 75 |
87 | #define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 76 |
88 | #define GCC_CAMSS_TOP_AHB_CLK 77 |
89 | #define GCC_CAMSS_TOP_AHB_CLK_SRC 78 |
90 | #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 79 |
91 | #define GCC_CPUSS_AHB_CLK_SRC 80 |
92 | #define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 81 |
93 | #define GCC_CPUSS_GNOC_CLK 82 |
94 | #define GCC_DISP_AHB_CLK 83 |
95 | #define GCC_DISP_GPLL0_CLK_SRC 84 |
96 | #define GCC_DISP_GPLL0_DIV_CLK_SRC 85 |
97 | #define GCC_DISP_HF_AXI_CLK 86 |
98 | #define GCC_DISP_SLEEP_CLK 87 |
99 | #define GCC_DISP_THROTTLE_CORE_CLK 88 |
100 | #define GCC_DISP_XO_CLK 89 |
101 | #define GCC_GP1_CLK 90 |
102 | #define GCC_GP1_CLK_SRC 91 |
103 | #define GCC_GP2_CLK 92 |
104 | #define GCC_GP2_CLK_SRC 93 |
105 | #define GCC_GP3_CLK 94 |
106 | #define GCC_GP3_CLK_SRC 95 |
107 | #define GCC_GPU_CFG_AHB_CLK 96 |
108 | #define GCC_GPU_GPLL0_CLK_SRC 97 |
109 | #define GCC_GPU_GPLL0_DIV_CLK_SRC 98 |
110 | #define GCC_GPU_MEMNOC_GFX_CLK 99 |
111 | #define GCC_GPU_SNOC_DVM_GFX_CLK 100 |
112 | #define GCC_GPU_THROTTLE_CORE_CLK 101 |
113 | #define GCC_PDM2_CLK 102 |
114 | #define GCC_PDM2_CLK_SRC 103 |
115 | #define GCC_PDM_AHB_CLK 104 |
116 | #define GCC_PDM_XO4_CLK 105 |
117 | #define GCC_PRNG_AHB_CLK 106 |
118 | #define GCC_QMIP_CAMERA_NRT_AHB_CLK 107 |
119 | #define GCC_QMIP_CAMERA_RT_AHB_CLK 108 |
120 | #define GCC_QMIP_DISP_AHB_CLK 109 |
121 | #define GCC_QMIP_GPU_CFG_AHB_CLK 110 |
122 | #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 111 |
123 | #define GCC_QUPV3_WRAP0_CORE_2X_CLK 112 |
124 | #define GCC_QUPV3_WRAP0_CORE_CLK 113 |
125 | #define GCC_QUPV3_WRAP0_S0_CLK 114 |
126 | #define GCC_QUPV3_WRAP0_S0_CLK_SRC 115 |
127 | #define GCC_QUPV3_WRAP0_S1_CLK 116 |
128 | #define GCC_QUPV3_WRAP0_S1_CLK_SRC 117 |
129 | #define GCC_QUPV3_WRAP0_S2_CLK 118 |
130 | #define GCC_QUPV3_WRAP0_S2_CLK_SRC 119 |
131 | #define GCC_QUPV3_WRAP0_S3_CLK 120 |
132 | #define GCC_QUPV3_WRAP0_S3_CLK_SRC 121 |
133 | #define GCC_QUPV3_WRAP0_S4_CLK 122 |
134 | #define GCC_QUPV3_WRAP0_S4_CLK_SRC 123 |
135 | #define GCC_QUPV3_WRAP0_S5_CLK 124 |
136 | #define GCC_QUPV3_WRAP0_S5_CLK_SRC 125 |
137 | #define GCC_QUPV3_WRAP1_CORE_2X_CLK 126 |
138 | #define GCC_QUPV3_WRAP1_CORE_CLK 127 |
139 | #define GCC_QUPV3_WRAP1_S0_CLK 128 |
140 | #define GCC_QUPV3_WRAP1_S0_CLK_SRC 129 |
141 | #define GCC_QUPV3_WRAP1_S1_CLK 130 |
142 | #define GCC_QUPV3_WRAP1_S1_CLK_SRC 131 |
143 | #define GCC_QUPV3_WRAP1_S2_CLK 132 |
144 | #define GCC_QUPV3_WRAP1_S2_CLK_SRC 133 |
145 | #define GCC_QUPV3_WRAP1_S3_CLK 134 |
146 | #define GCC_QUPV3_WRAP1_S3_CLK_SRC 135 |
147 | #define GCC_QUPV3_WRAP1_S4_CLK 136 |
148 | #define GCC_QUPV3_WRAP1_S4_CLK_SRC 137 |
149 | #define GCC_QUPV3_WRAP1_S5_CLK 138 |
150 | #define GCC_QUPV3_WRAP1_S5_CLK_SRC 139 |
151 | #define GCC_QUPV3_WRAP_0_M_AHB_CLK 140 |
152 | #define GCC_QUPV3_WRAP_0_S_AHB_CLK 141 |
153 | #define GCC_QUPV3_WRAP_1_M_AHB_CLK 142 |
154 | #define GCC_QUPV3_WRAP_1_S_AHB_CLK 143 |
155 | #define GCC_RX5_PCIE_CLKREF_EN_CLK 144 |
156 | #define GCC_SDCC1_AHB_CLK 145 |
157 | #define GCC_SDCC1_APPS_CLK 146 |
158 | #define GCC_SDCC1_APPS_CLK_SRC 147 |
159 | #define GCC_SDCC1_ICE_CORE_CLK 148 |
160 | #define GCC_SDCC1_ICE_CORE_CLK_SRC 149 |
161 | #define GCC_SDCC2_AHB_CLK 150 |
162 | #define GCC_SDCC2_APPS_CLK 151 |
163 | #define GCC_SDCC2_APPS_CLK_SRC 152 |
164 | #define GCC_SYS_NOC_CPUSS_AHB_CLK 153 |
165 | #define GCC_SYS_NOC_UFS_PHY_AXI_CLK 154 |
166 | #define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 155 |
167 | #define GCC_UFS_MEM_CLKREF_CLK 156 |
168 | #define GCC_UFS_PHY_AHB_CLK 157 |
169 | #define GCC_UFS_PHY_AXI_CLK 158 |
170 | #define GCC_UFS_PHY_AXI_CLK_SRC 159 |
171 | #define GCC_UFS_PHY_ICE_CORE_CLK 160 |
172 | #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 161 |
173 | #define GCC_UFS_PHY_PHY_AUX_CLK 162 |
174 | #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 163 |
175 | #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 164 |
176 | #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 165 |
177 | #define GCC_UFS_PHY_UNIPRO_CORE_CLK 166 |
178 | #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 167 |
179 | #define GCC_USB30_PRIM_MASTER_CLK 168 |
180 | #define GCC_USB30_PRIM_MASTER_CLK_SRC 169 |
181 | #define GCC_USB30_PRIM_MOCK_UTMI_CLK 170 |
182 | #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 171 |
183 | #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 172 |
184 | #define GCC_USB30_PRIM_SLEEP_CLK 173 |
185 | #define GCC_USB3_PRIM_CLKREF_CLK 174 |
186 | #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 175 |
187 | #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 176 |
188 | #define GCC_USB3_PRIM_PHY_PIPE_CLK 177 |
189 | #define GCC_VCODEC0_AXI_CLK 178 |
190 | #define GCC_VENUS_AHB_CLK 179 |
191 | #define GCC_VENUS_CTL_AXI_CLK 180 |
192 | #define GCC_VIDEO_AHB_CLK 181 |
193 | #define GCC_VIDEO_AXI0_CLK 182 |
194 | #define GCC_VIDEO_THROTTLE_CORE_CLK 183 |
195 | #define GCC_VIDEO_VCODEC0_SYS_CLK 184 |
196 | #define GCC_VIDEO_VENUS_CLK_SRC 185 |
197 | #define GCC_VIDEO_VENUS_CTL_CLK 186 |
198 | #define GCC_VIDEO_XO_CLK 187 |
199 | |
200 | /* Resets */ |
201 | #define GCC_CAMSS_OPE_BCR 0 |
202 | #define GCC_CAMSS_TFE_BCR 1 |
203 | #define GCC_CAMSS_TOP_BCR 2 |
204 | #define GCC_GPU_BCR 3 |
205 | #define GCC_MMSS_BCR 4 |
206 | #define GCC_PDM_BCR 5 |
207 | #define GCC_PRNG_BCR 6 |
208 | #define GCC_QUPV3_WRAPPER_0_BCR 7 |
209 | #define GCC_QUPV3_WRAPPER_1_BCR 8 |
210 | #define GCC_QUSB2PHY_PRIM_BCR 9 |
211 | #define GCC_QUSB2PHY_SEC_BCR 10 |
212 | #define GCC_SDCC1_BCR 11 |
213 | #define GCC_SDCC2_BCR 12 |
214 | #define GCC_UFS_PHY_BCR 13 |
215 | #define GCC_USB30_PRIM_BCR 14 |
216 | #define GCC_USB_PHY_CFG_AHB2PHY_BCR 15 |
217 | #define GCC_VCODEC0_BCR 16 |
218 | #define GCC_VENUS_BCR 17 |
219 | #define GCC_VIDEO_INTERFACE_BCR 18 |
220 | #define GCC_USB3_DP_PHY_PRIM_BCR 19 |
221 | #define GCC_USB3_PHY_PRIM_SP0_BCR 20 |
222 | |
223 | /* GDSCs */ |
224 | #define USB30_PRIM_GDSC 0 |
225 | #define UFS_PHY_GDSC 1 |
226 | #define CAMSS_TOP_GDSC 2 |
227 | #define VENUS_GDSC 3 |
228 | #define VCODEC0_GDSC 4 |
229 | #define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC 5 |
230 | #define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC 6 |
231 | #define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 7 |
232 | #define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 8 |
233 | |
234 | #endif |
235 | |