1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* Freescale Integrated Flash Controller |
3 | * |
4 | * Copyright 2011 Freescale Semiconductor, Inc |
5 | * |
6 | * Author: Dipen Dudhat <dipen.dudhat@freescale.com> |
7 | */ |
8 | |
9 | #ifndef __ASM_FSL_IFC_H |
10 | #define __ASM_FSL_IFC_H |
11 | |
12 | #include <linux/compiler.h> |
13 | #include <linux/types.h> |
14 | #include <linux/io.h> |
15 | |
16 | #include <linux/of_platform.h> |
17 | #include <linux/interrupt.h> |
18 | |
19 | /* |
20 | * The actual number of banks implemented depends on the IFC version |
21 | * - IFC version 1.0 implements 4 banks. |
22 | * - IFC version 1.1 onward implements 8 banks. |
23 | */ |
24 | #define FSL_IFC_BANK_COUNT 8 |
25 | |
26 | #define FSL_IFC_VERSION_MASK 0x0F0F0000 |
27 | #define FSL_IFC_VERSION_1_0_0 0x01000000 |
28 | #define FSL_IFC_VERSION_1_1_0 0x01010000 |
29 | #define FSL_IFC_VERSION_2_0_0 0x02000000 |
30 | |
31 | #define PGOFFSET_64K (64*1024) |
32 | #define PGOFFSET_4K (4*1024) |
33 | |
34 | /* |
35 | * CSPR - Chip Select Property Register |
36 | */ |
37 | #define CSPR_BA 0xFFFF0000 |
38 | #define CSPR_BA_SHIFT 16 |
39 | #define CSPR_PORT_SIZE 0x00000180 |
40 | #define CSPR_PORT_SIZE_SHIFT 7 |
41 | /* Port Size 8 bit */ |
42 | #define CSPR_PORT_SIZE_8 0x00000080 |
43 | /* Port Size 16 bit */ |
44 | #define CSPR_PORT_SIZE_16 0x00000100 |
45 | /* Port Size 32 bit */ |
46 | #define CSPR_PORT_SIZE_32 0x00000180 |
47 | /* Write Protect */ |
48 | #define CSPR_WP 0x00000040 |
49 | #define CSPR_WP_SHIFT 6 |
50 | /* Machine Select */ |
51 | #define CSPR_MSEL 0x00000006 |
52 | #define CSPR_MSEL_SHIFT 1 |
53 | /* NOR */ |
54 | #define CSPR_MSEL_NOR 0x00000000 |
55 | /* NAND */ |
56 | #define CSPR_MSEL_NAND 0x00000002 |
57 | /* GPCM */ |
58 | #define CSPR_MSEL_GPCM 0x00000004 |
59 | /* Bank Valid */ |
60 | #define CSPR_V 0x00000001 |
61 | #define CSPR_V_SHIFT 0 |
62 | |
63 | /* |
64 | * Address Mask Register |
65 | */ |
66 | #define IFC_AMASK_MASK 0xFFFF0000 |
67 | #define IFC_AMASK_SHIFT 16 |
68 | #define IFC_AMASK(n) (IFC_AMASK_MASK << \ |
69 | (__ilog2(n) - IFC_AMASK_SHIFT)) |
70 | |
71 | /* |
72 | * Chip Select Option Register IFC_NAND Machine |
73 | */ |
74 | /* Enable ECC Encoder */ |
75 | #define CSOR_NAND_ECC_ENC_EN 0x80000000 |
76 | #define CSOR_NAND_ECC_MODE_MASK 0x30000000 |
77 | /* 4 bit correction per 520 Byte sector */ |
78 | #define CSOR_NAND_ECC_MODE_4 0x00000000 |
79 | /* 8 bit correction per 528 Byte sector */ |
80 | #define CSOR_NAND_ECC_MODE_8 0x10000000 |
81 | /* Enable ECC Decoder */ |
82 | #define CSOR_NAND_ECC_DEC_EN 0x04000000 |
83 | /* Row Address Length */ |
84 | #define CSOR_NAND_RAL_MASK 0x01800000 |
85 | #define CSOR_NAND_RAL_SHIFT 20 |
86 | #define CSOR_NAND_RAL_1 0x00000000 |
87 | #define CSOR_NAND_RAL_2 0x00800000 |
88 | #define CSOR_NAND_RAL_3 0x01000000 |
89 | #define CSOR_NAND_RAL_4 0x01800000 |
90 | /* Page Size 512b, 2k, 4k */ |
91 | #define CSOR_NAND_PGS_MASK 0x00180000 |
92 | #define CSOR_NAND_PGS_SHIFT 16 |
93 | #define CSOR_NAND_PGS_512 0x00000000 |
94 | #define CSOR_NAND_PGS_2K 0x00080000 |
95 | #define CSOR_NAND_PGS_4K 0x00100000 |
96 | #define CSOR_NAND_PGS_8K 0x00180000 |
97 | /* Spare region Size */ |
98 | #define CSOR_NAND_SPRZ_MASK 0x0000E000 |
99 | #define CSOR_NAND_SPRZ_SHIFT 13 |
100 | #define CSOR_NAND_SPRZ_16 0x00000000 |
101 | #define CSOR_NAND_SPRZ_64 0x00002000 |
102 | #define CSOR_NAND_SPRZ_128 0x00004000 |
103 | #define CSOR_NAND_SPRZ_210 0x00006000 |
104 | #define CSOR_NAND_SPRZ_218 0x00008000 |
105 | #define CSOR_NAND_SPRZ_224 0x0000A000 |
106 | #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 |
107 | /* Pages Per Block */ |
108 | #define CSOR_NAND_PB_MASK 0x00000700 |
109 | #define CSOR_NAND_PB_SHIFT 8 |
110 | #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) |
111 | /* Time for Read Enable High to Output High Impedance */ |
112 | #define CSOR_NAND_TRHZ_MASK 0x0000001C |
113 | #define CSOR_NAND_TRHZ_SHIFT 2 |
114 | #define CSOR_NAND_TRHZ_20 0x00000000 |
115 | #define CSOR_NAND_TRHZ_40 0x00000004 |
116 | #define CSOR_NAND_TRHZ_60 0x00000008 |
117 | #define CSOR_NAND_TRHZ_80 0x0000000C |
118 | #define CSOR_NAND_TRHZ_100 0x00000010 |
119 | /* Buffer control disable */ |
120 | #define CSOR_NAND_BCTLD 0x00000001 |
121 | |
122 | /* |
123 | * Chip Select Option Register - NOR Flash Mode |
124 | */ |
125 | /* Enable Address shift Mode */ |
126 | #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 |
127 | /* Page Read Enable from NOR device */ |
128 | #define CSOR_NOR_PGRD_EN 0x10000000 |
129 | /* AVD Toggle Enable during Burst Program */ |
130 | #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 |
131 | /* Address Data Multiplexing Shift */ |
132 | #define CSOR_NOR_ADM_MASK 0x0003E000 |
133 | #define CSOR_NOR_ADM_SHIFT_SHIFT 13 |
134 | #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) |
135 | /* Type of the NOR device hooked */ |
136 | #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 |
137 | #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 |
138 | /* Time for Read Enable High to Output High Impedance */ |
139 | #define CSOR_NOR_TRHZ_MASK 0x0000001C |
140 | #define CSOR_NOR_TRHZ_SHIFT 2 |
141 | #define CSOR_NOR_TRHZ_20 0x00000000 |
142 | #define CSOR_NOR_TRHZ_40 0x00000004 |
143 | #define CSOR_NOR_TRHZ_60 0x00000008 |
144 | #define CSOR_NOR_TRHZ_80 0x0000000C |
145 | #define CSOR_NOR_TRHZ_100 0x00000010 |
146 | /* Buffer control disable */ |
147 | #define CSOR_NOR_BCTLD 0x00000001 |
148 | |
149 | /* |
150 | * Chip Select Option Register - GPCM Mode |
151 | */ |
152 | /* GPCM Mode - Normal */ |
153 | #define CSOR_GPCM_GPMODE_NORMAL 0x00000000 |
154 | /* GPCM Mode - GenericASIC */ |
155 | #define CSOR_GPCM_GPMODE_ASIC 0x80000000 |
156 | /* Parity Mode odd/even */ |
157 | #define CSOR_GPCM_PARITY_EVEN 0x40000000 |
158 | /* Parity Checking enable/disable */ |
159 | #define CSOR_GPCM_PAR_EN 0x20000000 |
160 | /* GPCM Timeout Count */ |
161 | #define CSOR_GPCM_GPTO_MASK 0x0F000000 |
162 | #define CSOR_GPCM_GPTO_SHIFT 24 |
163 | #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) |
164 | /* GPCM External Access Termination mode for read access */ |
165 | #define CSOR_GPCM_RGETA_EXT 0x00080000 |
166 | /* GPCM External Access Termination mode for write access */ |
167 | #define CSOR_GPCM_WGETA_EXT 0x00040000 |
168 | /* Address Data Multiplexing Shift */ |
169 | #define CSOR_GPCM_ADM_MASK 0x0003E000 |
170 | #define CSOR_GPCM_ADM_SHIFT_SHIFT 13 |
171 | #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) |
172 | /* Generic ASIC Parity error indication delay */ |
173 | #define CSOR_GPCM_GAPERRD_MASK 0x00000180 |
174 | #define CSOR_GPCM_GAPERRD_SHIFT 7 |
175 | #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) |
176 | /* Time for Read Enable High to Output High Impedance */ |
177 | #define CSOR_GPCM_TRHZ_MASK 0x0000001C |
178 | #define CSOR_GPCM_TRHZ_20 0x00000000 |
179 | #define CSOR_GPCM_TRHZ_40 0x00000004 |
180 | #define CSOR_GPCM_TRHZ_60 0x00000008 |
181 | #define CSOR_GPCM_TRHZ_80 0x0000000C |
182 | #define CSOR_GPCM_TRHZ_100 0x00000010 |
183 | /* Buffer control disable */ |
184 | #define CSOR_GPCM_BCTLD 0x00000001 |
185 | |
186 | /* |
187 | * Ready Busy Status Register (RB_STAT) |
188 | */ |
189 | /* CSn is READY */ |
190 | #define IFC_RB_STAT_READY_CS0 0x80000000 |
191 | #define IFC_RB_STAT_READY_CS1 0x40000000 |
192 | #define IFC_RB_STAT_READY_CS2 0x20000000 |
193 | #define IFC_RB_STAT_READY_CS3 0x10000000 |
194 | |
195 | /* |
196 | * General Control Register (GCR) |
197 | */ |
198 | #define IFC_GCR_MASK 0x8000F800 |
199 | /* reset all IFC hardware */ |
200 | #define IFC_GCR_SOFT_RST_ALL 0x80000000 |
201 | /* Turnaroud Time of external buffer */ |
202 | #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 |
203 | #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 |
204 | |
205 | /* |
206 | * Common Event and Error Status Register (CM_EVTER_STAT) |
207 | */ |
208 | /* Chip select error */ |
209 | #define IFC_CM_EVTER_STAT_CSER 0x80000000 |
210 | |
211 | /* |
212 | * Common Event and Error Enable Register (CM_EVTER_EN) |
213 | */ |
214 | /* Chip select error checking enable */ |
215 | #define IFC_CM_EVTER_EN_CSEREN 0x80000000 |
216 | |
217 | /* |
218 | * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) |
219 | */ |
220 | /* Chip select error interrupt enable */ |
221 | #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 |
222 | |
223 | /* |
224 | * Common Transfer Error Attribute Register-0 (CM_ERATTR0) |
225 | */ |
226 | /* transaction type of error Read/Write */ |
227 | #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 |
228 | #define IFC_CM_ERATTR0_ERAID 0x0FF00000 |
229 | #define IFC_CM_ERATTR0_ERAID_SHIFT 20 |
230 | #define IFC_CM_ERATTR0_ESRCID 0x0000FF00 |
231 | #define IFC_CM_ERATTR0_ESRCID_SHIFT 8 |
232 | |
233 | /* |
234 | * Clock Control Register (CCR) |
235 | */ |
236 | #define IFC_CCR_MASK 0x0F0F8800 |
237 | /* Clock division ratio */ |
238 | #define IFC_CCR_CLK_DIV_MASK 0x0F000000 |
239 | #define IFC_CCR_CLK_DIV_SHIFT 24 |
240 | #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) |
241 | /* IFC Clock Delay */ |
242 | #define IFC_CCR_CLK_DLY_MASK 0x000F0000 |
243 | #define IFC_CCR_CLK_DLY_SHIFT 16 |
244 | #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) |
245 | /* Invert IFC clock before sending out */ |
246 | #define IFC_CCR_INV_CLK_EN 0x00008000 |
247 | /* Fedback IFC Clock */ |
248 | #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 |
249 | |
250 | /* |
251 | * Clock Status Register (CSR) |
252 | */ |
253 | /* Clk is stable */ |
254 | #define IFC_CSR_CLK_STAT_STABLE 0x80000000 |
255 | |
256 | /* |
257 | * IFC_NAND Machine Specific Registers |
258 | */ |
259 | /* |
260 | * NAND Configuration Register (NCFGR) |
261 | */ |
262 | /* Auto Boot Mode */ |
263 | #define IFC_NAND_NCFGR_BOOT 0x80000000 |
264 | /* SRAM Initialization */ |
265 | #define IFC_NAND_NCFGR_SRAM_INIT_EN 0x20000000 |
266 | /* Addressing Mode-ROW0+n/COL0 */ |
267 | #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 |
268 | /* Addressing Mode-ROW0+n/COL0+n */ |
269 | #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 |
270 | /* Number of loop iterations of FIR sequences for multi page operations */ |
271 | #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 |
272 | #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 |
273 | #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) |
274 | /* Number of wait cycles */ |
275 | #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF |
276 | #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 |
277 | |
278 | /* |
279 | * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) |
280 | */ |
281 | /* General purpose FCM flash command bytes CMD0-CMD7 */ |
282 | #define IFC_NAND_FCR0_CMD0 0xFF000000 |
283 | #define IFC_NAND_FCR0_CMD0_SHIFT 24 |
284 | #define IFC_NAND_FCR0_CMD1 0x00FF0000 |
285 | #define IFC_NAND_FCR0_CMD1_SHIFT 16 |
286 | #define IFC_NAND_FCR0_CMD2 0x0000FF00 |
287 | #define IFC_NAND_FCR0_CMD2_SHIFT 8 |
288 | #define IFC_NAND_FCR0_CMD3 0x000000FF |
289 | #define IFC_NAND_FCR0_CMD3_SHIFT 0 |
290 | #define IFC_NAND_FCR1_CMD4 0xFF000000 |
291 | #define IFC_NAND_FCR1_CMD4_SHIFT 24 |
292 | #define IFC_NAND_FCR1_CMD5 0x00FF0000 |
293 | #define IFC_NAND_FCR1_CMD5_SHIFT 16 |
294 | #define IFC_NAND_FCR1_CMD6 0x0000FF00 |
295 | #define IFC_NAND_FCR1_CMD6_SHIFT 8 |
296 | #define IFC_NAND_FCR1_CMD7 0x000000FF |
297 | #define IFC_NAND_FCR1_CMD7_SHIFT 0 |
298 | |
299 | /* |
300 | * Flash ROW and COL Address Register (ROWn, COLn) |
301 | */ |
302 | /* Main/spare region locator */ |
303 | #define IFC_NAND_COL_MS 0x80000000 |
304 | /* Column Address */ |
305 | #define IFC_NAND_COL_CA_MASK 0x00000FFF |
306 | |
307 | /* |
308 | * NAND Flash Byte Count Register (NAND_BC) |
309 | */ |
310 | /* Byte Count for read/Write */ |
311 | #define IFC_NAND_BC 0x000001FF |
312 | |
313 | /* |
314 | * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) |
315 | */ |
316 | /* NAND Machine specific opcodes OP0-OP14*/ |
317 | #define IFC_NAND_FIR0_OP0 0xFC000000 |
318 | #define IFC_NAND_FIR0_OP0_SHIFT 26 |
319 | #define IFC_NAND_FIR0_OP1 0x03F00000 |
320 | #define IFC_NAND_FIR0_OP1_SHIFT 20 |
321 | #define IFC_NAND_FIR0_OP2 0x000FC000 |
322 | #define IFC_NAND_FIR0_OP2_SHIFT 14 |
323 | #define IFC_NAND_FIR0_OP3 0x00003F00 |
324 | #define IFC_NAND_FIR0_OP3_SHIFT 8 |
325 | #define IFC_NAND_FIR0_OP4 0x000000FC |
326 | #define IFC_NAND_FIR0_OP4_SHIFT 2 |
327 | #define IFC_NAND_FIR1_OP5 0xFC000000 |
328 | #define IFC_NAND_FIR1_OP5_SHIFT 26 |
329 | #define IFC_NAND_FIR1_OP6 0x03F00000 |
330 | #define IFC_NAND_FIR1_OP6_SHIFT 20 |
331 | #define IFC_NAND_FIR1_OP7 0x000FC000 |
332 | #define IFC_NAND_FIR1_OP7_SHIFT 14 |
333 | #define IFC_NAND_FIR1_OP8 0x00003F00 |
334 | #define IFC_NAND_FIR1_OP8_SHIFT 8 |
335 | #define IFC_NAND_FIR1_OP9 0x000000FC |
336 | #define IFC_NAND_FIR1_OP9_SHIFT 2 |
337 | #define IFC_NAND_FIR2_OP10 0xFC000000 |
338 | #define IFC_NAND_FIR2_OP10_SHIFT 26 |
339 | #define IFC_NAND_FIR2_OP11 0x03F00000 |
340 | #define IFC_NAND_FIR2_OP11_SHIFT 20 |
341 | #define IFC_NAND_FIR2_OP12 0x000FC000 |
342 | #define IFC_NAND_FIR2_OP12_SHIFT 14 |
343 | #define IFC_NAND_FIR2_OP13 0x00003F00 |
344 | #define IFC_NAND_FIR2_OP13_SHIFT 8 |
345 | #define IFC_NAND_FIR2_OP14 0x000000FC |
346 | #define IFC_NAND_FIR2_OP14_SHIFT 2 |
347 | |
348 | /* |
349 | * Instruction opcodes to be programmed |
350 | * in FIR registers- 6bits |
351 | */ |
352 | enum ifc_nand_fir_opcodes { |
353 | IFC_FIR_OP_NOP, |
354 | IFC_FIR_OP_CA0, |
355 | IFC_FIR_OP_CA1, |
356 | IFC_FIR_OP_CA2, |
357 | IFC_FIR_OP_CA3, |
358 | IFC_FIR_OP_RA0, |
359 | IFC_FIR_OP_RA1, |
360 | IFC_FIR_OP_RA2, |
361 | IFC_FIR_OP_RA3, |
362 | IFC_FIR_OP_CMD0, |
363 | IFC_FIR_OP_CMD1, |
364 | IFC_FIR_OP_CMD2, |
365 | IFC_FIR_OP_CMD3, |
366 | IFC_FIR_OP_CMD4, |
367 | IFC_FIR_OP_CMD5, |
368 | IFC_FIR_OP_CMD6, |
369 | IFC_FIR_OP_CMD7, |
370 | IFC_FIR_OP_CW0, |
371 | IFC_FIR_OP_CW1, |
372 | IFC_FIR_OP_CW2, |
373 | IFC_FIR_OP_CW3, |
374 | IFC_FIR_OP_CW4, |
375 | IFC_FIR_OP_CW5, |
376 | IFC_FIR_OP_CW6, |
377 | IFC_FIR_OP_CW7, |
378 | IFC_FIR_OP_WBCD, |
379 | IFC_FIR_OP_RBCD, |
380 | IFC_FIR_OP_BTRD, |
381 | IFC_FIR_OP_RDSTAT, |
382 | IFC_FIR_OP_NWAIT, |
383 | IFC_FIR_OP_WFR, |
384 | IFC_FIR_OP_SBRD, |
385 | IFC_FIR_OP_UA, |
386 | IFC_FIR_OP_RB, |
387 | }; |
388 | |
389 | /* |
390 | * NAND Chip Select Register (NAND_CSEL) |
391 | */ |
392 | #define IFC_NAND_CSEL 0x0C000000 |
393 | #define IFC_NAND_CSEL_SHIFT 26 |
394 | #define IFC_NAND_CSEL_CS0 0x00000000 |
395 | #define IFC_NAND_CSEL_CS1 0x04000000 |
396 | #define IFC_NAND_CSEL_CS2 0x08000000 |
397 | #define IFC_NAND_CSEL_CS3 0x0C000000 |
398 | |
399 | /* |
400 | * NAND Operation Sequence Start (NANDSEQ_STRT) |
401 | */ |
402 | /* NAND Flash Operation Start */ |
403 | #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 |
404 | /* Automatic Erase */ |
405 | #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 |
406 | /* Automatic Program */ |
407 | #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 |
408 | /* Automatic Copyback */ |
409 | #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 |
410 | /* Automatic Read Operation */ |
411 | #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 |
412 | /* Automatic Status Read */ |
413 | #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 |
414 | |
415 | /* |
416 | * NAND Event and Error Status Register (NAND_EVTER_STAT) |
417 | */ |
418 | /* Operation Complete */ |
419 | #define IFC_NAND_EVTER_STAT_OPC 0x80000000 |
420 | /* Flash Timeout Error */ |
421 | #define IFC_NAND_EVTER_STAT_FTOER 0x08000000 |
422 | /* Write Protect Error */ |
423 | #define IFC_NAND_EVTER_STAT_WPER 0x04000000 |
424 | /* ECC Error */ |
425 | #define IFC_NAND_EVTER_STAT_ECCER 0x02000000 |
426 | /* RCW Load Done */ |
427 | #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 |
428 | /* Boot Loadr Done */ |
429 | #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 |
430 | /* Bad Block Indicator search select */ |
431 | #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 |
432 | |
433 | /* |
434 | * NAND Flash Page Read Completion Event Status Register |
435 | * (PGRDCMPL_EVT_STAT) |
436 | */ |
437 | #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 |
438 | /* Small Page 0-15 Done */ |
439 | #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) |
440 | /* Large Page(2K) 0-3 Done */ |
441 | #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) |
442 | /* Large Page(4K) 0-1 Done */ |
443 | #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) |
444 | |
445 | /* |
446 | * NAND Event and Error Enable Register (NAND_EVTER_EN) |
447 | */ |
448 | /* Operation complete event enable */ |
449 | #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 |
450 | /* Page read complete event enable */ |
451 | #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 |
452 | /* Flash Timeout error enable */ |
453 | #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 |
454 | /* Write Protect error enable */ |
455 | #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 |
456 | /* ECC error logging enable */ |
457 | #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 |
458 | |
459 | /* |
460 | * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) |
461 | */ |
462 | /* Enable interrupt for operation complete */ |
463 | #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 |
464 | /* Enable interrupt for Page read complete */ |
465 | #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 |
466 | /* Enable interrupt for Flash timeout error */ |
467 | #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 |
468 | /* Enable interrupt for Write protect error */ |
469 | #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 |
470 | /* Enable interrupt for ECC error*/ |
471 | #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 |
472 | |
473 | /* |
474 | * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) |
475 | */ |
476 | #define IFC_NAND_ERATTR0_MASK 0x0C080000 |
477 | /* Error on CS0-3 for NAND */ |
478 | #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 |
479 | #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 |
480 | #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 |
481 | #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 |
482 | /* Transaction type of error Read/Write */ |
483 | #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 |
484 | |
485 | /* |
486 | * NAND Flash Status Register (NAND_FSR) |
487 | */ |
488 | /* First byte of data read from read status op */ |
489 | #define IFC_NAND_NFSR_RS0 0xFF000000 |
490 | /* Second byte of data read from read status op */ |
491 | #define IFC_NAND_NFSR_RS1 0x00FF0000 |
492 | |
493 | /* |
494 | * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) |
495 | */ |
496 | /* Number of ECC errors on sector n (n = 0-15) */ |
497 | #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 |
498 | #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 |
499 | #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 |
500 | #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 |
501 | #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 |
502 | #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 |
503 | #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F |
504 | #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 |
505 | #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 |
506 | #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 |
507 | #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 |
508 | #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 |
509 | #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 |
510 | #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 |
511 | #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F |
512 | #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 |
513 | #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 |
514 | #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 |
515 | #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 |
516 | #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 |
517 | #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 |
518 | #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 |
519 | #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F |
520 | #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 |
521 | #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 |
522 | #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 |
523 | #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 |
524 | #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 |
525 | #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 |
526 | #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 |
527 | #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F |
528 | #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 |
529 | |
530 | /* |
531 | * NAND Control Register (NANDCR) |
532 | */ |
533 | #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 |
534 | #define IFC_NAND_NCR_FTOCNT_SHIFT 25 |
535 | #define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) |
536 | |
537 | /* |
538 | * NAND_AUTOBOOT_TRGR |
539 | */ |
540 | /* Trigger RCW load */ |
541 | #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 |
542 | /* Trigget Auto Boot */ |
543 | #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 |
544 | |
545 | /* |
546 | * NAND_MDR |
547 | */ |
548 | /* 1st read data byte when opcode SBRD */ |
549 | #define IFC_NAND_MDR_RDATA0 0xFF000000 |
550 | /* 2nd read data byte when opcode SBRD */ |
551 | #define IFC_NAND_MDR_RDATA1 0x00FF0000 |
552 | |
553 | /* |
554 | * NOR Machine Specific Registers |
555 | */ |
556 | /* |
557 | * NOR Event and Error Status Register (NOR_EVTER_STAT) |
558 | */ |
559 | /* NOR Command Sequence Operation Complete */ |
560 | #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 |
561 | /* Write Protect Error */ |
562 | #define IFC_NOR_EVTER_STAT_WPER 0x04000000 |
563 | /* Command Sequence Timeout Error */ |
564 | #define IFC_NOR_EVTER_STAT_STOER 0x01000000 |
565 | |
566 | /* |
567 | * NOR Event and Error Enable Register (NOR_EVTER_EN) |
568 | */ |
569 | /* NOR Command Seq complete event enable */ |
570 | #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 |
571 | /* Write Protect Error Checking Enable */ |
572 | #define IFC_NOR_EVTER_EN_WPEREN 0x04000000 |
573 | /* Timeout Error Enable */ |
574 | #define IFC_NOR_EVTER_EN_STOEREN 0x01000000 |
575 | |
576 | /* |
577 | * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) |
578 | */ |
579 | /* Enable interrupt for OPC complete */ |
580 | #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 |
581 | /* Enable interrupt for write protect error */ |
582 | #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 |
583 | /* Enable interrupt for timeout error */ |
584 | #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 |
585 | |
586 | /* |
587 | * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) |
588 | */ |
589 | /* Source ID for error transaction */ |
590 | #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 |
591 | /* AXI ID for error transation */ |
592 | #define IFC_NOR_ERATTR0_ERAID 0x000FF000 |
593 | /* Chip select corresponds to NOR error */ |
594 | #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 |
595 | #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 |
596 | #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 |
597 | #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 |
598 | /* Type of transaction read/write */ |
599 | #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 |
600 | |
601 | /* |
602 | * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) |
603 | */ |
604 | #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 |
605 | #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 |
606 | |
607 | /* |
608 | * NOR Control Register (NORCR) |
609 | */ |
610 | #define IFC_NORCR_MASK 0x0F0F0000 |
611 | /* No. of Address/Data Phase */ |
612 | #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 |
613 | #define IFC_NORCR_NUM_PHASE_SHIFT 24 |
614 | #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) |
615 | /* Sequence Timeout Count */ |
616 | #define IFC_NORCR_STOCNT_MASK 0x000F0000 |
617 | #define IFC_NORCR_STOCNT_SHIFT 16 |
618 | #define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) |
619 | |
620 | /* |
621 | * GPCM Machine specific registers |
622 | */ |
623 | /* |
624 | * GPCM Event and Error Status Register (GPCM_EVTER_STAT) |
625 | */ |
626 | /* Timeout error */ |
627 | #define IFC_GPCM_EVTER_STAT_TOER 0x04000000 |
628 | /* Parity error */ |
629 | #define IFC_GPCM_EVTER_STAT_PER 0x01000000 |
630 | |
631 | /* |
632 | * GPCM Event and Error Enable Register (GPCM_EVTER_EN) |
633 | */ |
634 | /* Timeout error enable */ |
635 | #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 |
636 | /* Parity error enable */ |
637 | #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 |
638 | |
639 | /* |
640 | * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) |
641 | */ |
642 | /* Enable Interrupt for timeout error */ |
643 | #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 |
644 | /* Enable Interrupt for Parity error */ |
645 | #define IFC_GPCM_EEIER_PERIR_EN 0x01000000 |
646 | |
647 | /* |
648 | * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) |
649 | */ |
650 | /* Source ID for error transaction */ |
651 | #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 |
652 | /* AXI ID for error transaction */ |
653 | #define IFC_GPCM_ERATTR0_ERAID 0x000FF000 |
654 | /* Chip select corresponds to GPCM error */ |
655 | #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 |
656 | #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 |
657 | #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 |
658 | #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 |
659 | /* Type of transaction read/Write */ |
660 | #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 |
661 | |
662 | /* |
663 | * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) |
664 | */ |
665 | /* On which beat of address/data parity error is observed */ |
666 | #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 |
667 | /* Parity Error on byte */ |
668 | #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 |
669 | /* Parity Error reported in addr or data phase */ |
670 | #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 |
671 | |
672 | /* |
673 | * GPCM Status Register (GPCM_STAT) |
674 | */ |
675 | #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ |
676 | |
677 | /* |
678 | * IFC Controller NAND Machine registers |
679 | */ |
680 | struct fsl_ifc_nand { |
681 | __be32 ncfgr; |
682 | u32 res1[0x4]; |
683 | __be32 nand_fcr0; |
684 | __be32 nand_fcr1; |
685 | u32 res2[0x8]; |
686 | __be32 row0; |
687 | u32 res3; |
688 | __be32 col0; |
689 | u32 res4; |
690 | __be32 row1; |
691 | u32 res5; |
692 | __be32 col1; |
693 | u32 res6; |
694 | __be32 row2; |
695 | u32 res7; |
696 | __be32 col2; |
697 | u32 res8; |
698 | __be32 row3; |
699 | u32 res9; |
700 | __be32 col3; |
701 | u32 res10[0x24]; |
702 | __be32 nand_fbcr; |
703 | u32 res11; |
704 | __be32 nand_fir0; |
705 | __be32 nand_fir1; |
706 | __be32 nand_fir2; |
707 | u32 res12[0x10]; |
708 | __be32 nand_csel; |
709 | u32 res13; |
710 | __be32 nandseq_strt; |
711 | u32 res14; |
712 | __be32 nand_evter_stat; |
713 | u32 res15; |
714 | __be32 pgrdcmpl_evt_stat; |
715 | u32 res16[0x2]; |
716 | __be32 nand_evter_en; |
717 | u32 res17[0x2]; |
718 | __be32 nand_evter_intr_en; |
719 | __be32 nand_vol_addr_stat; |
720 | u32 res18; |
721 | __be32 nand_erattr0; |
722 | __be32 nand_erattr1; |
723 | u32 res19[0x10]; |
724 | __be32 nand_fsr; |
725 | u32 res20; |
726 | __be32 nand_eccstat[8]; |
727 | u32 res21[0x1c]; |
728 | __be32 nanndcr; |
729 | u32 res22[0x2]; |
730 | __be32 nand_autoboot_trgr; |
731 | u32 res23; |
732 | __be32 nand_mdr; |
733 | u32 res24[0x1C]; |
734 | __be32 nand_dll_lowcfg0; |
735 | __be32 nand_dll_lowcfg1; |
736 | u32 res25; |
737 | __be32 nand_dll_lowstat; |
738 | u32 res26[0x3c]; |
739 | }; |
740 | |
741 | /* |
742 | * IFC controller NOR Machine registers |
743 | */ |
744 | struct fsl_ifc_nor { |
745 | __be32 nor_evter_stat; |
746 | u32 res1[0x2]; |
747 | __be32 nor_evter_en; |
748 | u32 res2[0x2]; |
749 | __be32 nor_evter_intr_en; |
750 | u32 res3[0x2]; |
751 | __be32 nor_erattr0; |
752 | __be32 nor_erattr1; |
753 | __be32 nor_erattr2; |
754 | u32 res4[0x4]; |
755 | __be32 norcr; |
756 | u32 res5[0xEF]; |
757 | }; |
758 | |
759 | /* |
760 | * IFC controller GPCM Machine registers |
761 | */ |
762 | struct fsl_ifc_gpcm { |
763 | __be32 gpcm_evter_stat; |
764 | u32 res1[0x2]; |
765 | __be32 gpcm_evter_en; |
766 | u32 res2[0x2]; |
767 | __be32 gpcm_evter_intr_en; |
768 | u32 res3[0x2]; |
769 | __be32 gpcm_erattr0; |
770 | __be32 gpcm_erattr1; |
771 | __be32 gpcm_erattr2; |
772 | __be32 gpcm_stat; |
773 | }; |
774 | |
775 | /* |
776 | * IFC Controller Registers |
777 | */ |
778 | struct fsl_ifc_global { |
779 | __be32 ifc_rev; |
780 | u32 res1[0x2]; |
781 | struct { |
782 | __be32 cspr_ext; |
783 | __be32 cspr; |
784 | u32 res2; |
785 | } cspr_cs[FSL_IFC_BANK_COUNT]; |
786 | u32 res3[0xd]; |
787 | struct { |
788 | __be32 amask; |
789 | u32 res4[0x2]; |
790 | } amask_cs[FSL_IFC_BANK_COUNT]; |
791 | u32 res5[0xc]; |
792 | struct { |
793 | __be32 csor; |
794 | __be32 csor_ext; |
795 | u32 res6; |
796 | } csor_cs[FSL_IFC_BANK_COUNT]; |
797 | u32 res7[0xc]; |
798 | struct { |
799 | __be32 ftim[4]; |
800 | u32 res8[0x8]; |
801 | } ftim_cs[FSL_IFC_BANK_COUNT]; |
802 | u32 res9[0x30]; |
803 | __be32 rb_stat; |
804 | __be32 rb_map; |
805 | __be32 wb_map; |
806 | __be32 ifc_gcr; |
807 | u32 res10[0x2]; |
808 | __be32 cm_evter_stat; |
809 | u32 res11[0x2]; |
810 | __be32 cm_evter_en; |
811 | u32 res12[0x2]; |
812 | __be32 cm_evter_intr_en; |
813 | u32 res13[0x2]; |
814 | __be32 cm_erattr0; |
815 | __be32 cm_erattr1; |
816 | u32 res14[0x2]; |
817 | __be32 ifc_ccr; |
818 | __be32 ifc_csr; |
819 | __be32 ddr_ccr_low; |
820 | }; |
821 | |
822 | |
823 | struct fsl_ifc_runtime { |
824 | struct fsl_ifc_nand ifc_nand; |
825 | struct fsl_ifc_nor ifc_nor; |
826 | struct fsl_ifc_gpcm ifc_gpcm; |
827 | }; |
828 | |
829 | extern unsigned int convert_ifc_address(phys_addr_t addr_base); |
830 | extern int fsl_ifc_find(phys_addr_t addr_base); |
831 | |
832 | /* overview of the fsl ifc controller */ |
833 | |
834 | struct fsl_ifc_ctrl { |
835 | /* device info */ |
836 | struct device *dev; |
837 | struct fsl_ifc_global __iomem *gregs; |
838 | struct fsl_ifc_runtime __iomem *rregs; |
839 | int irq; |
840 | int nand_irq; |
841 | spinlock_t lock; |
842 | void *nand; |
843 | int version; |
844 | int banks; |
845 | |
846 | u32 nand_stat; |
847 | wait_queue_head_t nand_wait; |
848 | bool little_endian; |
849 | }; |
850 | |
851 | extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev; |
852 | |
853 | static inline u32 ifc_in32(void __iomem *addr) |
854 | { |
855 | u32 val; |
856 | |
857 | if (fsl_ifc_ctrl_dev->little_endian) |
858 | val = ioread32(addr); |
859 | else |
860 | val = ioread32be(addr); |
861 | |
862 | return val; |
863 | } |
864 | |
865 | static inline u16 ifc_in16(void __iomem *addr) |
866 | { |
867 | u16 val; |
868 | |
869 | if (fsl_ifc_ctrl_dev->little_endian) |
870 | val = ioread16(addr); |
871 | else |
872 | val = ioread16be(addr); |
873 | |
874 | return val; |
875 | } |
876 | |
877 | static inline u8 ifc_in8(void __iomem *addr) |
878 | { |
879 | return ioread8(addr); |
880 | } |
881 | |
882 | static inline void ifc_out32(u32 val, void __iomem *addr) |
883 | { |
884 | if (fsl_ifc_ctrl_dev->little_endian) |
885 | iowrite32(val, addr); |
886 | else |
887 | iowrite32be(val, addr); |
888 | } |
889 | |
890 | static inline void ifc_out16(u16 val, void __iomem *addr) |
891 | { |
892 | if (fsl_ifc_ctrl_dev->little_endian) |
893 | iowrite16(val, addr); |
894 | else |
895 | iowrite16be(val, addr); |
896 | } |
897 | |
898 | static inline void ifc_out8(u8 val, void __iomem *addr) |
899 | { |
900 | iowrite8(val, addr); |
901 | } |
902 | |
903 | #endif /* __ASM_FSL_IFC_H */ |
904 | |