| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * TI DaVinci DA8xx CHIPCFGx registers for syscon consumers. |
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| 4 | * |
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| 5 | * Copyright (C) 2016 David Lechner <david@lechnology.com> |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef __LINUX_MFD_DA8XX_CFGCHIP_H |
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| 9 | #define __LINUX_MFD_DA8XX_CFGCHIP_H |
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| 10 | |
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| 11 | #include <linux/bitops.h> |
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| 12 | |
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| 13 | /* register offset (32-bit registers) */ |
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| 14 | #define CFGCHIP(n) ((n) * 4) |
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| 15 | |
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| 16 | /* CFGCHIP0 (PLL0/EDMA3_0) register bits */ |
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| 17 | #define CFGCHIP0_PLL_MASTER_LOCK BIT(4) |
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| 18 | #define CFGCHIP0_EDMA30TC1DBS(n) ((n) << 2) |
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| 19 | #define CFGCHIP0_EDMA30TC1DBS_MASK CFGCHIP0_EDMA30TC1DBS(0x3) |
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| 20 | #define CFGCHIP0_EDMA30TC1DBS_16 CFGCHIP0_EDMA30TC1DBS(0x0) |
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| 21 | #define CFGCHIP0_EDMA30TC1DBS_32 CFGCHIP0_EDMA30TC1DBS(0x1) |
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| 22 | #define CFGCHIP0_EDMA30TC1DBS_64 CFGCHIP0_EDMA30TC1DBS(0x2) |
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| 23 | #define CFGCHIP0_EDMA30TC0DBS(n) ((n) << 0) |
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| 24 | #define CFGCHIP0_EDMA30TC0DBS_MASK CFGCHIP0_EDMA30TC0DBS(0x3) |
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| 25 | #define CFGCHIP0_EDMA30TC0DBS_16 CFGCHIP0_EDMA30TC0DBS(0x0) |
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| 26 | #define CFGCHIP0_EDMA30TC0DBS_32 CFGCHIP0_EDMA30TC0DBS(0x1) |
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| 27 | #define CFGCHIP0_EDMA30TC0DBS_64 CFGCHIP0_EDMA30TC0DBS(0x2) |
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| 28 | |
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| 29 | /* CFGCHIP1 (eCAP/HPI/EDMA3_1/eHRPWM TBCLK/McASP0 AMUTEIN) register bits */ |
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| 30 | #define CFGCHIP1_CAP2SRC(n) ((n) << 27) |
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| 31 | #define CFGCHIP1_CAP2SRC_MASK CFGCHIP1_CAP2SRC(0x1f) |
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| 32 | #define CFGCHIP1_CAP2SRC_ECAP_PIN CFGCHIP1_CAP2SRC(0x0) |
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| 33 | #define CFGCHIP1_CAP2SRC_MCASP0_TX CFGCHIP1_CAP2SRC(0x1) |
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| 34 | #define CFGCHIP1_CAP2SRC_MCASP0_RX CFGCHIP1_CAP2SRC(0x2) |
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| 35 | #define CFGCHIP1_CAP2SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP2SRC(0x7) |
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| 36 | #define CFGCHIP1_CAP2SRC_EMAC_C0_RX CFGCHIP1_CAP2SRC(0x8) |
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| 37 | #define CFGCHIP1_CAP2SRC_EMAC_C0_TX CFGCHIP1_CAP2SRC(0x9) |
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| 38 | #define CFGCHIP1_CAP2SRC_EMAC_C0_MISC CFGCHIP1_CAP2SRC(0xa) |
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| 39 | #define CFGCHIP1_CAP2SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xb) |
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| 40 | #define CFGCHIP1_CAP2SRC_EMAC_C1_RX CFGCHIP1_CAP2SRC(0xc) |
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| 41 | #define CFGCHIP1_CAP2SRC_EMAC_C1_TX CFGCHIP1_CAP2SRC(0xd) |
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| 42 | #define CFGCHIP1_CAP2SRC_EMAC_C1_MISC CFGCHIP1_CAP2SRC(0xe) |
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| 43 | #define CFGCHIP1_CAP2SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xf) |
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| 44 | #define CFGCHIP1_CAP2SRC_EMAC_C2_RX CFGCHIP1_CAP2SRC(0x10) |
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| 45 | #define CFGCHIP1_CAP2SRC_EMAC_C2_TX CFGCHIP1_CAP2SRC(0x11) |
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| 46 | #define CFGCHIP1_CAP2SRC_EMAC_C2_MISC CFGCHIP1_CAP2SRC(0x12) |
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| 47 | #define CFGCHIP1_CAP1SRC(n) ((n) << 22) |
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| 48 | #define CFGCHIP1_CAP1SRC_MASK CFGCHIP1_CAP1SRC(0x1f) |
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| 49 | #define CFGCHIP1_CAP1SRC_ECAP_PIN CFGCHIP1_CAP1SRC(0x0) |
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| 50 | #define CFGCHIP1_CAP1SRC_MCASP0_TX CFGCHIP1_CAP1SRC(0x1) |
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| 51 | #define CFGCHIP1_CAP1SRC_MCASP0_RX CFGCHIP1_CAP1SRC(0x2) |
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| 52 | #define CFGCHIP1_CAP1SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP1SRC(0x7) |
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| 53 | #define CFGCHIP1_CAP1SRC_EMAC_C0_RX CFGCHIP1_CAP1SRC(0x8) |
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| 54 | #define CFGCHIP1_CAP1SRC_EMAC_C0_TX CFGCHIP1_CAP1SRC(0x9) |
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| 55 | #define CFGCHIP1_CAP1SRC_EMAC_C0_MISC CFGCHIP1_CAP1SRC(0xa) |
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| 56 | #define CFGCHIP1_CAP1SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xb) |
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| 57 | #define CFGCHIP1_CAP1SRC_EMAC_C1_RX CFGCHIP1_CAP1SRC(0xc) |
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| 58 | #define CFGCHIP1_CAP1SRC_EMAC_C1_TX CFGCHIP1_CAP1SRC(0xd) |
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| 59 | #define CFGCHIP1_CAP1SRC_EMAC_C1_MISC CFGCHIP1_CAP1SRC(0xe) |
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| 60 | #define CFGCHIP1_CAP1SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xf) |
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| 61 | #define CFGCHIP1_CAP1SRC_EMAC_C2_RX CFGCHIP1_CAP1SRC(0x10) |
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| 62 | #define CFGCHIP1_CAP1SRC_EMAC_C2_TX CFGCHIP1_CAP1SRC(0x11) |
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| 63 | #define CFGCHIP1_CAP1SRC_EMAC_C2_MISC CFGCHIP1_CAP1SRC(0x12) |
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| 64 | #define CFGCHIP1_CAP0SRC(n) ((n) << 17) |
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| 65 | #define CFGCHIP1_CAP0SRC_MASK CFGCHIP1_CAP0SRC(0x1f) |
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| 66 | #define CFGCHIP1_CAP0SRC_ECAP_PIN CFGCHIP1_CAP0SRC(0x0) |
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| 67 | #define CFGCHIP1_CAP0SRC_MCASP0_TX CFGCHIP1_CAP0SRC(0x1) |
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| 68 | #define CFGCHIP1_CAP0SRC_MCASP0_RX CFGCHIP1_CAP0SRC(0x2) |
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| 69 | #define CFGCHIP1_CAP0SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP0SRC(0x7) |
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| 70 | #define CFGCHIP1_CAP0SRC_EMAC_C0_RX CFGCHIP1_CAP0SRC(0x8) |
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| 71 | #define CFGCHIP1_CAP0SRC_EMAC_C0_TX CFGCHIP1_CAP0SRC(0x9) |
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| 72 | #define CFGCHIP1_CAP0SRC_EMAC_C0_MISC CFGCHIP1_CAP0SRC(0xa) |
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| 73 | #define CFGCHIP1_CAP0SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xb) |
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| 74 | #define CFGCHIP1_CAP0SRC_EMAC_C1_RX CFGCHIP1_CAP0SRC(0xc) |
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| 75 | #define CFGCHIP1_CAP0SRC_EMAC_C1_TX CFGCHIP1_CAP0SRC(0xd) |
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| 76 | #define CFGCHIP1_CAP0SRC_EMAC_C1_MISC CFGCHIP1_CAP0SRC(0xe) |
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| 77 | #define CFGCHIP1_CAP0SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xf) |
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| 78 | #define CFGCHIP1_CAP0SRC_EMAC_C2_RX CFGCHIP1_CAP0SRC(0x10) |
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| 79 | #define CFGCHIP1_CAP0SRC_EMAC_C2_TX CFGCHIP1_CAP0SRC(0x11) |
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| 80 | #define CFGCHIP1_CAP0SRC_EMAC_C2_MISC CFGCHIP1_CAP0SRC(0x12) |
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| 81 | #define CFGCHIP1_HPIBYTEAD BIT(16) |
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| 82 | #define CFGCHIP1_HPIENA BIT(15) |
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| 83 | #define CFGCHIP0_EDMA31TC0DBS(n) ((n) << 13) |
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| 84 | #define CFGCHIP0_EDMA31TC0DBS_MASK CFGCHIP0_EDMA31TC0DBS(0x3) |
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| 85 | #define CFGCHIP0_EDMA31TC0DBS_16 CFGCHIP0_EDMA31TC0DBS(0x0) |
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| 86 | #define CFGCHIP0_EDMA31TC0DBS_32 CFGCHIP0_EDMA31TC0DBS(0x1) |
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| 87 | #define CFGCHIP0_EDMA31TC0DBS_64 CFGCHIP0_EDMA31TC0DBS(0x2) |
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| 88 | #define CFGCHIP1_TBCLKSYNC BIT(12) |
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| 89 | #define CFGCHIP1_AMUTESEL0(n) ((n) << 0) |
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| 90 | #define CFGCHIP1_AMUTESEL0_MASK CFGCHIP1_AMUTESEL0(0xf) |
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| 91 | #define CFGCHIP1_AMUTESEL0_LOW CFGCHIP1_AMUTESEL0(0x0) |
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| 92 | #define CFGCHIP1_AMUTESEL0_BANK_0 CFGCHIP1_AMUTESEL0(0x1) |
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| 93 | #define CFGCHIP1_AMUTESEL0_BANK_1 CFGCHIP1_AMUTESEL0(0x2) |
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| 94 | #define CFGCHIP1_AMUTESEL0_BANK_2 CFGCHIP1_AMUTESEL0(0x3) |
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| 95 | #define CFGCHIP1_AMUTESEL0_BANK_3 CFGCHIP1_AMUTESEL0(0x4) |
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| 96 | #define CFGCHIP1_AMUTESEL0_BANK_4 CFGCHIP1_AMUTESEL0(0x5) |
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| 97 | #define CFGCHIP1_AMUTESEL0_BANK_5 CFGCHIP1_AMUTESEL0(0x6) |
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| 98 | #define CFGCHIP1_AMUTESEL0_BANK_6 CFGCHIP1_AMUTESEL0(0x7) |
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| 99 | #define CFGCHIP1_AMUTESEL0_BANK_7 CFGCHIP1_AMUTESEL0(0x8) |
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| 100 | |
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| 101 | /* CFGCHIP2 (USB PHY) register bits */ |
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| 102 | #define CFGCHIP2_PHYCLKGD BIT(17) |
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| 103 | #define CFGCHIP2_VBUSSENSE BIT(16) |
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| 104 | #define CFGCHIP2_RESET BIT(15) |
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| 105 | #define CFGCHIP2_OTGMODE(n) ((n) << 13) |
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| 106 | #define CFGCHIP2_OTGMODE_MASK CFGCHIP2_OTGMODE(0x3) |
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| 107 | #define CFGCHIP2_OTGMODE_NO_OVERRIDE CFGCHIP2_OTGMODE(0x0) |
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| 108 | #define CFGCHIP2_OTGMODE_FORCE_HOST CFGCHIP2_OTGMODE(0x1) |
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| 109 | #define CFGCHIP2_OTGMODE_FORCE_DEVICE CFGCHIP2_OTGMODE(0x2) |
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| 110 | #define CFGCHIP2_OTGMODE_FORCE_HOST_VBUS_LOW CFGCHIP2_OTGMODE(0x3) |
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| 111 | #define CFGCHIP2_USB1PHYCLKMUX BIT(12) |
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| 112 | #define CFGCHIP2_USB2PHYCLKMUX BIT(11) |
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| 113 | #define CFGCHIP2_PHYPWRDN BIT(10) |
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| 114 | #define CFGCHIP2_OTGPWRDN BIT(9) |
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| 115 | #define CFGCHIP2_DATPOL BIT(8) |
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| 116 | #define CFGCHIP2_USB1SUSPENDM BIT(7) |
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| 117 | #define CFGCHIP2_PHY_PLLON BIT(6) |
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| 118 | #define CFGCHIP2_SESENDEN BIT(5) |
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| 119 | #define CFGCHIP2_VBDTCTEN BIT(4) |
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| 120 | #define CFGCHIP2_REFFREQ(n) ((n) << 0) |
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| 121 | #define CFGCHIP2_REFFREQ_MASK CFGCHIP2_REFFREQ(0xf) |
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| 122 | #define CFGCHIP2_REFFREQ_12MHZ CFGCHIP2_REFFREQ(0x1) |
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| 123 | #define CFGCHIP2_REFFREQ_24MHZ CFGCHIP2_REFFREQ(0x2) |
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| 124 | #define CFGCHIP2_REFFREQ_48MHZ CFGCHIP2_REFFREQ(0x3) |
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| 125 | #define CFGCHIP2_REFFREQ_19_2MHZ CFGCHIP2_REFFREQ(0x4) |
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| 126 | #define CFGCHIP2_REFFREQ_38_4MHZ CFGCHIP2_REFFREQ(0x5) |
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| 127 | #define CFGCHIP2_REFFREQ_13MHZ CFGCHIP2_REFFREQ(0x6) |
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| 128 | #define CFGCHIP2_REFFREQ_26MHZ CFGCHIP2_REFFREQ(0x7) |
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| 129 | #define CFGCHIP2_REFFREQ_20MHZ CFGCHIP2_REFFREQ(0x8) |
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| 130 | #define CFGCHIP2_REFFREQ_40MHZ CFGCHIP2_REFFREQ(0x9) |
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| 131 | |
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| 132 | /* CFGCHIP3 (EMAC/uPP/PLL1/ASYNC3/PRU/DIV4.5/EMIFA) register bits */ |
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| 133 | #define CFGCHIP3_RMII_SEL BIT(8) |
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| 134 | #define CFGCHIP3_UPP_TX_CLKSRC BIT(6) |
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| 135 | #define CFGCHIP3_PLL1_MASTER_LOCK BIT(5) |
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| 136 | #define CFGCHIP3_ASYNC3_CLKSRC BIT(4) |
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| 137 | #define CFGCHIP3_PRUEVTSEL BIT(3) |
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| 138 | #define CFGCHIP3_DIV45PENA BIT(2) |
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| 139 | #define CFGCHIP3_EMA_CLKSRC BIT(1) |
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| 140 | |
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| 141 | /* CFGCHIP4 (McASP0 AMUNTEIN) register bits */ |
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| 142 | #define CFGCHIP4_AMUTECLR0 BIT(0) |
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| 143 | |
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| 144 | #endif /* __LINUX_MFD_DA8XX_CFGCHIP_H */ |
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| 145 | |
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