| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Definitions for CS4271 ASoC codec driver |
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| 4 | * |
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| 5 | * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru> |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef __CS4271_H |
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| 9 | #define __CS4271_H |
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| 10 | |
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| 11 | struct cs4271_platform_data { |
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| 12 | bool amutec_eq_bmutec; /* flag to enable AMUTEC=BMUTEC */ |
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| 13 | |
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| 14 | /* |
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| 15 | * The CS4271 requires its LRCLK and MCLK to be stable before its RESET |
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| 16 | * line is de-asserted. That also means that clocks cannot be changed |
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| 17 | * without putting the chip back into hardware reset, which also requires |
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| 18 | * a complete re-initialization of all registers. |
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| 19 | * |
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| 20 | * One (undocumented) workaround is to assert and de-assert the PDN bit |
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| 21 | * in the MODE2 register. This workaround can be enabled with the |
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| 22 | * following flag. |
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| 23 | * |
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| 24 | * Note that this is not needed in case the clocks are stable |
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| 25 | * throughout the entire runtime of the codec. |
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| 26 | */ |
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| 27 | bool enable_soft_reset; |
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| 28 | }; |
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| 29 | |
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| 30 | #endif /* __CS4271_H */ |
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| 31 | |
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