1	// SPDX-License-Identifier: GPL-2.0-or-later
2	/* azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168).
3	* Copyright (C) 2002, 2005 - 2011 by Andreas Mohr <andi AT lisas.de>
4	*
5	* Framework borrowed from Bart Hartgers's als4000.c.
6	* Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801),
7	* found in a Fujitsu-Siemens PC ("Cordant", aluminum case).
8	* Other versions are:
9	* PCI168 A(W), sub ID 1800
10	* PCI168 A/AP, sub ID 8000
11	* Please give me feedback in case you try my driver with one of these!!
12	*
13	* Keywords: Windows XP Vista 168nt4-125.zip 168win95-125.zip PCI 168 download
14	* (XP/Vista do not support this card at all but every Linux distribution
15	* has very good support out of the box;
16	* just to make sure that the right people hit this and get to know that,
17	* despite the high level of Internet ignorance - as usual :-P -
18	* about very good support for this card - on Linux!)
19	*
20	* NOTES
21	* Since Aztech does not provide any chipset documentation,
22	* even on repeated request to various addresses,
23	* and the answer that was finally given was negative
24	* (and I was stupid enough to manage to get hold of a PCI168 soundcard
25	* in the first place >:-P}),
26	* I was forced to base this driver on reverse engineering
27	* (3 weeks' worth of evenings filled with driver work).
28	* (and no, I did NOT go the easy way: to pick up a SB PCI128 for 9 Euros)
29	*
30	* It is quite likely that the AZF3328 chip is the PCI cousin of the
31	* AZF3318 ("azt1020 pnp", "MM Pro 16") ISA chip, given very similar specs.
32	*
33	* The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name
34	* for compatibility reasons) from Azfin (joint-venture of Aztech and Fincitec,
35	* Fincitec acquired by National Semiconductor in 2002, together with the
36	* Fincitec-related company ARSmikro) has the following features:
37	*
38	* - compatibility & compliance:
39	* - Microsoft PC 97 ("PC 97 Hardware Design Guide",
40	* http://www.microsoft.com/whdc/archive/pcguides.mspx)
41	* - Microsoft PC 98 Baseline Audio
42	* - MPU401 UART
43	* - Sound Blaster Emulation (DOS Box)
44	* - builtin AC97 conformant codec (SNR over 80dB)
45	* Note that "conformant" != "compliant"!! this chip's mixer register layout
46	* *differs* from the standard AC97 layout:
47	* they chose to not implement the headphone register (which is not a
48	* problem since it's merely optional), yet when doing this, they committed
49	* the grave sin of letting other registers follow immediately instead of
50	* keeping a headphone dummy register, thereby shifting the mixer register
51	* addresses illegally. So far unfortunately it looks like the very flexible
52	* ALSA AC97 support is still not enough to easily compensate for such a
53	* grave layout violation despite all tweaks and quirks mechanisms it offers.
54	* Well, not quite: now ac97 layer is much improved (bus-specific ops!),
55	* thus I was able to implement support - it's actually working quite well.
56	* An interesting item might be Aztech AMR 2800-W, since it's an AC97
57	* modem card which might reveal the Aztech-specific codec ID which
58	* we might want to pretend, too. Dito PCI168's brother, PCI368,
59	* where the advertising datasheet says it's AC97-based and has a
60	* Digital Enhanced Game Port.
61	* - builtin genuine OPL3 - verified to work fine, 20080506
62	* - full duplex 16bit playback/record at independent sampling rate
63	* - MPU401 (+ legacy address support, claimed by one official spec sheet)
64	* FIXME: how to enable legacy addr??
65	* - game port (legacy address support)
66	* - builtin DirectInput support, helps reduce CPU overhead (interrupt-driven
67	* features supported). - See common term "Digital Enhanced Game Port"...
68	* (probably DirectInput 3.0 spec - confirm)
69	* - builtin 3D enhancement (said to be YAMAHA Ymersion)
70	* - built-in General DirectX timer having a 20 bits counter
71	* with 1us resolution (see below!)
72	* - I2S serial output port for external DAC
73	* [FIXME: 3.3V or 5V level? maximum rate is 66.2kHz right?]
74	* - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI
75	* - supports hardware volume control
76	* - single chip low cost solution (128 pin QFP)
77	* - supports programmable Sub-vendor and Sub-system ID [24C02 SEEPROM chip]
78	* required for Microsoft's logo compliance (FIXME: where?)
79	* At least the Trident 4D Wave DX has one bit somewhere
80	* to enable writes to PCI subsystem VID registers, that should be it.
81	* This might easily be in extended PCI reg space, since PCI168 also has
82	* some custom data starting at 0x80. What kind of config settings
83	* are located in our extended PCI space anyway??
84	* - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms
85	* [TDA1517P chip]
86	*
87	* Note that this driver now is actually *better* than the Windows driver,
88	* since it additionally supports the card's 1MHz DirectX timer - just try
89	* the following snd-seq module parameters etc.:
90	* - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0
91	* seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0
92	* seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000
93	* - "timidity -iAv -B2,8 -Os -EFreverb=0"
94	* - "pmidi -p 128:0 jazz.mid"
95	*
96	* OPL3 hardware playback testing, try something like:
97	* cat /proc/asound/hwdep
98	* and
99	* aconnect -o
100	* Then use
101	* sbiload -Dhw:x,y --opl3 /usr/share/sounds/opl3/std.o3 ......./drums.o3
102	* where x,y is the xx-yy number as given in hwdep.
103	* Then try
104	* pmidi -p a:b jazz.mid
105	* where a:b is the client number plus 0 usually, as given by aconnect above.
106	* Oh, and make sure to unmute the FM mixer control (doh!)
107	* NOTE: power use during OPL3 playback is _VERY_ high (70W --> 90W!)
108	* despite no CPU activity, possibly due to hindering ACPI idling somehow.
109	* Shouldn't be a problem of the AZF3328 chip itself, I'd hope.
110	* Higher PCM / FM mixer levels seem to conflict (causes crackling),
111	* at least sometimes. Maybe even use with hardware sequencer timer above :)
112	* adplay/adplug-utils might soon offer hardware-based OPL3 playback, too.
113	*
114	* Certain PCI versions of this card are susceptible to DMA traffic underruns
115	* in some systems (resulting in sound crackling/clicking/popping),
116	* probably because they don't have a DMA FIFO buffer or so.
117	* Overview (PCI ID/PCI subID/PCI rev.):
118	* - no DMA crackling on SiS735: 0x50DC/0x1801/16
119	* - unknown performance: 0x50DC/0x1801/10
120	* (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler)
121	*
122	* Crackling happens with VIA chipsets or, in my case, an SiS735, which is
123	* supposed to be very fast and supposed to get rid of crackling much
124	* better than a VIA, yet ironically I still get crackling, like many other
125	* people with the same chipset.
126	* Possible remedies:
127	* - use speaker (amplifier) output instead of headphone output
128	* (in case crackling is due to overloaded output clipping)
129	* - plug card into a different PCI slot, preferably one that isn't shared
130	* too much (this helps a lot, but not completely!)
131	* - get rid of PCI VGA card, use AGP instead
132	* - upgrade or downgrade BIOS
133	* - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX)
134	* Not too helpful.
135	* - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS
136	*
137	* BUGS
138	* - full-duplex might *still* be problematic, however a recent test was fine
139	* - (non-bug) "Bass/Treble or 3D settings don't work" - they do get evaluated
140	* if you set PCM output switch to "pre 3D" instead of "post 3D".
141	* If this can't be set, then get a mixer application that Isn't Stupid (tm)
142	* (e.g. kmix, gamix) - unfortunately several are!!
143	* - locking is not entirely clean, especially the audio stream activity
144	* ints --> may be racy
145	* - an _unconnected_ secondary joystick at the gameport will be reported
146	* to be "active" (floating values, not precisely -1) due to the way we need
147	* to read the Digital Enhanced Game Port. Not sure whether it is fixable.
148	*
149	* TODO
150	* - use PCI_VDEVICE
151	* - verify driver status on x86_64
152	* - test multi-card driver operation
153	* - (ab)use 1MHz DirectX timer as kernel clocksource
154	* - test MPU401 MIDI playback etc.
155	* - add more power micro-management (disable various units of the card
156	* as long as they're unused, to improve audio quality and save power).
157	* However this requires more I/O ports which I haven't figured out yet
158	* and which thus might not even exist...
159	* The standard suspend/resume functionality could probably make use of
160	* some improvement, too...
161	* - figure out what all unknown port bits are responsible for
162	* - figure out some cleverly evil scheme to possibly make ALSA AC97 code
163	* fully accept our quite incompatible ""AC97"" mixer and thus save some
164	* code (but I'm not too optimistic that doing this is possible at all)
165	* - use MMIO (memory-mapped I/O)? Slightly faster access, e.g. for gameport.
166	*/
167
168	#include <linux/io.h>
169	#include <linux/init.h>
170	#include <linux/bug.h> /* WARN_ONCE */
171	#include <linux/pci.h>
172	#include <linux/delay.h>
173	#include <linux/slab.h>
174	#include <linux/gameport.h>
175	#include <linux/module.h>
176	#include <linux/dma-mapping.h>
177	#include <sound/core.h>
178	#include <sound/control.h>
179	#include <sound/pcm.h>
180	#include <sound/rawmidi.h>
181	#include <sound/mpu401.h>
182	#include <sound/opl3.h>
183	#include <sound/initval.h>
184	/*
185	* Config switch, to use ALSA's AC97 layer instead of old custom mixer crap.
186	* If the AC97 compatibility parts we needed to implement locally turn out
187	* to work nicely, then remove the old implementation eventually.
188	*/
189	#define AZF_USE_AC97_LAYER 1
190
191	#ifdef AZF_USE_AC97_LAYER
192	#include <sound/ac97_codec.h>
193	#endif
194	#include "azt3328.h"
195
196	MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>");
197	MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)");
198	MODULE_LICENSE("GPL");
199
200	#if IS_REACHABLE(CONFIG_GAMEPORT)
201	#define SUPPORT_GAMEPORT 1
202	#endif
203
204	/* === Debug settings ===
205	Further diagnostic functionality than the settings below
206	does not need to be provided, since one can easily write a POSIX shell script
207	to dump the card's I/O ports (those listed in lspci -v -v):
208	dump()
209	{
210	local descr=$1; local addr=$2; local count=$3
211
212	echo "${descr}: ${count} @ ${addr}:"
213	dd if=/dev/port skip=`printf %d ${addr}` count=${count} bs=1 \
214	2>/dev/null| hexdump -C
215	}
216	and then use something like
217	"dump joy200 0x200 8", "dump mpu388 0x388 4", "dump joy 0xb400 8",
218	"dump codec00 0xa800 32", "dump mixer 0xb800 64", "dump synth 0xbc00 8",
219	possibly within a "while true; do ... sleep 1; done" loop.
220	Tweaking ports could be done using
221	VALSTRING="`printf "%02x" $value`"
222	printf "\x""$VALSTRING"|dd of=/dev/port seek=`printf %d ${addr}` bs=1 \
223	2>/dev/null
224	*/
225
226	static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
227	module_param_array(index, int, NULL, 0444);
228	MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard.");
229
230	static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
231	module_param_array(id, charp, NULL, 0444);
232	MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard.");
233
234	static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
235	module_param_array(enable, bool, NULL, 0444);
236	MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard.");
237
238	static int seqtimer_scaling = 128;
239	module_param(seqtimer_scaling, int, 0444);
240	MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128.");
241
242	enum snd_azf3328_codec_type {
243	/* warning: fixed indices (also used for bitmask checks!) */
244	AZF_CODEC_PLAYBACK = 0,
245	AZF_CODEC_CAPTURE = 1,
246	AZF_CODEC_I2S_OUT = 2,
247	};
248
249	struct snd_azf3328_codec_data {
250	unsigned long io_base; /* keep first! (avoid offset calc) */
251	unsigned int dma_base; /* helper to avoid an indirection in hotpath */
252	spinlock_t *lock; /* TODO: convert to our own per-codec lock member */
253	struct snd_pcm_substream *substream;
254	bool running;
255	enum snd_azf3328_codec_type type;
256	const char *name;
257	};
258
259	struct snd_azf3328 {
260	/* often-used fields towards beginning, then grouped */
261
262	unsigned long ctrl_io; /* usually 0xb000, size 128 */
263	unsigned long game_io; /* usually 0xb400, size 8 */
264	unsigned long mpu_io; /* usually 0xb800, size 4 */
265	unsigned long opl3_io; /* usually 0xbc00, size 8 */
266	unsigned long mixer_io; /* usually 0xc000, size 64 */
267
268	spinlock_t reg_lock;
269
270	struct snd_timer *timer;
271
272	struct snd_pcm *pcm[3];
273
274	/* playback, recording and I2S out codecs */
275	struct snd_azf3328_codec_data codecs[3];
276
277	#ifdef AZF_USE_AC97_LAYER
278	struct snd_ac97 *ac97;
279	#endif
280
281	struct snd_card *card;
282	struct snd_rawmidi *rmidi;
283
284	#ifdef SUPPORT_GAMEPORT
285	struct gameport *gameport;
286	u16 axes[4];
287	#endif
288
289	struct pci_dev *pci;
290	int irq;
291
292	/* register 0x6a is write-only, thus need to remember setting.
293	* If we need to add more registers here, then we might try to fold this
294	* into some transparent combined shadow register handling with
295	* CONFIG_PM register storage below, but that's slightly difficult. */
296	u16 shadow_reg_ctrl_6AH;
297
298	/* register value containers for power management
299	* Note: not always full I/O range preserved (similar to Win driver!) */
300	u32 saved_regs_ctrl[AZF_ALIGN(AZF_IO_SIZE_CTRL_PM) / 4];
301	u32 saved_regs_game[AZF_ALIGN(AZF_IO_SIZE_GAME_PM) / 4];
302	u32 saved_regs_mpu[AZF_ALIGN(AZF_IO_SIZE_MPU_PM) / 4];
303	u32 saved_regs_opl3[AZF_ALIGN(AZF_IO_SIZE_OPL3_PM) / 4];
304	u32 saved_regs_mixer[AZF_ALIGN(AZF_IO_SIZE_MIXER_PM) / 4];
305	};
306
307	static const struct pci_device_id snd_azf3328_ids[] = {
308	{ 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */
309	{ 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */
310	{ 0, }
311	};
312
313	MODULE_DEVICE_TABLE(pci, snd_azf3328_ids);
314
315
316	static int
317	snd_azf3328_io_reg_setb(unsigned reg, u8 mask, bool do_set)
318	{
319	/* Well, strictly spoken, the inb/outb sequence isn't atomic
320	and would need locking. However we currently don't care
321	since it potentially complicates matters. */
322	u8 prev = inb(port: reg), new;
323
324	new = (do_set) ? (prev|mask) : (prev & ~mask);
325	/* we need to always write the new value no matter whether it differs
326	* or not, since some register bits don't indicate their setting */
327	outb(value: new, port: reg);
328	if (new != prev)
329	return 1;
330
331	return 0;
332	}
333
334	static inline void
335	snd_azf3328_codec_outb(const struct snd_azf3328_codec_data *codec,
336	unsigned reg,
337	u8 value
338	)
339	{
340	outb(value, port: codec->io_base + reg);
341	}
342
343	static inline u8
344	snd_azf3328_codec_inb(const struct snd_azf3328_codec_data *codec, unsigned reg)
345	{
346	return inb(port: codec->io_base + reg);
347	}
348
349	static inline void
350	snd_azf3328_codec_outw(const struct snd_azf3328_codec_data *codec,
351	unsigned reg,
352	u16 value
353	)
354	{
355	outw(value, port: codec->io_base + reg);
356	}
357
358	static inline u16
359	snd_azf3328_codec_inw(const struct snd_azf3328_codec_data *codec, unsigned reg)
360	{
361	return inw(port: codec->io_base + reg);
362	}
363
364	static inline void
365	snd_azf3328_codec_outl_multi(const struct snd_azf3328_codec_data *codec,
366	unsigned reg, const void *buffer, int count
367	)
368	{
369	unsigned long addr = codec->io_base + reg;
370	if (count) {
371	const u32 *buf = buffer;
372	do {
373	outl(value: *buf++, port: addr);
374	addr += 4;
375	} while (--count);
376	}
377	}
378
379	static inline u32
380	snd_azf3328_codec_inl(const struct snd_azf3328_codec_data *codec, unsigned reg)
381	{
382	return inl(port: codec->io_base + reg);
383	}
384
385	static inline void
386	snd_azf3328_ctrl_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
387	{
388	outb(value, port: chip->ctrl_io + reg);
389	}
390
391	static inline u8
392	snd_azf3328_ctrl_inb(const struct snd_azf3328 *chip, unsigned reg)
393	{
394	return inb(port: chip->ctrl_io + reg);
395	}
396
397	static inline u16
398	snd_azf3328_ctrl_inw(const struct snd_azf3328 *chip, unsigned reg)
399	{
400	return inw(port: chip->ctrl_io + reg);
401	}
402
403	static inline void
404	snd_azf3328_ctrl_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
405	{
406	outw(value, port: chip->ctrl_io + reg);
407	}
408
409	static inline void
410	snd_azf3328_ctrl_outl(const struct snd_azf3328 *chip, unsigned reg, u32 value)
411	{
412	outl(value, port: chip->ctrl_io + reg);
413	}
414
415	static inline void
416	snd_azf3328_game_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
417	{
418	outb(value, port: chip->game_io + reg);
419	}
420
421	static inline void
422	snd_azf3328_game_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
423	{
424	outw(value, port: chip->game_io + reg);
425	}
426
427	static inline u8
428	snd_azf3328_game_inb(const struct snd_azf3328 *chip, unsigned reg)
429	{
430	return inb(port: chip->game_io + reg);
431	}
432
433	static inline u16
434	snd_azf3328_game_inw(const struct snd_azf3328 *chip, unsigned reg)
435	{
436	return inw(port: chip->game_io + reg);
437	}
438
439	static inline void
440	snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
441	{
442	outw(value, port: chip->mixer_io + reg);
443	}
444
445	static inline u16
446	snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, unsigned reg)
447	{
448	return inw(port: chip->mixer_io + reg);
449	}
450
451	#define AZF_MUTE_BIT 0x80
452
453	static bool
454	snd_azf3328_mixer_mute_control(const struct snd_azf3328 *chip,
455	unsigned reg, bool do_mute
456	)
457	{
458	unsigned long portbase = chip->mixer_io + reg + 1;
459	bool updated;
460
461	/* the mute bit is on the *second* (i.e. right) register of a
462	* left/right channel setting */
463	updated = snd_azf3328_io_reg_setb(reg: portbase, AZF_MUTE_BIT, do_set: do_mute);
464
465	/* indicate whether it was muted before */
466	return (do_mute) ? !updated : updated;
467	}
468
469	static inline bool
470	snd_azf3328_mixer_mute_control_master(const struct snd_azf3328 *chip,
471	bool do_mute
472	)
473	{
474	return snd_azf3328_mixer_mute_control(
475	chip,
476	IDX_MIXER_PLAY_MASTER,
477	do_mute
478	);
479	}
480
481	static inline bool
482	snd_azf3328_mixer_mute_control_pcm(const struct snd_azf3328 *chip,
483	bool do_mute
484	)
485	{
486	return snd_azf3328_mixer_mute_control(
487	chip,
488	IDX_MIXER_WAVEOUT,
489	do_mute
490	);
491	}
492
493	static inline void
494	snd_azf3328_mixer_reset(const struct snd_azf3328 *chip)
495	{
496	/* reset (close) mixer:
497	* first mute master volume, then reset
498	*/
499	snd_azf3328_mixer_mute_control_master(chip, do_mute: 1);
500	snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, value: 0x0000);
501	}
502
503	#ifdef AZF_USE_AC97_LAYER
504
505	static inline void
506	snd_azf3328_mixer_ac97_map_unsupported(const struct snd_azf3328 *chip,
507	unsigned short reg, const char *mode)
508	{
509	/* need to add some more or less clever emulation? */
510	dev_warn(chip->card->dev,
511	"missing %s emulation for AC97 register 0x%02x!\n",
512	mode, reg);
513	}
514
515	/*
516	* Need to have _special_ AC97 mixer hardware register index mapper,
517	* to compensate for the issue of a rather AC97-incompatible hardware layout.
518	*/
519	#define AZF_REG_MASK 0x3f
520	#define AZF_AC97_REG_UNSUPPORTED 0x8000
521	#define AZF_AC97_REG_REAL_IO_READ 0x4000
522	#define AZF_AC97_REG_REAL_IO_WRITE 0x2000
523	#define AZF_AC97_REG_REAL_IO_RW \
524	(AZF_AC97_REG_REAL_IO_READ | AZF_AC97_REG_REAL_IO_WRITE)
525	#define AZF_AC97_REG_EMU_IO_READ 0x0400
526	#define AZF_AC97_REG_EMU_IO_WRITE 0x0200
527	#define AZF_AC97_REG_EMU_IO_RW \
528	(AZF_AC97_REG_EMU_IO_READ | AZF_AC97_REG_EMU_IO_WRITE)
529	static unsigned short
530	snd_azf3328_mixer_ac97_map_reg_idx(unsigned short reg)
531	{
532	static const struct {
533	unsigned short azf_reg;
534	} azf_reg_mapper[] = {
535	/* Especially when taking into consideration
536	* mono/stereo-based sequence of azf vs. AC97 control series,
537	* it's quite obvious that azf simply got rid
538	* of the AC97_HEADPHONE control at its intended offset,
539	* thus shifted _all_ controls by one,
540	* and _then_ simply added it as an FMSYNTH control at the end,
541	* to make up for the offset.
542	* This means we'll have to translate indices here as
543	* needed and then do some tiny AC97 patch action
544	* (snd_ac97_rename_vol_ctl() etc.) - that's it.
545	*/
546	{ /* AC97_RESET */ IDX_MIXER_RESET
547	| AZF_AC97_REG_REAL_IO_WRITE
548	| AZF_AC97_REG_EMU_IO_READ },
549	{ /* AC97_MASTER */ IDX_MIXER_PLAY_MASTER },
550	/* note large shift: AC97_HEADPHONE to IDX_MIXER_FMSYNTH! */
551	{ /* AC97_HEADPHONE */ IDX_MIXER_FMSYNTH },
552	{ /* AC97_MASTER_MONO */ IDX_MIXER_MODEMOUT },
553	{ /* AC97_MASTER_TONE */ IDX_MIXER_BASSTREBLE },
554	{ /* AC97_PC_BEEP */ IDX_MIXER_PCBEEP },
555	{ /* AC97_PHONE */ IDX_MIXER_MODEMIN },
556	{ /* AC97_MIC */ IDX_MIXER_MIC },
557	{ /* AC97_LINE */ IDX_MIXER_LINEIN },
558	{ /* AC97_CD */ IDX_MIXER_CDAUDIO },
559	{ /* AC97_VIDEO */ IDX_MIXER_VIDEO },
560	{ /* AC97_AUX */ IDX_MIXER_AUX },
561	{ /* AC97_PCM */ IDX_MIXER_WAVEOUT },
562	{ /* AC97_REC_SEL */ IDX_MIXER_REC_SELECT },
563	{ /* AC97_REC_GAIN */ IDX_MIXER_REC_VOLUME },
564	{ /* AC97_REC_GAIN_MIC */ AZF_AC97_REG_EMU_IO_RW },
565	{ /* AC97_GENERAL_PURPOSE */ IDX_MIXER_ADVCTL2 },
566	{ /* AC97_3D_CONTROL */ IDX_MIXER_ADVCTL1 },
567	};
568
569	unsigned short reg_azf = AZF_AC97_REG_UNSUPPORTED;
570
571	/* azf3328 supports the low-numbered and low-spec:ed range
572	of AC97 regs only */
573	if (reg <= AC97_3D_CONTROL) {
574	unsigned short reg_idx = reg / 2;
575	reg_azf = azf_reg_mapper[reg_idx].azf_reg;
576	/* a translation-only entry means it's real read/write: */
577	if (!(reg_azf & ~AZF_REG_MASK))
578	reg_azf |= AZF_AC97_REG_REAL_IO_RW;
579	} else {
580	switch (reg) {
581	case AC97_POWERDOWN:
582	reg_azf = AZF_AC97_REG_EMU_IO_RW;
583	break;
584	case AC97_EXTENDED_ID:
585	reg_azf = AZF_AC97_REG_EMU_IO_READ;
586	break;
587	case AC97_EXTENDED_STATUS:
588	/* I don't know what the h*ll AC97 layer
589	* would consult this _extended_ register for
590	* given a base-AC97-advertised card,
591	* but let's just emulate it anyway :-P
592	*/
593	reg_azf = AZF_AC97_REG_EMU_IO_RW;
594	break;
595	case AC97_VENDOR_ID1:
596	case AC97_VENDOR_ID2:
597	reg_azf = AZF_AC97_REG_EMU_IO_READ;
598	break;
599	}
600	}
601	return reg_azf;
602	}
603
604	static const unsigned short
605	azf_emulated_ac97_caps =
606	AC97_BC_DEDICATED_MIC |
607	AC97_BC_BASS_TREBLE |
608	/* Headphone is an FM Synth control here */
609	AC97_BC_HEADPHONE |
610	/* no AC97_BC_LOUDNESS! */
611	/* mask 0x7c00 is
612	vendor-specific 3D enhancement
613	vendor indicator.
614	Since there actually _is_ an
615	entry for Aztech Labs
616	(13), make damn sure
617	to indicate it. */
618	(13 << 10);
619
620	static const unsigned short
621	azf_emulated_ac97_powerdown =
622	/* pretend everything to be active */
623	AC97_PD_ADC_STATUS |
624	AC97_PD_DAC_STATUS |
625	AC97_PD_MIXER_STATUS |
626	AC97_PD_VREF_STATUS;
627
628	/*
629	* Emulated, _inofficial_ vendor ID
630	* (there might be some devices such as the MR 2800-W
631	* which could reveal the real Aztech AC97 ID).
632	* We choose to use "AZT" prefix, and then use 1 to indicate PCI168
633	* (better don't use 0x68 since there's a PCI368 as well).
634	*/
635	static const unsigned int
636	azf_emulated_ac97_vendor_id = 0x415a5401;
637
638	static unsigned short
639	snd_azf3328_mixer_ac97_read(struct snd_ac97 *ac97, unsigned short reg_ac97)
640	{
641	const struct snd_azf3328 *chip = ac97->private_data;
642	unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg: reg_ac97);
643	unsigned short reg_val = 0;
644	bool unsupported = false;
645
646	dev_dbg(chip->card->dev, "snd_azf3328_mixer_ac97_read reg_ac97 %u\n",
647	reg_ac97);
648	if (reg_azf & AZF_AC97_REG_UNSUPPORTED)
649	unsupported = true;
650	else {
651	if (reg_azf & AZF_AC97_REG_REAL_IO_READ)
652	reg_val = snd_azf3328_mixer_inw(chip,
653	reg: reg_azf & AZF_REG_MASK);
654	else {
655	/*
656	* Proceed with dummy I/O read,
657	* to ensure compatible timing where this may matter.
658	* (ALSA AC97 layer usually doesn't call I/O functions
659	* due to intelligent I/O caching anyway)
660	* Choose a mixer register that's thoroughly unrelated
661	* to common audio (try to minimize distortion).
662	*/
663	snd_azf3328_mixer_inw(chip, IDX_MIXER_SOMETHING30H);
664	}
665
666	if (reg_azf & AZF_AC97_REG_EMU_IO_READ) {
667	switch (reg_ac97) {
668	case AC97_RESET:
669	reg_val |= azf_emulated_ac97_caps;
670	break;
671	case AC97_POWERDOWN:
672	reg_val |= azf_emulated_ac97_powerdown;
673	break;
674	case AC97_EXTENDED_ID:
675	case AC97_EXTENDED_STATUS:
676	/* AFAICS we simply can't support anything: */
677	reg_val |= 0;
678	break;
679	case AC97_VENDOR_ID1:
680	reg_val = azf_emulated_ac97_vendor_id >> 16;
681	break;
682	case AC97_VENDOR_ID2:
683	reg_val = azf_emulated_ac97_vendor_id & 0xffff;
684	break;
685	default:
686	unsupported = true;
687	break;
688	}
689	}
690	}
691	if (unsupported)
692	snd_azf3328_mixer_ac97_map_unsupported(chip, reg: reg_ac97, mode: "read");
693
694	return reg_val;
695	}
696
697	static void
698	snd_azf3328_mixer_ac97_write(struct snd_ac97 *ac97,
699	unsigned short reg_ac97, unsigned short val)
700	{
701	const struct snd_azf3328 *chip = ac97->private_data;
702	unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg: reg_ac97);
703	bool unsupported = false;
704
705	dev_dbg(chip->card->dev,
706	"snd_azf3328_mixer_ac97_write reg_ac97 %u val %u\n",
707	reg_ac97, val);
708	if (reg_azf & AZF_AC97_REG_UNSUPPORTED)
709	unsupported = true;
710	else {
711	if (reg_azf & AZF_AC97_REG_REAL_IO_WRITE)
712	snd_azf3328_mixer_outw(
713	chip,
714	reg: reg_azf & AZF_REG_MASK,
715	value: val
716	);
717	else
718	if (reg_azf & AZF_AC97_REG_EMU_IO_WRITE) {
719	switch (reg_ac97) {
720	case AC97_REC_GAIN_MIC:
721	case AC97_POWERDOWN:
722	case AC97_EXTENDED_STATUS:
723	/*
724	* Silently swallow these writes.
725	* Since for most registers our card doesn't
726	* actually support a comparable feature,
727	* this is exactly what we should do here.
728	* The AC97 layer's I/O caching probably
729	* automatically takes care of all the rest...
730	* (remembers written values etc.)
731	*/
732	break;
733	default:
734	unsupported = true;
735	break;
736	}
737	}
738	}
739	if (unsupported)
740	snd_azf3328_mixer_ac97_map_unsupported(chip, reg: reg_ac97, mode: "write");
741	}
742
743	static int
744	snd_azf3328_mixer_new(struct snd_azf3328 *chip)
745	{
746	struct snd_ac97_bus *bus;
747	struct snd_ac97_template ac97;
748	static const struct snd_ac97_bus_ops ops = {
749	.write = snd_azf3328_mixer_ac97_write,
750	.read = snd_azf3328_mixer_ac97_read,
751	};
752	int rc;
753
754	memset(&ac97, 0, sizeof(ac97));
755	ac97.scaps = AC97_SCAP_SKIP_MODEM
756	| AC97_SCAP_AUDIO /* we support audio! */
757	| AC97_SCAP_NO_SPDIF;
758	ac97.private_data = chip;
759	ac97.pci = chip->pci;
760
761	/*
762	* ALSA's AC97 layer has terrible init crackling issues,
763	* unfortunately, and since it makes use of AC97_RESET,
764	* there's no use trying to mute Master Playback proactively.
765	*/
766
767	rc = snd_ac97_bus(card: chip->card, num: 0, ops: &ops, NULL, rbus: &bus);
768	if (!rc)
769	rc = snd_ac97_mixer(bus, template: &ac97, rac97: &chip->ac97);
770	/*
771	* Make sure to complain loudly in case of AC97 init failure,
772	* since failure may happen quite often,
773	* due to this card being a very quirky AC97 "lookalike".
774	*/
775	if (rc)
776	dev_err(chip->card->dev, "AC97 init failed, err %d!\n", rc);
777
778	/* If we return an error here, then snd_card_free() should
779	* free up any ac97 codecs that got created, as well as the bus.
780	*/
781	return rc;
782	}
783	#else /* AZF_USE_AC97_LAYER */
784	static void
785	snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip,
786	unsigned reg,
787	unsigned char dst_vol_left,
788	unsigned char dst_vol_right,
789	int chan_sel, int delay
790	)
791	{
792	unsigned long portbase = chip->mixer_io + reg;
793	unsigned char curr_vol_left = 0, curr_vol_right = 0;
794	int left_change = 0, right_change = 0;
795
796	if (chan_sel & SET_CHAN_LEFT) {
797	curr_vol_left = inb(portbase + 1);
798
799	/* take care of muting flag contained in left channel */
800	if (curr_vol_left & AZF_MUTE_BIT)
801	dst_vol_left |= AZF_MUTE_BIT;
802	else
803	dst_vol_left &= ~AZF_MUTE_BIT;
804
805	left_change = (curr_vol_left > dst_vol_left) ? -1 : 1;
806	}
807
808	if (chan_sel & SET_CHAN_RIGHT) {
809	curr_vol_right = inb(portbase + 0);
810
811	right_change = (curr_vol_right > dst_vol_right) ? -1 : 1;
812	}
813
814	do {
815	if (left_change) {
816	if (curr_vol_left != dst_vol_left) {
817	curr_vol_left += left_change;
818	outb(curr_vol_left, portbase + 1);
819	} else
820	left_change = 0;
821	}
822	if (right_change) {
823	if (curr_vol_right != dst_vol_right) {
824	curr_vol_right += right_change;
825
826	/* during volume change, the right channel is crackling
827	* somewhat more than the left channel, unfortunately.
828	* This seems to be a hardware issue. */
829	outb(curr_vol_right, portbase + 0);
830	} else
831	right_change = 0;
832	}
833	if (delay)
834	mdelay(delay);
835	} while ((left_change) || (right_change));
836	}
837
838	/*
839	* general mixer element
840	*/
841	struct azf3328_mixer_reg {
842	unsigned reg;
843	unsigned int lchan_shift, rchan_shift;
844	unsigned int mask;
845	unsigned int invert: 1;
846	unsigned int stereo: 1;
847	unsigned int enum_c: 4;
848	};
849
850	#define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \
851	((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \
852	(mask << 16) | \
853	(invert << 24) | \
854	(stereo << 25) | \
855	(enum_c << 26))
856
857	static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val)
858	{
859	r->reg = val & 0xff;
860	r->lchan_shift = (val >> 8) & 0x0f;
861	r->rchan_shift = (val >> 12) & 0x0f;
862	r->mask = (val >> 16) & 0xff;
863	r->invert = (val >> 24) & 1;
864	r->stereo = (val >> 25) & 1;
865	r->enum_c = (val >> 26) & 0x0f;
866	}
867
868	/*
869	* mixer switches/volumes
870	*/
871
872	#define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \
873	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
874	.info = snd_azf3328_info_mixer, \
875	.get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
876	.private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \
877	}
878
879	#define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \
880	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
881	.info = snd_azf3328_info_mixer, \
882	.get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
883	.private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \
884	}
885
886	#define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \
887	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
888	.info = snd_azf3328_info_mixer, \
889	.get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
890	.private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \
891	}
892
893	#define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \
894	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
895	.info = snd_azf3328_info_mixer, \
896	.get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
897	.private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \
898	}
899
900	#define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \
901	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
902	.info = snd_azf3328_info_mixer_enum, \
903	.get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \
904	.private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \
905	}
906
907	static int
908	snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol,
909	struct snd_ctl_elem_info *uinfo)
910	{
911	struct azf3328_mixer_reg reg;
912
913	snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
914	uinfo->type = reg.mask == 1 ?
915	SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
916	uinfo->count = reg.stereo + 1;
917	uinfo->value.integer.min = 0;
918	uinfo->value.integer.max = reg.mask;
919	return 0;
920	}
921
922	static int
923	snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol,
924	struct snd_ctl_elem_value *ucontrol)
925	{
926	struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
927	struct azf3328_mixer_reg reg;
928	u16 oreg, val;
929
930	snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
931
932	oreg = snd_azf3328_mixer_inw(chip, reg.reg);
933	val = (oreg >> reg.lchan_shift) & reg.mask;
934	if (reg.invert)
935	val = reg.mask - val;
936	ucontrol->value.integer.value[0] = val;
937	if (reg.stereo) {
938	val = (oreg >> reg.rchan_shift) & reg.mask;
939	if (reg.invert)
940	val = reg.mask - val;
941	ucontrol->value.integer.value[1] = val;
942	}
943	dev_dbg(chip->card->dev,
944	"get: %02x is %04x -> vol %02lx|%02lx (shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n",
945	reg.reg, oreg,
946	ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
947	reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo);
948	return 0;
949	}
950
951	static int
952	snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol,
953	struct snd_ctl_elem_value *ucontrol)
954	{
955	struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
956	struct azf3328_mixer_reg reg;
957	u16 oreg, nreg, val;
958
959	snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
960	oreg = snd_azf3328_mixer_inw(chip, reg.reg);
961	val = ucontrol->value.integer.value[0] & reg.mask;
962	if (reg.invert)
963	val = reg.mask - val;
964	nreg = oreg & ~(reg.mask << reg.lchan_shift);
965	nreg |= (val << reg.lchan_shift);
966	if (reg.stereo) {
967	val = ucontrol->value.integer.value[1] & reg.mask;
968	if (reg.invert)
969	val = reg.mask - val;
970	nreg &= ~(reg.mask << reg.rchan_shift);
971	nreg |= (val << reg.rchan_shift);
972	}
973	if (reg.mask >= 0x07) /* it's a volume control, so better take care */
974	snd_azf3328_mixer_write_volume_gradually(
975	chip, reg.reg, nreg >> 8, nreg & 0xff,
976	/* just set both channels, doesn't matter */
977	SET_CHAN_LEFT|SET_CHAN_RIGHT,
978	0);
979	else
980	snd_azf3328_mixer_outw(chip, reg.reg, nreg);
981
982	dev_dbg(chip->card->dev,
983	"put: %02x to %02lx|%02lx, oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n",
984	reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
985	oreg, reg.lchan_shift, reg.rchan_shift,
986	nreg, snd_azf3328_mixer_inw(chip, reg.reg));
987	return (nreg != oreg);
988	}
989
990	static int
991	snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol,
992	struct snd_ctl_elem_info *uinfo)
993	{
994	static const char * const texts1[] = {
995	"Mic1", "Mic2"
996	};
997	static const char * const texts2[] = {
998	"Mix", "Mic"
999	};
1000	static const char * const texts3[] = {
1001	"Mic", "CD", "Video", "Aux",
1002	"Line", "Mix", "Mix Mono", "Phone"
1003	};
1004	static const char * const texts4[] = {
1005	"pre 3D", "post 3D"
1006	};
1007	struct azf3328_mixer_reg reg;
1008	const char * const *p = NULL;
1009
1010	snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
1011	if (reg.reg == IDX_MIXER_ADVCTL2) {
1012	switch(reg.lchan_shift) {
1013	case 8: /* modem out sel */
1014	p = texts1;
1015	break;
1016	case 9: /* mono sel source */
1017	p = texts2;
1018	break;
1019	case 15: /* PCM Out Path */
1020	p = texts4;
1021	break;
1022	}
1023	} else if (reg.reg == IDX_MIXER_REC_SELECT)
1024	p = texts3;
1025
1026	return snd_ctl_enum_info(uinfo,
1027	(reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1,
1028	reg.enum_c, p);
1029	}
1030
1031	static int
1032	snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol,
1033	struct snd_ctl_elem_value *ucontrol)
1034	{
1035	struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
1036	struct azf3328_mixer_reg reg;
1037	unsigned short val;
1038
1039	snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
1040	val = snd_azf3328_mixer_inw(chip, reg.reg);
1041	if (reg.reg == IDX_MIXER_REC_SELECT) {
1042	ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1);
1043	ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1);
1044	} else
1045	ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1);
1046
1047	dev_dbg(chip->card->dev,
1048	"get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n",
1049	reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1],
1050	reg.lchan_shift, reg.enum_c);
1051	return 0;
1052	}
1053
1054	static int
1055	snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol,
1056	struct snd_ctl_elem_value *ucontrol)
1057	{
1058	struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
1059	struct azf3328_mixer_reg reg;
1060	u16 oreg, nreg, val;
1061
1062	snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
1063	oreg = snd_azf3328_mixer_inw(chip, reg.reg);
1064	val = oreg;
1065	if (reg.reg == IDX_MIXER_REC_SELECT) {
1066	if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U ||
1067	ucontrol->value.enumerated.item[1] > reg.enum_c - 1U)
1068	return -EINVAL;
1069	val = (ucontrol->value.enumerated.item[0] << 8) |
1070	(ucontrol->value.enumerated.item[1] << 0);
1071	} else {
1072	if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U)
1073	return -EINVAL;
1074	val &= ~((reg.enum_c - 1) << reg.lchan_shift);
1075	val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift);
1076	}
1077	snd_azf3328_mixer_outw(chip, reg.reg, val);
1078	nreg = val;
1079
1080	dev_dbg(chip->card->dev,
1081	"put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg);
1082	return (nreg != oreg);
1083	}
1084
1085	static const struct snd_kcontrol_new snd_azf3328_mixer_controls[] = {
1086	AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1),
1087	AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1),
1088	AZF3328_MIXER_SWITCH("PCM Playback Switch", IDX_MIXER_WAVEOUT, 15, 1),
1089	AZF3328_MIXER_VOL_STEREO("PCM Playback Volume",
1090	IDX_MIXER_WAVEOUT, 0x1f, 1),
1091	AZF3328_MIXER_SWITCH("PCM 3D Bypass Playback Switch",
1092	IDX_MIXER_ADVCTL2, 7, 1),
1093	AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1),
1094	AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1),
1095	AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1),
1096	AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1),
1097	AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1),
1098	AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0),
1099	AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0),
1100	AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1),
1101	AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1),
1102	AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0),
1103	AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1),
1104	AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1),
1105	AZF3328_MIXER_SWITCH("Beep Playback Switch", IDX_MIXER_PCBEEP, 15, 1),
1106	AZF3328_MIXER_VOL_SPECIAL("Beep Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1),
1107	AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1),
1108	AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1),
1109	AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1),
1110	AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1),
1111	AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1),
1112	AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1),
1113	AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1),
1114	AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1),
1115	AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8),
1116	AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9),
1117	AZF3328_MIXER_ENUM("PCM Output Route", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */
1118	AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0),
1119	AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0),
1120	AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0),
1121	AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */
1122	AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */
1123	#if MIXER_TESTING
1124	AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0),
1125	AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0),
1126	AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0),
1127	AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0),
1128	AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0),
1129	AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0),
1130	AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0),
1131	AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0),
1132	AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0),
1133	AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0),
1134	AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0),
1135	AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0),
1136	AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0),
1137	AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0),
1138	AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0),
1139	AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0),
1140	#endif
1141	};
1142
1143	static const u16 snd_azf3328_init_values[][2] = {
1144	{ IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f },
1145	{ IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f },
1146	{ IDX_MIXER_BASSTREBLE, 0x0000 },
1147	{ IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f },
1148	{ IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f },
1149	{ IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f },
1150	{ IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f },
1151	{ IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f },
1152	{ IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f },
1153	{ IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f },
1154	{ IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f },
1155	{ IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f },
1156	{ IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 },
1157	};
1158
1159	static int
1160	snd_azf3328_mixer_new(struct snd_azf3328 *chip)
1161	{
1162	struct snd_card *card;
1163	const struct snd_kcontrol_new *sw;
1164	unsigned int idx;
1165	int err;
1166
1167	if (snd_BUG_ON(!chip || !chip->card))
1168	return -EINVAL;
1169
1170	card = chip->card;
1171
1172	/* mixer reset */
1173	snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
1174
1175	/* mute and zero volume channels */
1176	for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); ++idx) {
1177	snd_azf3328_mixer_outw(chip,
1178	snd_azf3328_init_values[idx][0],
1179	snd_azf3328_init_values[idx][1]);
1180	}
1181
1182	/* add mixer controls */
1183	sw = snd_azf3328_mixer_controls;
1184	for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls);
1185	++idx, ++sw) {
1186	err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip));
1187	if (err < 0)
1188	return err;
1189	}
1190	snd_component_add(card, "AZF3328 mixer");
1191	strcpy(card->mixername, "AZF3328 mixer");
1192
1193	return 0;
1194	}
1195	#endif /* AZF_USE_AC97_LAYER */
1196
1197	static void
1198	snd_azf3328_codec_setfmt(struct snd_azf3328_codec_data *codec,
1199	enum azf_freq_t bitrate,
1200	unsigned int format_width,
1201	unsigned int channels
1202	)
1203	{
1204	unsigned long flags;
1205	u16 val = 0xff00;
1206	u8 freq = 0;
1207
1208	switch (bitrate) {
1209	case AZF_FREQ_4000: freq = SOUNDFORMAT_FREQ_SUSPECTED_4000; break;
1210	case AZF_FREQ_4800: freq = SOUNDFORMAT_FREQ_SUSPECTED_4800; break;
1211	case AZF_FREQ_5512:
1212	/* the AZF3328 names it "5510" for some strange reason */
1213	freq = SOUNDFORMAT_FREQ_5510; break;
1214	case AZF_FREQ_6620: freq = SOUNDFORMAT_FREQ_6620; break;
1215	case AZF_FREQ_8000: freq = SOUNDFORMAT_FREQ_8000; break;
1216	case AZF_FREQ_9600: freq = SOUNDFORMAT_FREQ_9600; break;
1217	case AZF_FREQ_11025: freq = SOUNDFORMAT_FREQ_11025; break;
1218	case AZF_FREQ_13240: freq = SOUNDFORMAT_FREQ_SUSPECTED_13240; break;
1219	case AZF_FREQ_16000: freq = SOUNDFORMAT_FREQ_16000; break;
1220	case AZF_FREQ_22050: freq = SOUNDFORMAT_FREQ_22050; break;
1221	case AZF_FREQ_32000: freq = SOUNDFORMAT_FREQ_32000; break;
1222	default:
1223	snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate);
1224	fallthrough;
1225	case AZF_FREQ_44100: freq = SOUNDFORMAT_FREQ_44100; break;
1226	case AZF_FREQ_48000: freq = SOUNDFORMAT_FREQ_48000; break;
1227	case AZF_FREQ_66200: freq = SOUNDFORMAT_FREQ_SUSPECTED_66200; break;
1228	}
1229	/* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */
1230	/* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */
1231	/* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */
1232	/* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */
1233	/* val = 0xff05; 5m11.556s (... -> 44100Hz) */
1234	/* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */
1235	/* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */
1236	/* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */
1237	/* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */
1238
1239	val |= freq;
1240
1241	if (channels == 2)
1242	val |= SOUNDFORMAT_FLAG_2CHANNELS;
1243
1244	if (format_width == 16)
1245	val |= SOUNDFORMAT_FLAG_16BIT;
1246
1247	spin_lock_irqsave(codec->lock, flags);
1248
1249	/* set bitrate/format */
1250	snd_azf3328_codec_outw(codec, IDX_IO_CODEC_SOUNDFORMAT, value: val);
1251
1252	/* changing the bitrate/format settings switches off the
1253	* audio output with an annoying click in case of 8/16bit format change
1254	* (maybe shutting down DAC/ADC?), thus immediately
1255	* do some tweaking to reenable it and get rid of the clicking
1256	* (FIXME: yes, it works, but what exactly am I doing here?? :)
1257	* FIXME: does this have some side effects for full-duplex
1258	* or other dramatic side effects? */
1259	/* do it for non-capture codecs only */
1260	if (codec->type != AZF_CODEC_CAPTURE)
1261	snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1262	value: snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS) |
1263	DMA_RUN_SOMETHING1 |
1264	DMA_RUN_SOMETHING2 |
1265	SOMETHING_ALMOST_ALWAYS_SET |
1266	DMA_EPILOGUE_SOMETHING |
1267	DMA_SOMETHING_ELSE
1268	);
1269
1270	spin_unlock_irqrestore(lock: codec->lock, flags);
1271	}
1272
1273	static inline void
1274	snd_azf3328_codec_setfmt_lowpower(struct snd_azf3328_codec_data *codec
1275	)
1276	{
1277	/* choose lowest frequency for low power consumption.
1278	* While this will cause louder noise due to rather coarse frequency,
1279	* it should never matter since output should always
1280	* get disabled properly when idle anyway. */
1281	snd_azf3328_codec_setfmt(codec, bitrate: AZF_FREQ_4000, format_width: 8, channels: 1);
1282	}
1283
1284	static void
1285	snd_azf3328_ctrl_reg_6AH_update(struct snd_azf3328 *chip,
1286	unsigned bitmask,
1287	bool enable
1288	)
1289	{
1290	bool do_mask = !enable;
1291	if (do_mask)
1292	chip->shadow_reg_ctrl_6AH |= bitmask;
1293	else
1294	chip->shadow_reg_ctrl_6AH &= ~bitmask;
1295	dev_dbg(chip->card->dev,
1296	"6AH_update mask 0x%04x do_mask %d: val 0x%04x\n",
1297	bitmask, do_mask, chip->shadow_reg_ctrl_6AH);
1298	snd_azf3328_ctrl_outw(chip, IDX_IO_6AH, value: chip->shadow_reg_ctrl_6AH);
1299	}
1300
1301	static inline void
1302	snd_azf3328_ctrl_enable_codecs(struct snd_azf3328 *chip, bool enable)
1303	{
1304	dev_dbg(chip->card->dev, "codec_enable %d\n", enable);
1305	/* no idea what exactly is being done here, but I strongly assume it's
1306	* PM related */
1307	snd_azf3328_ctrl_reg_6AH_update(
1308	chip, IO_6A_PAUSE_PLAYBACK_BIT8, enable
1309	);
1310	}
1311
1312	static void
1313	snd_azf3328_ctrl_codec_activity(struct snd_azf3328 *chip,
1314	enum snd_azf3328_codec_type codec_type,
1315	bool enable
1316	)
1317	{
1318	struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
1319	bool need_change = (codec->running != enable);
1320
1321	dev_dbg(chip->card->dev,
1322	"codec_activity: %s codec, enable %d, need_change %d\n",
1323	codec->name, enable, need_change
1324	);
1325	if (need_change) {
1326	static const struct {
1327	enum snd_azf3328_codec_type other1;
1328	enum snd_azf3328_codec_type other2;
1329	} peer_codecs[3] =
1330	{ { AZF_CODEC_CAPTURE, AZF_CODEC_I2S_OUT },
1331	{ AZF_CODEC_PLAYBACK, AZF_CODEC_I2S_OUT },
1332	{ AZF_CODEC_PLAYBACK, AZF_CODEC_CAPTURE } };
1333	bool call_function;
1334
1335	if (enable)
1336	/* if enable codec, call enable_codecs func
1337	to enable codec supply... */
1338	call_function = 1;
1339	else {
1340	/* ...otherwise call enable_codecs func
1341	(which globally shuts down operation of codecs)
1342	only in case the other codecs are currently
1343	not active either! */
1344	call_function =
1345	((!chip->codecs[peer_codecs[codec_type].other1]
1346	.running)
1347	&& (!chip->codecs[peer_codecs[codec_type].other2]
1348	.running));
1349	}
1350	if (call_function)
1351	snd_azf3328_ctrl_enable_codecs(chip, enable);
1352
1353	/* ...and adjust clock, too
1354	* (reduce noise and power consumption) */
1355	if (!enable)
1356	snd_azf3328_codec_setfmt_lowpower(codec);
1357	codec->running = enable;
1358	}
1359	}
1360
1361	static void
1362	snd_azf3328_codec_setdmaa(struct snd_azf3328 *chip,
1363	struct snd_azf3328_codec_data *codec,
1364	unsigned long addr,
1365	unsigned int period_bytes,
1366	unsigned int buffer_bytes
1367	)
1368	{
1369	WARN_ONCE(period_bytes & 1, "odd period length!?\n");
1370	WARN_ONCE(buffer_bytes != 2 * period_bytes,
1371	"missed our input expectations! %u vs. %u\n",
1372	buffer_bytes, period_bytes);
1373	if (!codec->running) {
1374	/* AZF3328 uses a two buffer pointer DMA transfer approach */
1375
1376	unsigned long flags;
1377
1378	/* width 32bit (prevent overflow): */
1379	u32 area_length;
1380	struct codec_setup_io {
1381	u32 dma_start_1;
1382	u32 dma_start_2;
1383	u32 dma_lengths;
1384	} __packed setup_io;
1385
1386	area_length = buffer_bytes/2;
1387
1388	setup_io.dma_start_1 = addr;
1389	setup_io.dma_start_2 = addr+area_length;
1390
1391	dev_dbg(chip->card->dev,
1392	"setdma: buffers %08x[%u] / %08x[%u], %u, %u\n",
1393	setup_io.dma_start_1, area_length,
1394	setup_io.dma_start_2, area_length,
1395	period_bytes, buffer_bytes);
1396
1397	/* Hmm, are we really supposed to decrement this by 1??
1398	Most definitely certainly not: configuring full length does
1399	work properly (i.e. likely better), and BTW we
1400	violated possibly differing frame sizes with this...
1401
1402	area_length--; |* max. index *|
1403	*/
1404
1405	/* build combined I/O buffer length word */
1406	setup_io.dma_lengths = (area_length << 16) | (area_length);
1407
1408	spin_lock_irqsave(codec->lock, flags);
1409	snd_azf3328_codec_outl_multi(
1410	codec, IDX_IO_CODEC_DMA_START_1, buffer: &setup_io, count: 3
1411	);
1412	spin_unlock_irqrestore(lock: codec->lock, flags);
1413	}
1414	}
1415
1416	static int
1417	snd_azf3328_pcm_prepare(struct snd_pcm_substream *substream)
1418	{
1419	struct snd_pcm_runtime *runtime = substream->runtime;
1420	struct snd_azf3328_codec_data *codec = runtime->private_data;
1421	#if 0
1422	unsigned int size = snd_pcm_lib_buffer_bytes(substream);
1423	unsigned int count = snd_pcm_lib_period_bytes(substream);
1424	#endif
1425
1426	codec->dma_base = runtime->dma_addr;
1427
1428	#if 0
1429	snd_azf3328_codec_setfmt(codec,
1430	runtime->rate,
1431	snd_pcm_format_width(runtime->format),
1432	runtime->channels);
1433	snd_azf3328_codec_setdmaa(chip, codec,
1434	runtime->dma_addr, count, size);
1435	#endif
1436	return 0;
1437	}
1438
1439	static int
1440	snd_azf3328_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1441	{
1442	struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1443	struct snd_pcm_runtime *runtime = substream->runtime;
1444	struct snd_azf3328_codec_data *codec = runtime->private_data;
1445	int result = 0;
1446	u16 flags1;
1447	bool previously_muted = false;
1448	bool is_main_mixer_playback_codec = (AZF_CODEC_PLAYBACK == codec->type);
1449
1450	switch (cmd) {
1451	case SNDRV_PCM_TRIGGER_START:
1452	dev_dbg(chip->card->dev, "START PCM %s\n", codec->name);
1453
1454	if (is_main_mixer_playback_codec) {
1455	/* mute WaveOut (avoid clicking during setup) */
1456	previously_muted =
1457	snd_azf3328_mixer_mute_control_pcm(
1458	chip, do_mute: 1
1459	);
1460	}
1461
1462	snd_azf3328_codec_setfmt(codec,
1463	bitrate: runtime->rate,
1464	format_width: snd_pcm_format_width(format: runtime->format),
1465	channels: runtime->channels);
1466
1467	spin_lock(lock: codec->lock);
1468	/* first, remember current value: */
1469	flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS);
1470
1471	/* stop transfer */
1472	flags1 &= ~DMA_RESUME;
1473	snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, value: flags1);
1474
1475	/* FIXME: clear interrupts or what??? */
1476	snd_azf3328_codec_outw(codec, IDX_IO_CODEC_IRQTYPE, value: 0xffff);
1477	spin_unlock(lock: codec->lock);
1478
1479	snd_azf3328_codec_setdmaa(chip, codec, addr: runtime->dma_addr,
1480	period_bytes: snd_pcm_lib_period_bytes(substream),
1481	buffer_bytes: snd_pcm_lib_buffer_bytes(substream)
1482	);
1483
1484	spin_lock(lock: codec->lock);
1485	#ifdef WIN9X
1486	/* FIXME: enable playback/recording??? */
1487	flags1 |= DMA_RUN_SOMETHING1 | DMA_RUN_SOMETHING2;
1488	snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1489
1490	/* start transfer again */
1491	/* FIXME: what is this value (0x0010)??? */
1492	flags1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
1493	snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1494	#else /* NT4 */
1495	snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1496	value: 0x0000);
1497	snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1498	DMA_RUN_SOMETHING1);
1499	snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1500	DMA_RUN_SOMETHING1 |
1501	DMA_RUN_SOMETHING2);
1502	snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1503	DMA_RESUME |
1504	SOMETHING_ALMOST_ALWAYS_SET |
1505	DMA_EPILOGUE_SOMETHING |
1506	DMA_SOMETHING_ELSE);
1507	#endif
1508	spin_unlock(lock: codec->lock);
1509	snd_azf3328_ctrl_codec_activity(chip, codec_type: codec->type, enable: 1);
1510
1511	if (is_main_mixer_playback_codec) {
1512	/* now unmute WaveOut */
1513	if (!previously_muted)
1514	snd_azf3328_mixer_mute_control_pcm(
1515	chip, do_mute: 0
1516	);
1517	}
1518
1519	dev_dbg(chip->card->dev, "PCM STARTED %s\n", codec->name);
1520	break;
1521	case SNDRV_PCM_TRIGGER_RESUME:
1522	dev_dbg(chip->card->dev, "PCM RESUME %s\n", codec->name);
1523	/* resume codec if we were active */
1524	spin_lock(lock: codec->lock);
1525	if (codec->running)
1526	snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1527	value: snd_azf3328_codec_inw(
1528	codec, IDX_IO_CODEC_DMA_FLAGS
1529	) | DMA_RESUME
1530	);
1531	spin_unlock(lock: codec->lock);
1532	break;
1533	case SNDRV_PCM_TRIGGER_STOP:
1534	dev_dbg(chip->card->dev, "PCM STOP %s\n", codec->name);
1535
1536	if (is_main_mixer_playback_codec) {
1537	/* mute WaveOut (avoid clicking during setup) */
1538	previously_muted =
1539	snd_azf3328_mixer_mute_control_pcm(
1540	chip, do_mute: 1
1541	);
1542	}
1543
1544	spin_lock(lock: codec->lock);
1545	/* first, remember current value: */
1546	flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS);
1547
1548	/* stop transfer */
1549	flags1 &= ~DMA_RESUME;
1550	snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, value: flags1);
1551
1552	/* hmm, is this really required? we're resetting the same bit
1553	* immediately thereafter... */
1554	flags1 |= DMA_RUN_SOMETHING1;
1555	snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, value: flags1);
1556
1557	flags1 &= ~DMA_RUN_SOMETHING1;
1558	snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, value: flags1);
1559	spin_unlock(lock: codec->lock);
1560	snd_azf3328_ctrl_codec_activity(chip, codec_type: codec->type, enable: 0);
1561
1562	if (is_main_mixer_playback_codec) {
1563	/* now unmute WaveOut */
1564	if (!previously_muted)
1565	snd_azf3328_mixer_mute_control_pcm(
1566	chip, do_mute: 0
1567	);
1568	}
1569
1570	dev_dbg(chip->card->dev, "PCM STOPPED %s\n", codec->name);
1571	break;
1572	case SNDRV_PCM_TRIGGER_SUSPEND:
1573	dev_dbg(chip->card->dev, "PCM SUSPEND %s\n", codec->name);
1574	/* make sure codec is stopped */
1575	snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1576	value: snd_azf3328_codec_inw(
1577	codec, IDX_IO_CODEC_DMA_FLAGS
1578	) & ~DMA_RESUME
1579	);
1580	break;
1581	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1582	WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
1583	break;
1584	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1585	WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
1586	break;
1587	default:
1588	WARN(1, "FIXME: unknown trigger mode!\n");
1589	return -EINVAL;
1590	}
1591
1592	return result;
1593	}
1594
1595	static snd_pcm_uframes_t
1596	snd_azf3328_pcm_pointer(struct snd_pcm_substream *substream
1597	)
1598	{
1599	const struct snd_azf3328_codec_data *codec =
1600	substream->runtime->private_data;
1601	unsigned long result;
1602	snd_pcm_uframes_t frmres;
1603
1604	result = snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_CURRPOS);
1605
1606	/* calculate offset */
1607	#ifdef QUERY_HARDWARE
1608	result -= snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_START_1);
1609	#else
1610	result -= codec->dma_base;
1611	#endif
1612	frmres = bytes_to_frames( runtime: substream->runtime, size: result);
1613	dev_dbg(substream->pcm->card->dev, "%08li %s @ 0x%8lx, frames %8ld\n",
1614	jiffies, codec->name, result, frmres);
1615	return frmres;
1616	}
1617
1618	/******************************************************************/
1619
1620	#ifdef SUPPORT_GAMEPORT
1621	static inline void
1622	snd_azf3328_gameport_irq_enable(struct snd_azf3328 *chip,
1623	bool enable
1624	)
1625	{
1626	snd_azf3328_io_reg_setb(
1627	reg: chip->game_io+IDX_GAME_HWCONFIG,
1628	GAME_HWCFG_IRQ_ENABLE,
1629	do_set: enable
1630	);
1631	}
1632
1633	static inline void
1634	snd_azf3328_gameport_legacy_address_enable(struct snd_azf3328 *chip,
1635	bool enable
1636	)
1637	{
1638	snd_azf3328_io_reg_setb(
1639	reg: chip->game_io+IDX_GAME_HWCONFIG,
1640	GAME_HWCFG_LEGACY_ADDRESS_ENABLE,
1641	do_set: enable
1642	);
1643	}
1644
1645	static void
1646	snd_azf3328_gameport_set_counter_frequency(struct snd_azf3328 *chip,
1647	unsigned int freq_cfg
1648	)
1649	{
1650	snd_azf3328_io_reg_setb(
1651	reg: chip->game_io+IDX_GAME_HWCONFIG,
1652	mask: 0x02,
1653	do_set: (freq_cfg & 1) != 0
1654	);
1655	snd_azf3328_io_reg_setb(
1656	reg: chip->game_io+IDX_GAME_HWCONFIG,
1657	mask: 0x04,
1658	do_set: (freq_cfg & 2) != 0
1659	);
1660	}
1661
1662	static inline void
1663	snd_azf3328_gameport_axis_circuit_enable(struct snd_azf3328 *chip, bool enable)
1664	{
1665	snd_azf3328_ctrl_reg_6AH_update(
1666	chip, IO_6A_SOMETHING2_GAMEPORT, enable
1667	);
1668	}
1669
1670	static inline void
1671	snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
1672	{
1673	/*
1674	* skeleton handler only
1675	* (we do not want axis reading in interrupt handler - too much load!)
1676	*/
1677	dev_dbg(chip->card->dev, "gameport irq\n");
1678
1679	/* this should ACK the gameport IRQ properly, hopefully. */
1680	snd_azf3328_game_inw(chip, IDX_GAME_AXIS_VALUE);
1681	}
1682
1683	static int
1684	snd_azf3328_gameport_open(struct gameport *gameport, int mode)
1685	{
1686	struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1687	int res;
1688
1689	dev_dbg(chip->card->dev, "gameport_open, mode %d\n", mode);
1690	switch (mode) {
1691	case GAMEPORT_MODE_COOKED:
1692	case GAMEPORT_MODE_RAW:
1693	res = 0;
1694	break;
1695	default:
1696	res = -1;
1697	break;
1698	}
1699
1700	snd_azf3328_gameport_set_counter_frequency(chip,
1701	GAME_HWCFG_ADC_COUNTER_FREQ_STD);
1702	snd_azf3328_gameport_axis_circuit_enable(chip, enable: (res == 0));
1703
1704	return res;
1705	}
1706
1707	static void
1708	snd_azf3328_gameport_close(struct gameport *gameport)
1709	{
1710	struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1711
1712	dev_dbg(chip->card->dev, "gameport_close\n");
1713	snd_azf3328_gameport_set_counter_frequency(chip,
1714	GAME_HWCFG_ADC_COUNTER_FREQ_1_200);
1715	snd_azf3328_gameport_axis_circuit_enable(chip, enable: 0);
1716	}
1717
1718	static int
1719	snd_azf3328_gameport_cooked_read(struct gameport *gameport,
1720	int *axes,
1721	int *buttons
1722	)
1723	{
1724	struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1725	int i;
1726	u8 val;
1727	unsigned long flags;
1728
1729	if (snd_BUG_ON(!chip))
1730	return 0;
1731
1732	spin_lock_irqsave(&chip->reg_lock, flags);
1733	val = snd_azf3328_game_inb(chip, IDX_GAME_LEGACY_COMPATIBLE);
1734	*buttons = (~(val) >> 4) & 0xf;
1735
1736	/* ok, this one is a bit dirty: cooked_read is being polled by a timer,
1737	* thus we're atomic and cannot actively wait in here
1738	* (which would be useful for us since it probably would be better
1739	* to trigger a measurement in here, then wait a short amount of
1740	* time until it's finished, then read values of _this_ measurement).
1741	*
1742	* Thus we simply resort to reading values if they're available already
1743	* and trigger the next measurement.
1744	*/
1745
1746	val = snd_azf3328_game_inb(chip, IDX_GAME_AXES_CONFIG);
1747	if (val & GAME_AXES_SAMPLING_READY) {
1748	for (i = 0; i < ARRAY_SIZE(chip->axes); ++i) {
1749	/* configure the axis to read */
1750	val = (i << 4) | 0x0f;
1751	snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, value: val);
1752
1753	chip->axes[i] = snd_azf3328_game_inw(
1754	chip, IDX_GAME_AXIS_VALUE
1755	);
1756	}
1757	}
1758
1759	/* trigger next sampling of axes, to be evaluated the next time we
1760	* enter this function */
1761
1762	/* for some very, very strange reason we cannot enable
1763	* Measurement Ready monitoring for all axes here,
1764	* at least not when only one joystick connected */
1765	val = 0x03; /* we're able to monitor axes 1 and 2 only */
1766	snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, value: val);
1767
1768	snd_azf3328_game_outw(chip, IDX_GAME_AXIS_VALUE, value: 0xffff);
1769	spin_unlock_irqrestore(lock: &chip->reg_lock, flags);
1770
1771	for (i = 0; i < ARRAY_SIZE(chip->axes); i++) {
1772	axes[i] = chip->axes[i];
1773	if (axes[i] == 0xffff)
1774	axes[i] = -1;
1775	}
1776
1777	dev_dbg(chip->card->dev, "cooked_read: axes %d %d %d %d buttons %d\n",
1778	axes[0], axes[1], axes[2], axes[3], *buttons);
1779
1780	return 0;
1781	}
1782
1783	static int
1784	snd_azf3328_gameport(struct snd_azf3328 *chip, int dev)
1785	{
1786	struct gameport *gp;
1787
1788	chip->gameport = gp = gameport_allocate_port();
1789	if (!gp) {
1790	dev_err(chip->card->dev, "cannot alloc memory for gameport\n");
1791	return -ENOMEM;
1792	}
1793
1794	gameport_set_name(gameport: gp, name: "AZF3328 Gameport");
1795	gameport_set_phys(gameport: gp, fmt: "pci%s/gameport0", pci_name(pdev: chip->pci));
1796	gameport_set_dev_parent(gp, &chip->pci->dev);
1797	gp->io = chip->game_io;
1798	gameport_set_port_data(gp, chip);
1799
1800	gp->open = snd_azf3328_gameport_open;
1801	gp->close = snd_azf3328_gameport_close;
1802	gp->fuzz = 16; /* seems ok */
1803	gp->cooked_read = snd_azf3328_gameport_cooked_read;
1804
1805	/* DISABLE legacy address: we don't need it! */
1806	snd_azf3328_gameport_legacy_address_enable(chip, enable: 0);
1807
1808	snd_azf3328_gameport_set_counter_frequency(chip,
1809	GAME_HWCFG_ADC_COUNTER_FREQ_1_200);
1810	snd_azf3328_gameport_axis_circuit_enable(chip, enable: 0);
1811
1812	gameport_register_port(chip->gameport);
1813
1814	return 0;
1815	}
1816
1817	static void
1818	snd_azf3328_gameport_free(struct snd_azf3328 *chip)
1819	{
1820	if (chip->gameport) {
1821	gameport_unregister_port(gameport: chip->gameport);
1822	chip->gameport = NULL;
1823	}
1824	snd_azf3328_gameport_irq_enable(chip, enable: 0);
1825	}
1826	#else
1827	static inline int
1828	snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) { return -ENOSYS; }
1829	static inline void
1830	snd_azf3328_gameport_free(struct snd_azf3328 *chip) { }
1831	static inline void
1832	snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
1833	{
1834	dev_warn(chip->card->dev, "huh, game port IRQ occurred!?\n");
1835	}
1836	#endif /* SUPPORT_GAMEPORT */
1837
1838	/******************************************************************/
1839
1840	static inline void
1841	snd_azf3328_irq_log_unknown_type(struct snd_azf3328 *chip, u8 which)
1842	{
1843	dev_dbg(chip->card->dev,
1844	"unknown IRQ type (%x) occurred, please report!\n",
1845	which);
1846	}
1847
1848	static inline void
1849	snd_azf3328_pcm_interrupt(struct snd_azf3328 *chip,
1850	const struct snd_azf3328_codec_data *first_codec,
1851	u8 status
1852	)
1853	{
1854	u8 which;
1855	enum snd_azf3328_codec_type codec_type;
1856	const struct snd_azf3328_codec_data *codec = first_codec;
1857
1858	for (codec_type = AZF_CODEC_PLAYBACK;
1859	codec_type <= AZF_CODEC_I2S_OUT;
1860	++codec_type, ++codec) {
1861
1862	/* skip codec if there's no interrupt for it */
1863	if (!(status & (1 << codec_type)))
1864	continue;
1865
1866	spin_lock(lock: codec->lock);
1867	which = snd_azf3328_codec_inb(codec, IDX_IO_CODEC_IRQTYPE);
1868	/* ack all IRQ types immediately */
1869	snd_azf3328_codec_outb(codec, IDX_IO_CODEC_IRQTYPE, value: which);
1870	spin_unlock(lock: codec->lock);
1871
1872	if (codec->substream) {
1873	snd_pcm_period_elapsed(substream: codec->substream);
1874	dev_dbg(chip->card->dev, "%s period done (#%x), @ %x\n",
1875	codec->name,
1876	which,
1877	snd_azf3328_codec_inl(
1878	codec, IDX_IO_CODEC_DMA_CURRPOS));
1879	} else
1880	dev_warn(chip->card->dev, "irq handler problem!\n");
1881	if (which & IRQ_SOMETHING)
1882	snd_azf3328_irq_log_unknown_type(chip, which);
1883	}
1884	}
1885
1886	static irqreturn_t
1887	snd_azf3328_interrupt(int irq, void *dev_id)
1888	{
1889	struct snd_azf3328 *chip = dev_id;
1890	u8 status;
1891	static unsigned long irq_count;
1892
1893	status = snd_azf3328_ctrl_inb(chip, IDX_IO_IRQSTATUS);
1894
1895	/* fast path out, to ease interrupt sharing */
1896	if (!(status &
1897	(IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT
1898	|IRQ_GAMEPORT|IRQ_MPU401|IRQ_TIMER)
1899	))
1900	return IRQ_NONE; /* must be interrupt for another device */
1901
1902	dev_dbg(chip->card->dev,
1903	"irq_count %ld! IDX_IO_IRQSTATUS %04x\n",
1904	irq_count++ /* debug-only */,
1905	status);
1906
1907	if (status & IRQ_TIMER) {
1908	/* dev_dbg(chip->card->dev, "timer %ld\n",
1909	snd_azf3328_codec_inl(chip, IDX_IO_TIMER_VALUE)
1910	& TIMER_VALUE_MASK
1911	); */
1912	if (chip->timer)
1913	snd_timer_interrupt(timer: chip->timer, ticks_left: chip->timer->sticks);
1914	/* ACK timer */
1915	spin_lock(lock: &chip->reg_lock);
1916	snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, value: 0x07);
1917	spin_unlock(lock: &chip->reg_lock);
1918	dev_dbg(chip->card->dev, "timer IRQ\n");
1919	}
1920
1921	if (status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT))
1922	snd_azf3328_pcm_interrupt(chip, first_codec: chip->codecs, status);
1923
1924	if (status & IRQ_GAMEPORT)
1925	snd_azf3328_gameport_interrupt(chip);
1926
1927	/* MPU401 has less critical IRQ requirements
1928	* than timer and playback/recording, right? */
1929	if (status & IRQ_MPU401) {
1930	snd_mpu401_uart_interrupt(irq, dev_id: chip->rmidi->private_data);
1931
1932	/* hmm, do we have to ack the IRQ here somehow?
1933	* If so, then I don't know how yet... */
1934	dev_dbg(chip->card->dev, "MPU401 IRQ\n");
1935	}
1936	return IRQ_HANDLED;
1937	}
1938
1939	/*****************************************************************/
1940
1941	/* as long as we think we have identical snd_pcm_hardware parameters
1942	for playback, capture and i2s out, we can use the same physical struct
1943	since the struct is simply being copied into a member.
1944	*/
1945	static const struct snd_pcm_hardware snd_azf3328_hardware =
1946	{
1947	/* FIXME!! Correct? */
1948	.info = SNDRV_PCM_INFO_MMAP |
1949	SNDRV_PCM_INFO_INTERLEAVED |
1950	SNDRV_PCM_INFO_MMAP_VALID,
1951	.formats = SNDRV_PCM_FMTBIT_S8 |
1952	SNDRV_PCM_FMTBIT_U8 |
1953	SNDRV_PCM_FMTBIT_S16_LE |
1954	SNDRV_PCM_FMTBIT_U16_LE,
1955	.rates = SNDRV_PCM_RATE_5512 |
1956	SNDRV_PCM_RATE_8000_48000 |
1957	SNDRV_PCM_RATE_KNOT,
1958	.rate_min = AZF_FREQ_4000,
1959	.rate_max = AZF_FREQ_66200,
1960	.channels_min = 1,
1961	.channels_max = 2,
1962	.buffer_bytes_max = (64*1024),
1963	.period_bytes_min = 1024,
1964	.period_bytes_max = (32*1024),
1965	/* We simply have two DMA areas (instead of a list of descriptors
1966	such as other cards); I believe that this is a fixed hardware
1967	attribute and there isn't much driver magic to be done to expand it.
1968	Thus indicate that we have at least and at most 2 periods. */
1969	.periods_min = 2,
1970	.periods_max = 2,
1971	/* FIXME: maybe that card actually has a FIFO?
1972	* Hmm, it seems newer revisions do have one, but we still don't know
1973	* its size... */
1974	.fifo_size = 0,
1975	};
1976
1977
1978	static const unsigned int snd_azf3328_fixed_rates[] = {
1979	AZF_FREQ_4000,
1980	AZF_FREQ_4800,
1981	AZF_FREQ_5512,
1982	AZF_FREQ_6620,
1983	AZF_FREQ_8000,
1984	AZF_FREQ_9600,
1985	AZF_FREQ_11025,
1986	AZF_FREQ_13240,
1987	AZF_FREQ_16000,
1988	AZF_FREQ_22050,
1989	AZF_FREQ_32000,
1990	AZF_FREQ_44100,
1991	AZF_FREQ_48000,
1992	AZF_FREQ_66200
1993	};
1994
1995	static const struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = {
1996	.count = ARRAY_SIZE(snd_azf3328_fixed_rates),
1997	.list = snd_azf3328_fixed_rates,
1998	.mask = 0,
1999	};
2000
2001	/*****************************************************************/
2002
2003	static int
2004	snd_azf3328_pcm_open(struct snd_pcm_substream *substream,
2005	enum snd_azf3328_codec_type codec_type
2006	)
2007	{
2008	struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
2009	struct snd_pcm_runtime *runtime = substream->runtime;
2010	struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
2011
2012	codec->substream = substream;
2013
2014	/* same parameters for all our codecs - at least we think so... */
2015	runtime->hw = snd_azf3328_hardware;
2016
2017	snd_pcm_hw_constraint_list(runtime, cond: 0, SNDRV_PCM_HW_PARAM_RATE,
2018	l: &snd_azf3328_hw_constraints_rates);
2019	runtime->private_data = codec;
2020	return 0;
2021	}
2022
2023	static int
2024	snd_azf3328_pcm_playback_open(struct snd_pcm_substream *substream)
2025	{
2026	return snd_azf3328_pcm_open(substream, codec_type: AZF_CODEC_PLAYBACK);
2027	}
2028
2029	static int
2030	snd_azf3328_pcm_capture_open(struct snd_pcm_substream *substream)
2031	{
2032	return snd_azf3328_pcm_open(substream, codec_type: AZF_CODEC_CAPTURE);
2033	}
2034
2035	static int
2036	snd_azf3328_pcm_i2s_out_open(struct snd_pcm_substream *substream)
2037	{
2038	return snd_azf3328_pcm_open(substream, codec_type: AZF_CODEC_I2S_OUT);
2039	}
2040
2041	static int
2042	snd_azf3328_pcm_close(struct snd_pcm_substream *substream
2043	)
2044	{
2045	struct snd_azf3328_codec_data *codec =
2046	substream->runtime->private_data;
2047
2048	codec->substream = NULL;
2049	return 0;
2050	}
2051
2052	/******************************************************************/
2053
2054	static const struct snd_pcm_ops snd_azf3328_playback_ops = {
2055	.open = snd_azf3328_pcm_playback_open,
2056	.close = snd_azf3328_pcm_close,
2057	.prepare = snd_azf3328_pcm_prepare,
2058	.trigger = snd_azf3328_pcm_trigger,
2059	.pointer = snd_azf3328_pcm_pointer
2060	};
2061
2062	static const struct snd_pcm_ops snd_azf3328_capture_ops = {
2063	.open = snd_azf3328_pcm_capture_open,
2064	.close = snd_azf3328_pcm_close,
2065	.prepare = snd_azf3328_pcm_prepare,
2066	.trigger = snd_azf3328_pcm_trigger,
2067	.pointer = snd_azf3328_pcm_pointer
2068	};
2069
2070	static const struct snd_pcm_ops snd_azf3328_i2s_out_ops = {
2071	.open = snd_azf3328_pcm_i2s_out_open,
2072	.close = snd_azf3328_pcm_close,
2073	.prepare = snd_azf3328_pcm_prepare,
2074	.trigger = snd_azf3328_pcm_trigger,
2075	.pointer = snd_azf3328_pcm_pointer
2076	};
2077
2078	static int
2079	snd_azf3328_pcm(struct snd_azf3328 *chip)
2080	{
2081	/* pcm devices */
2082	enum { AZF_PCMDEV_STD, AZF_PCMDEV_I2S_OUT, NUM_AZF_PCMDEVS };
2083
2084	struct snd_pcm *pcm;
2085	int err;
2086
2087	err = snd_pcm_new(card: chip->card, id: "AZF3328 DSP", device: AZF_PCMDEV_STD,
2088	playback_count: 1, capture_count: 1, rpcm: &pcm);
2089	if (err < 0)
2090	return err;
2091	snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_PLAYBACK,
2092	ops: &snd_azf3328_playback_ops);
2093	snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_CAPTURE,
2094	ops: &snd_azf3328_capture_ops);
2095
2096	pcm->private_data = chip;
2097	pcm->info_flags = 0;
2098	strcpy(p: pcm->name, q: chip->card->shortname);
2099	/* same pcm object for playback/capture (see snd_pcm_new() above) */
2100	chip->pcm[AZF_CODEC_PLAYBACK] = pcm;
2101	chip->pcm[AZF_CODEC_CAPTURE] = pcm;
2102
2103	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, data: &chip->pci->dev,
2104	size: 64*1024, max: 64*1024);
2105
2106	err = snd_pcm_new(card: chip->card, id: "AZF3328 I2S OUT", device: AZF_PCMDEV_I2S_OUT,
2107	playback_count: 1, capture_count: 0, rpcm: &pcm);
2108	if (err < 0)
2109	return err;
2110	snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_PLAYBACK,
2111	ops: &snd_azf3328_i2s_out_ops);
2112
2113	pcm->private_data = chip;
2114	pcm->info_flags = 0;
2115	strcpy(p: pcm->name, q: chip->card->shortname);
2116	chip->pcm[AZF_CODEC_I2S_OUT] = pcm;
2117
2118	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, data: &chip->pci->dev,
2119	size: 64*1024, max: 64*1024);
2120
2121	return 0;
2122	}
2123
2124	/******************************************************************/
2125
2126	/*** NOTE: the physical timer resolution actually is 1024000 ticks per second
2127	*** (probably derived from main crystal via a divider of 24),
2128	*** but announcing those attributes to user-space would make programs
2129	*** configure the timer to a 1 tick value, resulting in an absolutely fatal
2130	*** timer IRQ storm.
2131	*** Thus I chose to announce a down-scaled virtual timer to the outside and
2132	*** calculate real timer countdown values internally.
2133	*** (the scale factor can be set via module parameter "seqtimer_scaling").
2134	***/
2135
2136	static int
2137	snd_azf3328_timer_start(struct snd_timer *timer)
2138	{
2139	struct snd_azf3328 *chip;
2140	unsigned long flags;
2141	unsigned int delay;
2142
2143	chip = snd_timer_chip(timer);
2144	delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK;
2145	if (delay < 49) {
2146	/* uhoh, that's not good, since user-space won't know about
2147	* this timing tweak
2148	* (we need to do it to avoid a lockup, though) */
2149
2150	dev_dbg(chip->card->dev, "delay was too low (%d)!\n", delay);
2151	delay = 49; /* minimum time is 49 ticks */
2152	}
2153	dev_dbg(chip->card->dev, "setting timer countdown value %d\n", delay);
2154	delay |= TIMER_COUNTDOWN_ENABLE | TIMER_IRQ_ENABLE;
2155	spin_lock_irqsave(&chip->reg_lock, flags);
2156	snd_azf3328_ctrl_outl(chip, IDX_IO_TIMER_VALUE, value: delay);
2157	spin_unlock_irqrestore(lock: &chip->reg_lock, flags);
2158	return 0;
2159	}
2160
2161	static int
2162	snd_azf3328_timer_stop(struct snd_timer *timer)
2163	{
2164	struct snd_azf3328 *chip;
2165	unsigned long flags;
2166
2167	chip = snd_timer_chip(timer);
2168	spin_lock_irqsave(&chip->reg_lock, flags);
2169	/* disable timer countdown and interrupt */
2170	/* Hmm, should we write TIMER_IRQ_ACK here?
2171	YES indeed, otherwise a rogue timer operation - which prompts
2172	ALSA(?) to call repeated stop() in vain, but NOT start() -
2173	will never end (value 0x03 is kept shown in control byte).
2174	Simply manually poking 0x04 _once_ immediately successfully stops
2175	the hardware/ALSA interrupt activity. */
2176	snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, value: 0x04);
2177	spin_unlock_irqrestore(lock: &chip->reg_lock, flags);
2178	return 0;
2179	}
2180
2181
2182	static int
2183	snd_azf3328_timer_precise_resolution(struct snd_timer *timer,
2184	unsigned long *num, unsigned long *den)
2185	{
2186	*num = 1;
2187	*den = 1024000 / seqtimer_scaling;
2188	return 0;
2189	}
2190
2191	static struct snd_timer_hardware snd_azf3328_timer_hw = {
2192	.flags = SNDRV_TIMER_HW_AUTO,
2193	.resolution = 977, /* 1000000/1024000 = 0.9765625us */
2194	.ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */
2195	.start = snd_azf3328_timer_start,
2196	.stop = snd_azf3328_timer_stop,
2197	.precise_resolution = snd_azf3328_timer_precise_resolution,
2198	};
2199
2200	static int
2201	snd_azf3328_timer(struct snd_azf3328 *chip, int device)
2202	{
2203	struct snd_timer *timer = NULL;
2204	struct snd_timer_id tid;
2205	int err;
2206
2207	tid.dev_class = SNDRV_TIMER_CLASS_CARD;
2208	tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
2209	tid.card = chip->card->number;
2210	tid.device = device;
2211	tid.subdevice = 0;
2212
2213	snd_azf3328_timer_hw.resolution *= seqtimer_scaling;
2214	snd_azf3328_timer_hw.ticks /= seqtimer_scaling;
2215
2216	err = snd_timer_new(card: chip->card, id: "AZF3328", tid: &tid, rtimer: &timer);
2217	if (err < 0)
2218	goto out;
2219
2220	strcpy(p: timer->name, q: "AZF3328 timer");
2221	timer->private_data = chip;
2222	timer->hw = snd_azf3328_timer_hw;
2223
2224	chip->timer = timer;
2225
2226	snd_azf3328_timer_stop(timer);
2227
2228	err = 0;
2229
2230	out:
2231	return err;
2232	}
2233
2234	/******************************************************************/
2235
2236	static void
2237	snd_azf3328_free(struct snd_card *card)
2238	{
2239	struct snd_azf3328 *chip = card->private_data;
2240
2241	snd_azf3328_mixer_reset(chip);
2242
2243	snd_azf3328_timer_stop(timer: chip->timer);
2244	snd_azf3328_gameport_free(chip);
2245	}
2246
2247	#if 0
2248	/* check whether a bit can be modified */
2249	static void
2250	snd_azf3328_test_bit(unsigned unsigned reg, int bit)
2251	{
2252	unsigned char val, valoff, valon;
2253
2254	val = inb(reg);
2255
2256	outb(val & ~(1 << bit), reg);
2257	valoff = inb(reg);
2258
2259	outb(val|(1 << bit), reg);
2260	valon = inb(reg);
2261
2262	outb(val, reg);
2263
2264	printk(KERN_DEBUG "reg %04x bit %d: %02x %02x %02x\n",
2265	reg, bit, val, valoff, valon
2266	);
2267	}
2268	#endif
2269
2270	static inline void
2271	snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip)
2272	{
2273	u16 tmp;
2274
2275	dev_dbg(chip->card->dev,
2276	"ctrl_io 0x%lx, game_io 0x%lx, mpu_io 0x%lx, "
2277	"opl3_io 0x%lx, mixer_io 0x%lx, irq %d\n",
2278	chip->ctrl_io, chip->game_io, chip->mpu_io,
2279	chip->opl3_io, chip->mixer_io, chip->irq);
2280
2281	dev_dbg(chip->card->dev,
2282	"game %02x %02x %02x %02x %02x %02x\n",
2283	snd_azf3328_game_inb(chip, 0),
2284	snd_azf3328_game_inb(chip, 1),
2285	snd_azf3328_game_inb(chip, 2),
2286	snd_azf3328_game_inb(chip, 3),
2287	snd_azf3328_game_inb(chip, 4),
2288	snd_azf3328_game_inb(chip, 5));
2289
2290	for (tmp = 0; tmp < 0x07; tmp += 1)
2291	dev_dbg(chip->card->dev,
2292	"mpu_io 0x%04x\n", inb(chip->mpu_io + tmp));
2293
2294	for (tmp = 0; tmp <= 0x07; tmp += 1)
2295	dev_dbg(chip->card->dev,
2296	"0x%02x: game200 0x%04x, game208 0x%04x\n",
2297	tmp, inb(0x200 + tmp), inb(0x208 + tmp));
2298
2299	for (tmp = 0; tmp <= 0x01; tmp += 1)
2300	dev_dbg(chip->card->dev,
2301	"0x%02x: mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, "
2302	"mpu330 0x%04x opl388 0x%04x opl38c 0x%04x\n",
2303	tmp,
2304	inb(0x300 + tmp),
2305	inb(0x310 + tmp),
2306	inb(0x320 + tmp),
2307	inb(0x330 + tmp),
2308	inb(0x388 + tmp),
2309	inb(0x38c + tmp));
2310
2311	for (tmp = 0; tmp < AZF_IO_SIZE_CTRL; tmp += 2)
2312	dev_dbg(chip->card->dev,
2313	"ctrl 0x%02x: 0x%04x\n",
2314	tmp, snd_azf3328_ctrl_inw(chip, tmp));
2315
2316	for (tmp = 0; tmp < AZF_IO_SIZE_MIXER; tmp += 2)
2317	dev_dbg(chip->card->dev,
2318	"mixer 0x%02x: 0x%04x\n",
2319	tmp, snd_azf3328_mixer_inw(chip, tmp));
2320	}
2321
2322	static int
2323	snd_azf3328_create(struct snd_card *card,
2324	struct pci_dev *pci,
2325	unsigned long device_type)
2326	{
2327	struct snd_azf3328 *chip = card->private_data;
2328	int err;
2329	u8 dma_init;
2330	enum snd_azf3328_codec_type codec_type;
2331	struct snd_azf3328_codec_data *codec_setup;
2332
2333	err = pcim_enable_device(pdev: pci);
2334	if (err < 0)
2335	return err;
2336
2337	spin_lock_init(&chip->reg_lock);
2338	chip->card = card;
2339	chip->pci = pci;
2340	chip->irq = -1;
2341
2342	/* check if we can restrict PCI DMA transfers to 24 bits */
2343	if (dma_set_mask_and_coherent(dev: &pci->dev, DMA_BIT_MASK(24))) {
2344	dev_err(card->dev,
2345	"architecture does not support 24bit PCI busmaster DMA\n"
2346	);
2347	return -ENXIO;
2348	}
2349
2350	err = pci_request_regions(pci, "Aztech AZF3328");
2351	if (err < 0)
2352	return err;
2353
2354	chip->ctrl_io = pci_resource_start(pci, 0);
2355	chip->game_io = pci_resource_start(pci, 1);
2356	chip->mpu_io = pci_resource_start(pci, 2);
2357	chip->opl3_io = pci_resource_start(pci, 3);
2358	chip->mixer_io = pci_resource_start(pci, 4);
2359
2360	codec_setup = &chip->codecs[AZF_CODEC_PLAYBACK];
2361	codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_PLAYBACK;
2362	codec_setup->lock = &chip->reg_lock;
2363	codec_setup->type = AZF_CODEC_PLAYBACK;
2364	codec_setup->name = "PLAYBACK";
2365
2366	codec_setup = &chip->codecs[AZF_CODEC_CAPTURE];
2367	codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_CAPTURE;
2368	codec_setup->lock = &chip->reg_lock;
2369	codec_setup->type = AZF_CODEC_CAPTURE;
2370	codec_setup->name = "CAPTURE";
2371
2372	codec_setup = &chip->codecs[AZF_CODEC_I2S_OUT];
2373	codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_I2S_OUT;
2374	codec_setup->lock = &chip->reg_lock;
2375	codec_setup->type = AZF_CODEC_I2S_OUT;
2376	codec_setup->name = "I2S_OUT";
2377
2378	if (devm_request_irq(dev: &pci->dev, irq: pci->irq, handler: snd_azf3328_interrupt,
2379	IRQF_SHARED, KBUILD_MODNAME, dev_id: chip)) {
2380	dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2381	return -EBUSY;
2382	}
2383	chip->irq = pci->irq;
2384	card->sync_irq = chip->irq;
2385	card->private_free = snd_azf3328_free;
2386	pci_set_master(dev: pci);
2387
2388	snd_azf3328_debug_show_ports(chip);
2389
2390	/* create mixer interface & switches */
2391	err = snd_azf3328_mixer_new(chip);
2392	if (err < 0)
2393	return err;
2394
2395	/* standard codec init stuff */
2396	/* default DMA init value */
2397	dma_init = DMA_RUN_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE;
2398
2399	for (codec_type = AZF_CODEC_PLAYBACK;
2400	codec_type <= AZF_CODEC_I2S_OUT; ++codec_type) {
2401	struct snd_azf3328_codec_data *codec =
2402	&chip->codecs[codec_type];
2403
2404	/* shutdown codecs to reduce power / noise */
2405	/* have ...ctrl_codec_activity() act properly */
2406	codec->running = true;
2407	snd_azf3328_ctrl_codec_activity(chip, codec_type, enable: 0);
2408
2409	spin_lock_irq(lock: codec->lock);
2410	snd_azf3328_codec_outb(codec, IDX_IO_CODEC_DMA_FLAGS,
2411	value: dma_init);
2412	spin_unlock_irq(lock: codec->lock);
2413	}
2414
2415	return 0;
2416	}
2417
2418	static int
2419	__snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2420	{
2421	static int dev;
2422	struct snd_card *card;
2423	struct snd_azf3328 *chip;
2424	struct snd_opl3 *opl3;
2425	int err;
2426
2427	if (dev >= SNDRV_CARDS)
2428	return -ENODEV;
2429	if (!enable[dev]) {
2430	dev++;
2431	return -ENOENT;
2432	}
2433
2434	err = snd_devm_card_new(parent: &pci->dev, idx: index[dev], xid: id[dev], THIS_MODULE,
2435	extra_size: sizeof(*chip), card_ret: &card);
2436	if (err < 0)
2437	return err;
2438	chip = card->private_data;
2439
2440	strcpy(p: card->driver, q: "AZF3328");
2441	strcpy(p: card->shortname, q: "Aztech AZF3328 (PCI168)");
2442
2443	err = snd_azf3328_create(card, pci, device_type: pci_id->driver_data);
2444	if (err < 0)
2445	return err;
2446
2447	/* chose to use MPU401_HW_AZT2320 ID instead of MPU401_HW_MPU401,
2448	since our hardware ought to be similar, thus use same ID. */
2449	err = snd_mpu401_uart_new(
2450	card, device: 0,
2451	MPU401_HW_AZT2320, port: chip->mpu_io,
2452	MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
2453	irq: -1, rrawmidi: &chip->rmidi
2454	);
2455	if (err < 0) {
2456	dev_err(card->dev, "no MPU-401 device at 0x%lx?\n",
2457	chip->mpu_io
2458	);
2459	return err;
2460	}
2461
2462	err = snd_azf3328_timer(chip, device: 0);
2463	if (err < 0)
2464	return err;
2465
2466	err = snd_azf3328_pcm(chip);
2467	if (err < 0)
2468	return err;
2469
2470	if (snd_opl3_create(card, l_port: chip->opl3_io, r_port: chip->opl3_io+2,
2471	OPL3_HW_AUTO, integrated: 1, opl3: &opl3) < 0) {
2472	dev_err(card->dev, "no OPL3 device at 0x%lx-0x%lx?\n",
2473	chip->opl3_io, chip->opl3_io+2
2474	);
2475	} else {
2476	/* need to use IDs 1, 2 since ID 0 is snd_azf3328_timer above */
2477	err = snd_opl3_timer_new(opl3, timer1_dev: 1, timer2_dev: 2);
2478	if (err < 0)
2479	return err;
2480	err = snd_opl3_hwdep_new(opl3, device: 0, seq_device: 1, NULL);
2481	if (err < 0)
2482	return err;
2483	opl3->private_data = chip;
2484	}
2485
2486	sprintf(buf: card->longname, fmt: "%s at 0x%lx, irq %i",
2487	card->shortname, chip->ctrl_io, chip->irq);
2488
2489	err = snd_card_register(card);
2490	if (err < 0)
2491	return err;
2492
2493	#ifdef MODULE
2494	dev_info(card->dev,
2495	"Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n");
2496	dev_info(card->dev,
2497	"Hardware was completely undocumented, unfortunately.\n");
2498	dev_info(card->dev,
2499	"Feel free to contact andi AT lisas.de for bug reports etc.!\n");
2500	dev_info(card->dev,
2501	"User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n",
2502	1024000 / seqtimer_scaling, seqtimer_scaling);
2503	#endif
2504
2505	snd_azf3328_gameport(chip, dev);
2506
2507	pci_set_drvdata(pdev: pci, data: card);
2508	dev++;
2509	return 0;
2510	}
2511
2512	static int
2513	snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2514	{
2515	return snd_card_free_on_error(dev: &pci->dev, ret: __snd_azf3328_probe(pci, pci_id));
2516	}
2517
2518	static inline void
2519	snd_azf3328_suspend_regs(const struct snd_azf3328 *chip,
2520	unsigned long io_addr, unsigned count, u32 *saved_regs)
2521	{
2522	unsigned reg;
2523
2524	for (reg = 0; reg < count; ++reg) {
2525	*saved_regs = inl(port: io_addr);
2526	dev_dbg(chip->card->dev, "suspend: io 0x%04lx: 0x%08x\n",
2527	io_addr, *saved_regs);
2528	++saved_regs;
2529	io_addr += sizeof(*saved_regs);
2530	}
2531	}
2532
2533	static inline void
2534	snd_azf3328_resume_regs(const struct snd_azf3328 *chip,
2535	const u32 *saved_regs,
2536	unsigned long io_addr,
2537	unsigned count
2538	)
2539	{
2540	unsigned reg;
2541
2542	for (reg = 0; reg < count; ++reg) {
2543	outl(value: *saved_regs, port: io_addr);
2544	dev_dbg(chip->card->dev,
2545	"resume: io 0x%04lx: 0x%08x --> 0x%08x\n",
2546	io_addr, *saved_regs, inl(io_addr));
2547	++saved_regs;
2548	io_addr += sizeof(*saved_regs);
2549	}
2550	}
2551
2552	static inline void
2553	snd_azf3328_suspend_ac97(struct snd_azf3328 *chip)
2554	{
2555	#ifdef AZF_USE_AC97_LAYER
2556	snd_ac97_suspend(ac97: chip->ac97);
2557	#else
2558	snd_azf3328_suspend_regs(chip, chip->mixer_io,
2559	ARRAY_SIZE(chip->saved_regs_mixer), chip->saved_regs_mixer);
2560
2561	/* make sure to disable master volume etc. to prevent looping sound */
2562	snd_azf3328_mixer_mute_control_master(chip, 1);
2563	snd_azf3328_mixer_mute_control_pcm(chip, 1);
2564	#endif /* AZF_USE_AC97_LAYER */
2565	}
2566
2567	static inline void
2568	snd_azf3328_resume_ac97(const struct snd_azf3328 *chip)
2569	{
2570	#ifdef AZF_USE_AC97_LAYER
2571	snd_ac97_resume(ac97: chip->ac97);
2572	#else
2573	snd_azf3328_resume_regs(chip, chip->saved_regs_mixer, chip->mixer_io,
2574	ARRAY_SIZE(chip->saved_regs_mixer));
2575
2576	/* unfortunately with 32bit transfers, IDX_MIXER_PLAY_MASTER (0x02)
2577	and IDX_MIXER_RESET (offset 0x00) get touched at the same time,
2578	resulting in a mixer reset condition persisting until _after_
2579	master vol was restored. Thus master vol needs an extra restore. */
2580	outw(((u16 *)chip->saved_regs_mixer)[1], chip->mixer_io + 2);
2581	#endif /* AZF_USE_AC97_LAYER */
2582	}
2583
2584	static int
2585	snd_azf3328_suspend(struct device *dev)
2586	{
2587	struct snd_card *card = dev_get_drvdata(dev);
2588	struct snd_azf3328 *chip = card->private_data;
2589	u16 *saved_regs_ctrl_u16;
2590
2591	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2592
2593	snd_azf3328_suspend_ac97(chip);
2594
2595	snd_azf3328_suspend_regs(chip, io_addr: chip->ctrl_io,
2596	ARRAY_SIZE(chip->saved_regs_ctrl), saved_regs: chip->saved_regs_ctrl);
2597
2598	/* manually store the one currently relevant write-only reg, too */
2599	saved_regs_ctrl_u16 = (u16 *)chip->saved_regs_ctrl;
2600	saved_regs_ctrl_u16[IDX_IO_6AH / 2] = chip->shadow_reg_ctrl_6AH;
2601
2602	snd_azf3328_suspend_regs(chip, io_addr: chip->game_io,
2603	ARRAY_SIZE(chip->saved_regs_game), saved_regs: chip->saved_regs_game);
2604	snd_azf3328_suspend_regs(chip, io_addr: chip->mpu_io,
2605	ARRAY_SIZE(chip->saved_regs_mpu), saved_regs: chip->saved_regs_mpu);
2606	snd_azf3328_suspend_regs(chip, io_addr: chip->opl3_io,
2607	ARRAY_SIZE(chip->saved_regs_opl3), saved_regs: chip->saved_regs_opl3);
2608	return 0;
2609	}
2610
2611	static int
2612	snd_azf3328_resume(struct device *dev)
2613	{
2614	struct snd_card *card = dev_get_drvdata(dev);
2615	const struct snd_azf3328 *chip = card->private_data;
2616
2617	snd_azf3328_resume_regs(chip, saved_regs: chip->saved_regs_game, io_addr: chip->game_io,
2618	ARRAY_SIZE(chip->saved_regs_game));
2619	snd_azf3328_resume_regs(chip, saved_regs: chip->saved_regs_mpu, io_addr: chip->mpu_io,
2620	ARRAY_SIZE(chip->saved_regs_mpu));
2621	snd_azf3328_resume_regs(chip, saved_regs: chip->saved_regs_opl3, io_addr: chip->opl3_io,
2622	ARRAY_SIZE(chip->saved_regs_opl3));
2623
2624	snd_azf3328_resume_ac97(chip);
2625
2626	snd_azf3328_resume_regs(chip, saved_regs: chip->saved_regs_ctrl, io_addr: chip->ctrl_io,
2627	ARRAY_SIZE(chip->saved_regs_ctrl));
2628
2629	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2630	return 0;
2631	}
2632
2633	static DEFINE_SIMPLE_DEV_PM_OPS(snd_azf3328_pm, snd_azf3328_suspend, snd_azf3328_resume);
2634
2635	static struct pci_driver azf3328_driver = {
2636	.name = KBUILD_MODNAME,
2637	.id_table = snd_azf3328_ids,
2638	.probe = snd_azf3328_probe,
2639	.driver = {
2640	.pm = &snd_azf3328_pm,
2641	},
2642	};
2643
2644	module_pci_driver(azf3328_driver);
2645