1 | //===--- BuiltinsPPC.def - PowerPC Builtin function database ----*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file defines the PowerPC-specific builtin function database. Users of |
10 | // this file must define the BUILTIN macro or the CUSTOM_BUILTIN macro to |
11 | // make use of this information. The latter is used for builtins requiring |
12 | // custom code generation and checking. |
13 | // |
14 | //===----------------------------------------------------------------------===// |
15 | |
16 | // FIXME: this needs to be the full list supported by GCC. Right now, I'm just |
17 | // adding stuff on demand. |
18 | |
19 | // The format of this database matches clang/Basic/Builtins.def except for the |
20 | // MMA builtins that are using their own format documented below. |
21 | |
22 | #ifndef BUILTIN |
23 | #define BUILTIN(ID, TYPE, ATTRS) |
24 | #endif |
25 | |
26 | #if defined(BUILTIN) && !defined(TARGET_BUILTIN) |
27 | #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS) |
28 | #endif |
29 | |
30 | #ifndef CUSTOM_BUILTIN |
31 | #define CUSTOM_BUILTIN(ID, INTR, TYPES, ACCUMULATE, FEATURE) \ |
32 | TARGET_BUILTIN(__builtin_##ID, "i.", "t", FEATURE) |
33 | #endif |
34 | |
35 | #define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE, FEATURE) \ |
36 | CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE, FEATURE) |
37 | |
38 | // GCC predefined macros to rename builtins, undef them to keep original names. |
39 | #if defined(__GNUC__) && !defined(__clang__) |
40 | #undef __builtin_vsx_xvnmaddadp |
41 | #undef __builtin_vsx_xvnmaddasp |
42 | #undef __builtin_vsx_xvmsubasp |
43 | #undef __builtin_vsx_xvmsubadp |
44 | #undef __builtin_vsx_xvmaddadp |
45 | #undef __builtin_vsx_xvnmsubasp |
46 | #undef __builtin_vsx_xvnmsubadp |
47 | #undef __builtin_vsx_xvmaddasp |
48 | #endif |
49 | |
50 | // XL Compatibility built-ins |
51 | BUILTIN(__builtin_ppc_popcntb, "ULiULi" , "" ) |
52 | BUILTIN(__builtin_ppc_poppar4, "iUi" , "" ) |
53 | BUILTIN(__builtin_ppc_poppar8, "iULLi" , "" ) |
54 | BUILTIN(__builtin_ppc_eieio, "v" , "" ) |
55 | BUILTIN(__builtin_ppc_iospace_eieio, "v" , "" ) |
56 | BUILTIN(__builtin_ppc_isync, "v" , "" ) |
57 | BUILTIN(__builtin_ppc_lwsync, "v" , "" ) |
58 | BUILTIN(__builtin_ppc_iospace_lwsync, "v" , "" ) |
59 | BUILTIN(__builtin_ppc_sync, "v" , "" ) |
60 | BUILTIN(__builtin_ppc_iospace_sync, "v" , "" ) |
61 | BUILTIN(__builtin_ppc_dcbfl, "vvC*" , "" ) |
62 | BUILTIN(__builtin_ppc_dcbflp, "vvC*" , "" ) |
63 | BUILTIN(__builtin_ppc_dcbst, "vvC*" , "" ) |
64 | BUILTIN(__builtin_ppc_dcbt, "vv*" , "" ) |
65 | BUILTIN(__builtin_ppc_dcbtst, "vv*" , "" ) |
66 | BUILTIN(__builtin_ppc_dcbz, "vv*" , "" ) |
67 | TARGET_BUILTIN(__builtin_ppc_icbt, "vv*" , "" , "isa-v207-instructions" ) |
68 | BUILTIN(__builtin_ppc_fric, "dd" , "" ) |
69 | BUILTIN(__builtin_ppc_frim, "dd" , "" ) |
70 | BUILTIN(__builtin_ppc_frims, "ff" , "" ) |
71 | BUILTIN(__builtin_ppc_frin, "dd" , "" ) |
72 | BUILTIN(__builtin_ppc_frins, "ff" , "" ) |
73 | BUILTIN(__builtin_ppc_frip, "dd" , "" ) |
74 | BUILTIN(__builtin_ppc_frips, "ff" , "" ) |
75 | BUILTIN(__builtin_ppc_friz, "dd" , "" ) |
76 | BUILTIN(__builtin_ppc_frizs, "ff" , "" ) |
77 | BUILTIN(__builtin_ppc_fsel, "dddd" , "" ) |
78 | BUILTIN(__builtin_ppc_fsels, "ffff" , "" ) |
79 | BUILTIN(__builtin_ppc_frsqrte, "dd" , "" ) |
80 | BUILTIN(__builtin_ppc_frsqrtes, "ff" , "" ) |
81 | BUILTIN(__builtin_ppc_fsqrt, "dd" , "" ) |
82 | BUILTIN(__builtin_ppc_fsqrts, "ff" , "" ) |
83 | BUILTIN(__builtin_ppc_compare_and_swap, "iiD*i*i" , "" ) |
84 | BUILTIN(__builtin_ppc_compare_and_swaplp, "iLiD*Li*Li" , "" ) |
85 | BUILTIN(__builtin_ppc_fetch_and_add, "iiD*i" , "" ) |
86 | BUILTIN(__builtin_ppc_fetch_and_addlp, "LiLiD*Li" , "" ) |
87 | BUILTIN(__builtin_ppc_fetch_and_and, "UiUiD*Ui" , "" ) |
88 | BUILTIN(__builtin_ppc_fetch_and_andlp, "ULiULiD*ULi" , "" ) |
89 | BUILTIN(__builtin_ppc_fetch_and_or, "UiUiD*Ui" , "" ) |
90 | BUILTIN(__builtin_ppc_fetch_and_orlp, "ULiULiD*ULi" , "" ) |
91 | BUILTIN(__builtin_ppc_fetch_and_swap, "UiUiD*Ui" , "" ) |
92 | BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi" , "" ) |
93 | BUILTIN(__builtin_ppc_ldarx, "LiLiD*" , "" ) |
94 | BUILTIN(__builtin_ppc_lwarx, "iiD*" , "" ) |
95 | TARGET_BUILTIN(__builtin_ppc_lharx, "ssD*" , "" , "isa-v207-instructions" ) |
96 | TARGET_BUILTIN(__builtin_ppc_lbarx, "ccD*" , "" , "isa-v207-instructions" ) |
97 | BUILTIN(__builtin_ppc_stdcx, "iLiD*Li" , "" ) |
98 | BUILTIN(__builtin_ppc_stwcx, "iiD*i" , "" ) |
99 | TARGET_BUILTIN(__builtin_ppc_sthcx, "isD*s" , "" , "isa-v207-instructions" ) |
100 | TARGET_BUILTIN(__builtin_ppc_stbcx, "icD*i" , "" , "isa-v207-instructions" ) |
101 | BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi" , "" ) |
102 | BUILTIN(__builtin_ppc_tw, "viiIUi" , "" ) |
103 | BUILTIN(__builtin_ppc_trap, "vi" , "" ) |
104 | BUILTIN(__builtin_ppc_trapd, "vLi" , "" ) |
105 | BUILTIN(__builtin_ppc_fcfid, "dd" , "" ) |
106 | BUILTIN(__builtin_ppc_fcfud, "dd" , "" ) |
107 | BUILTIN(__builtin_ppc_fctid, "dd" , "" ) |
108 | BUILTIN(__builtin_ppc_fctidz, "dd" , "" ) |
109 | BUILTIN(__builtin_ppc_fctiw, "dd" , "" ) |
110 | BUILTIN(__builtin_ppc_fctiwz, "dd" , "" ) |
111 | BUILTIN(__builtin_ppc_fctudz, "dd" , "" ) |
112 | BUILTIN(__builtin_ppc_fctuwz, "dd" , "" ) |
113 | |
114 | // fence builtin prevents all instructions moved across it |
115 | BUILTIN(__builtin_ppc_fence, "v" , "" ) |
116 | |
117 | BUILTIN(__builtin_ppc_swdiv_nochk, "ddd" , "" ) |
118 | BUILTIN(__builtin_ppc_swdivs_nochk, "fff" , "" ) |
119 | BUILTIN(__builtin_ppc_alignx, "vIivC*" , "nc" ) |
120 | BUILTIN(__builtin_ppc_rdlam, "UWiUWiUWiUWIi" , "nc" ) |
121 | TARGET_BUILTIN(__builtin_ppc_compare_exp_uo, "idd" , "" , "isa-v30-instructions,vsx" ) |
122 | TARGET_BUILTIN(__builtin_ppc_compare_exp_lt, "idd" , "" , "isa-v30-instructions,vsx" ) |
123 | TARGET_BUILTIN(__builtin_ppc_compare_exp_gt, "idd" , "" , "isa-v30-instructions,vsx" ) |
124 | TARGET_BUILTIN(__builtin_ppc_compare_exp_eq, "idd" , "" , "isa-v30-instructions,vsx" ) |
125 | TARGET_BUILTIN(__builtin_ppc_test_data_class, "idIi" , "t" , "isa-v30-instructions,vsx" ) |
126 | BUILTIN(__builtin_ppc_swdiv, "ddd" , "" ) |
127 | BUILTIN(__builtin_ppc_swdivs, "fff" , "" ) |
128 | // Compare |
129 | TARGET_BUILTIN(__builtin_ppc_cmpeqb, "LLiLLiLLi" , "" , "isa-v30-instructions" ) |
130 | TARGET_BUILTIN(__builtin_ppc_cmprb, "iCIiii" , "" , "isa-v30-instructions" ) |
131 | TARGET_BUILTIN(__builtin_ppc_setb, "LLiLLiLLi" , "" , "isa-v30-instructions" ) |
132 | BUILTIN(__builtin_ppc_cmpb, "LLiLLiLLi" , "" ) |
133 | // Multiply |
134 | BUILTIN(__builtin_ppc_mulhd, "LLiLiLi" , "" ) |
135 | BUILTIN(__builtin_ppc_mulhdu, "ULLiULiULi" , "" ) |
136 | BUILTIN(__builtin_ppc_mulhw, "iii" , "" ) |
137 | BUILTIN(__builtin_ppc_mulhwu, "UiUiUi" , "" ) |
138 | TARGET_BUILTIN(__builtin_ppc_maddhd, "LLiLLiLLiLLi" , "" , "isa-v30-instructions" ) |
139 | TARGET_BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi" , "" , |
140 | "isa-v30-instructions" ) |
141 | TARGET_BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi" , "" , "isa-v30-instructions" ) |
142 | // Rotate |
143 | BUILTIN(__builtin_ppc_rlwnm, "UiUiUiIUi" , "" ) |
144 | BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi" , "" ) |
145 | BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi" , "" ) |
146 | // load |
147 | BUILTIN(__builtin_ppc_load2r, "UsUs*" , "" ) |
148 | BUILTIN(__builtin_ppc_load4r, "UiUi*" , "" ) |
149 | TARGET_BUILTIN(__builtin_ppc_load8r, "ULLiULLi*" , "" , "isa-v206-instructions" ) |
150 | // store |
151 | BUILTIN(__builtin_ppc_store2r, "vUiUs*" , "" ) |
152 | BUILTIN(__builtin_ppc_store4r, "vUiUi*" , "" ) |
153 | TARGET_BUILTIN(__builtin_ppc_store8r, "vULLiULLi*" , "" , "isa-v206-instructions" ) |
154 | TARGET_BUILTIN(__builtin_ppc_extract_exp, "Uid" , "" , "power9-vector" ) |
155 | TARGET_BUILTIN(__builtin_ppc_extract_sig, "ULLid" , "" , "power9-vector" ) |
156 | BUILTIN(__builtin_ppc_mtfsb0, "vUIi" , "" ) |
157 | BUILTIN(__builtin_ppc_mtfsb1, "vUIi" , "" ) |
158 | BUILTIN(__builtin_ppc_mffs, "d" , "" ) |
159 | TARGET_BUILTIN(__builtin_ppc_mffsl, "d" , "" , "isa-v30-instructions" ) |
160 | BUILTIN(__builtin_ppc_mtfsf, "vUIiUi" , "" ) |
161 | BUILTIN(__builtin_ppc_mtfsfi, "vUIiUIi" , "" ) |
162 | BUILTIN(__builtin_ppc_set_fpscr_rn, "di" , "" ) |
163 | TARGET_BUILTIN(__builtin_ppc_insert_exp, "ddULLi" , "" , "power9-vector" ) |
164 | BUILTIN(__builtin_ppc_fmsub, "dddd" , "" ) |
165 | BUILTIN(__builtin_ppc_fmsubs, "ffff" , "" ) |
166 | BUILTIN(__builtin_ppc_fnmadd, "dddd" , "" ) |
167 | BUILTIN(__builtin_ppc_fnmadds, "ffff" , "" ) |
168 | BUILTIN(__builtin_ppc_fnmsub, "dddd" , "" ) |
169 | BUILTIN(__builtin_ppc_fnmsubs, "ffff" , "" ) |
170 | BUILTIN(__builtin_ppc_fre, "dd" , "" ) |
171 | BUILTIN(__builtin_ppc_fres, "ff" , "" ) |
172 | BUILTIN(__builtin_ppc_dcbtstt, "vv*" , "" ) |
173 | BUILTIN(__builtin_ppc_dcbtt, "vv*" , "" ) |
174 | BUILTIN(__builtin_ppc_mftbu, "Ui" , "" ) |
175 | BUILTIN(__builtin_ppc_mfmsr, "Ui" , "" ) |
176 | BUILTIN(__builtin_ppc_mfspr, "ULiIi" , "" ) |
177 | BUILTIN(__builtin_ppc_mtmsr, "vUi" , "" ) |
178 | BUILTIN(__builtin_ppc_mtspr, "vIiULi" , "" ) |
179 | BUILTIN(__builtin_ppc_stfiw, "viC*d" , "" ) |
180 | TARGET_BUILTIN(__builtin_ppc_addex, "LLiLLiLLiCIi" , "" , "isa-v30-instructions" ) |
181 | // select |
182 | BUILTIN(__builtin_ppc_maxfe, "LdLdLdLd." , "t" ) |
183 | BUILTIN(__builtin_ppc_maxfl, "dddd." , "t" ) |
184 | BUILTIN(__builtin_ppc_maxfs, "ffff." , "t" ) |
185 | BUILTIN(__builtin_ppc_minfe, "LdLdLdLd." , "t" ) |
186 | BUILTIN(__builtin_ppc_minfl, "dddd." , "t" ) |
187 | BUILTIN(__builtin_ppc_minfs, "ffff." , "t" ) |
188 | // Floating Negative Absolute Value |
189 | BUILTIN(__builtin_ppc_fnabs, "dd" , "" ) |
190 | BUILTIN(__builtin_ppc_fnabss, "ff" , "" ) |
191 | |
192 | BUILTIN(__builtin_ppc_get_timebase, "ULLi" , "n" ) |
193 | |
194 | // This is just a placeholder, the types and attributes are wrong. |
195 | TARGET_BUILTIN(__builtin_altivec_vaddcuw, "V4UiV4UiV4Ui" , "" , "altivec" ) |
196 | |
197 | TARGET_BUILTIN(__builtin_altivec_vaddsbs, "V16ScV16ScV16Sc" , "" , "altivec" ) |
198 | TARGET_BUILTIN(__builtin_altivec_vaddubs, "V16UcV16UcV16Uc" , "" , "altivec" ) |
199 | TARGET_BUILTIN(__builtin_altivec_vaddshs, "V8SsV8SsV8Ss" , "" , "altivec" ) |
200 | TARGET_BUILTIN(__builtin_altivec_vadduhs, "V8UsV8UsV8Us" , "" , "altivec" ) |
201 | TARGET_BUILTIN(__builtin_altivec_vaddsws, "V4SiV4SiV4Si" , "" , "altivec" ) |
202 | TARGET_BUILTIN(__builtin_altivec_vadduws, "V4UiV4UiV4Ui" , "" , "altivec" ) |
203 | TARGET_BUILTIN(__builtin_altivec_vaddeuqm, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi" , "" , |
204 | "power8-vector" ) |
205 | TARGET_BUILTIN(__builtin_altivec_vaddcuq, "V1ULLLiV1ULLLiV1ULLLi" , "" , |
206 | "power8-vector" ) |
207 | TARGET_BUILTIN(__builtin_altivec_vaddecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi" , "" , |
208 | "power8-vector" ) |
209 | TARGET_BUILTIN(__builtin_altivec_vadduqm, "V1ULLLiV16UcV16Uc" , "" , |
210 | "power8-vector" ) |
211 | TARGET_BUILTIN(__builtin_altivec_vaddeuqm_c, "V16UcV16UcV16UcV16Uc" , "" , |
212 | "power8-vector" ) |
213 | TARGET_BUILTIN(__builtin_altivec_vaddcuq_c, "V16UcV16UcV16Uc" , "" , |
214 | "power8-vector" ) |
215 | TARGET_BUILTIN(__builtin_altivec_vaddecuq_c, "V16UcV16UcV16UcV16Uc" , "" , |
216 | "power8-vector" ) |
217 | |
218 | TARGET_BUILTIN(__builtin_altivec_vsubsbs, "V16ScV16ScV16Sc" , "" , "altivec" ) |
219 | TARGET_BUILTIN(__builtin_altivec_vsububs, "V16UcV16UcV16Uc" , "" , "altivec" ) |
220 | TARGET_BUILTIN(__builtin_altivec_vsubshs, "V8SsV8SsV8Ss" , "" , "altivec" ) |
221 | TARGET_BUILTIN(__builtin_altivec_vsubuhs, "V8UsV8UsV8Us" , "" , "altivec" ) |
222 | TARGET_BUILTIN(__builtin_altivec_vsubsws, "V4SiV4SiV4Si" , "" , "altivec" ) |
223 | TARGET_BUILTIN(__builtin_altivec_vsubuws, "V4UiV4UiV4Ui" , "" , "altivec" ) |
224 | TARGET_BUILTIN(__builtin_altivec_vsubeuqm, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi" , "" , |
225 | "power8-vector" ) |
226 | TARGET_BUILTIN(__builtin_altivec_vsubcuq, "V1ULLLiV1ULLLiV1ULLLi" , "" , |
227 | "power8-vector" ) |
228 | TARGET_BUILTIN(__builtin_altivec_vsubecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi" , "" , |
229 | "power8-vector" ) |
230 | TARGET_BUILTIN(__builtin_altivec_vsubuqm, "V1ULLLiV16UcV16Uc" , "" , |
231 | "power8-vector" ) |
232 | TARGET_BUILTIN(__builtin_altivec_vsubeuqm_c, "V16UcV16UcV16UcV16Uc" , "" , |
233 | "power8-vector" ) |
234 | TARGET_BUILTIN(__builtin_altivec_vsubcuq_c, "V16UcV16UcV16Uc" , "" , |
235 | "power8-vector" ) |
236 | TARGET_BUILTIN(__builtin_altivec_vsubecuq_c, "V16UcV16UcV16UcV16Uc" , "" , |
237 | "power8-vector" ) |
238 | |
239 | TARGET_BUILTIN(__builtin_altivec_vavgsb, "V16ScV16ScV16Sc" , "" , "altivec" ) |
240 | TARGET_BUILTIN(__builtin_altivec_vavgub, "V16UcV16UcV16Uc" , "" , "altivec" ) |
241 | TARGET_BUILTIN(__builtin_altivec_vavgsh, "V8SsV8SsV8Ss" , "" , "altivec" ) |
242 | TARGET_BUILTIN(__builtin_altivec_vavguh, "V8UsV8UsV8Us" , "" , "altivec" ) |
243 | TARGET_BUILTIN(__builtin_altivec_vavgsw, "V4SiV4SiV4Si" , "" , "altivec" ) |
244 | TARGET_BUILTIN(__builtin_altivec_vavguw, "V4UiV4UiV4Ui" , "" , "altivec" ) |
245 | |
246 | TARGET_BUILTIN(__builtin_altivec_vrfip, "V4fV4f" , "" , "altivec" ) |
247 | |
248 | TARGET_BUILTIN(__builtin_altivec_vcfsx, "V4fV4SiIi" , "" , "altivec" ) |
249 | TARGET_BUILTIN(__builtin_altivec_vcfux, "V4fV4UiIi" , "" , "altivec" ) |
250 | TARGET_BUILTIN(__builtin_altivec_vctsxs, "V4SiV4fIi" , "" , "altivec" ) |
251 | TARGET_BUILTIN(__builtin_altivec_vctuxs, "V4UiV4fIi" , "" , "altivec" ) |
252 | |
253 | TARGET_BUILTIN(__builtin_altivec_dss, "vUIi" , "" , "altivec" ) |
254 | TARGET_BUILTIN(__builtin_altivec_dssall, "v" , "" , "altivec" ) |
255 | TARGET_BUILTIN(__builtin_altivec_dst, "vvC*iUIi" , "" , "altivec" ) |
256 | TARGET_BUILTIN(__builtin_altivec_dstt, "vvC*iUIi" , "" , "altivec" ) |
257 | TARGET_BUILTIN(__builtin_altivec_dstst, "vvC*iUIi" , "" , "altivec" ) |
258 | TARGET_BUILTIN(__builtin_altivec_dststt, "vvC*iUIi" , "" , "altivec" ) |
259 | |
260 | TARGET_BUILTIN(__builtin_altivec_vexptefp, "V4fV4f" , "" , "altivec" ) |
261 | |
262 | TARGET_BUILTIN(__builtin_altivec_vrfim, "V4fV4f" , "" , "altivec" ) |
263 | |
264 | TARGET_BUILTIN(__builtin_altivec_lvx, "V4iLivC*" , "" , "altivec" ) |
265 | TARGET_BUILTIN(__builtin_altivec_lvxl, "V4iLivC*" , "" , "altivec" ) |
266 | TARGET_BUILTIN(__builtin_altivec_lvebx, "V16cLivC*" , "" , "altivec" ) |
267 | TARGET_BUILTIN(__builtin_altivec_lvehx, "V8sLivC*" , "" , "altivec" ) |
268 | TARGET_BUILTIN(__builtin_altivec_lvewx, "V4iLivC*" , "" , "altivec" ) |
269 | |
270 | TARGET_BUILTIN(__builtin_altivec_vlogefp, "V4fV4f" , "" , "altivec" ) |
271 | |
272 | TARGET_BUILTIN(__builtin_altivec_lvsl, "V16cUcvC*" , "" , "altivec" ) |
273 | TARGET_BUILTIN(__builtin_altivec_lvsr, "V16cUcvC*" , "" , "altivec" ) |
274 | |
275 | TARGET_BUILTIN(__builtin_altivec_vmaddfp, "V4fV4fV4fV4f" , "" , "altivec" ) |
276 | TARGET_BUILTIN(__builtin_altivec_vmhaddshs, "V8sV8sV8sV8s" , "" , "altivec" ) |
277 | TARGET_BUILTIN(__builtin_altivec_vmhraddshs, "V8sV8sV8sV8s" , "" , "altivec" ) |
278 | |
279 | TARGET_BUILTIN(__builtin_altivec_vmsumubm, "V4UiV16UcV16UcV4Ui" , "" , "altivec" ) |
280 | TARGET_BUILTIN(__builtin_altivec_vmsummbm, "V4SiV16ScV16UcV4Si" , "" , "altivec" ) |
281 | TARGET_BUILTIN(__builtin_altivec_vmsumuhm, "V4UiV8UsV8UsV4Ui" , "" , "altivec" ) |
282 | TARGET_BUILTIN(__builtin_altivec_vmsumshm, "V4SiV8SsV8SsV4Si" , "" , "altivec" ) |
283 | TARGET_BUILTIN(__builtin_altivec_vmsumuhs, "V4UiV8UsV8UsV4Ui" , "" , "altivec" ) |
284 | TARGET_BUILTIN(__builtin_altivec_vmsumshs, "V4SiV8SsV8SsV4Si" , "" , "altivec" ) |
285 | |
286 | TARGET_BUILTIN(__builtin_altivec_vmuleub, "V8UsV16UcV16Uc" , "" , "altivec" ) |
287 | TARGET_BUILTIN(__builtin_altivec_vmulesb, "V8SsV16ScV16Sc" , "" , "altivec" ) |
288 | TARGET_BUILTIN(__builtin_altivec_vmuleuh, "V4UiV8UsV8Us" , "" , "altivec" ) |
289 | TARGET_BUILTIN(__builtin_altivec_vmulesh, "V4SiV8SsV8Ss" , "" , "altivec" ) |
290 | TARGET_BUILTIN(__builtin_altivec_vmuleuw, "V2ULLiV4UiV4Ui" , "" , "power8-vector" ) |
291 | TARGET_BUILTIN(__builtin_altivec_vmulesw, "V2SLLiV4SiV4Si" , "" , "power8-vector" ) |
292 | TARGET_BUILTIN(__builtin_altivec_vmuloub, "V8UsV16UcV16Uc" , "" , "altivec" ) |
293 | TARGET_BUILTIN(__builtin_altivec_vmulosb, "V8SsV16ScV16Sc" , "" , "altivec" ) |
294 | TARGET_BUILTIN(__builtin_altivec_vmulouh, "V4UiV8UsV8Us" , "" , "altivec" ) |
295 | TARGET_BUILTIN(__builtin_altivec_vmulosh, "V4SiV8SsV8Ss" , "" , "altivec" ) |
296 | TARGET_BUILTIN(__builtin_altivec_vmulouw, "V2ULLiV4UiV4Ui" , "" , "power8-vector" ) |
297 | TARGET_BUILTIN(__builtin_altivec_vmulosw, "V2SLLiV4SiV4Si" , "" , "power8-vector" ) |
298 | TARGET_BUILTIN(__builtin_altivec_vmuleud, "V1ULLLiV2ULLiV2ULLi" , "" , |
299 | "power10-vector" ) |
300 | TARGET_BUILTIN(__builtin_altivec_vmulesd, "V1SLLLiV2SLLiV2SLLi" , "" , |
301 | "power10-vector" ) |
302 | TARGET_BUILTIN(__builtin_altivec_vmuloud, "V1ULLLiV2ULLiV2ULLi" , "" , |
303 | "power10-vector" ) |
304 | TARGET_BUILTIN(__builtin_altivec_vmulosd, "V1SLLLiV2SLLiV2SLLi" , "" , |
305 | "power10-vector" ) |
306 | TARGET_BUILTIN(__builtin_altivec_vmsumcud, "V1ULLLiV2ULLiV2ULLiV1ULLLi" , "" , |
307 | "power10-vector" ) |
308 | |
309 | TARGET_BUILTIN(__builtin_altivec_vnmsubfp, "V4fV4fV4fV4f" , "" , "altivec" ) |
310 | |
311 | TARGET_BUILTIN(__builtin_altivec_vpkpx, "V8sV4UiV4Ui" , "" , "altivec" ) |
312 | TARGET_BUILTIN(__builtin_altivec_vpkuhus, "V16UcV8UsV8Us" , "" , "altivec" ) |
313 | TARGET_BUILTIN(__builtin_altivec_vpkshss, "V16ScV8SsV8Ss" , "" , "altivec" ) |
314 | TARGET_BUILTIN(__builtin_altivec_vpkuwus, "V8UsV4UiV4Ui" , "" , "altivec" ) |
315 | TARGET_BUILTIN(__builtin_altivec_vpkswss, "V8SsV4SiV4Si" , "" , "altivec" ) |
316 | TARGET_BUILTIN(__builtin_altivec_vpkshus, "V16UcV8SsV8Ss" , "" , "altivec" ) |
317 | TARGET_BUILTIN(__builtin_altivec_vpkswus, "V8UsV4SiV4Si" , "" , "altivec" ) |
318 | TARGET_BUILTIN(__builtin_altivec_vpksdss, "V4SiV2SLLiV2SLLi" , "" , |
319 | "power8-vector" ) |
320 | TARGET_BUILTIN(__builtin_altivec_vpksdus, "V4UiV2SLLiV2SLLi" , "" , |
321 | "power8-vector" ) |
322 | TARGET_BUILTIN(__builtin_altivec_vpkudus, "V4UiV2ULLiV2ULLi" , "" , |
323 | "power8-vector" ) |
324 | TARGET_BUILTIN(__builtin_altivec_vpkudum, "V4UiV2ULLiV2ULLi" , "" , |
325 | "power8-vector" ) |
326 | |
327 | TARGET_BUILTIN(__builtin_altivec_vperm_4si, "V4iV4iV4iV16Uc" , "" , "altivec" ) |
328 | |
329 | TARGET_BUILTIN(__builtin_altivec_stvx, "vV4iLiv*" , "" , "altivec" ) |
330 | TARGET_BUILTIN(__builtin_altivec_stvxl, "vV4iLiv*" , "" , "altivec" ) |
331 | TARGET_BUILTIN(__builtin_altivec_stvebx, "vV16cLiv*" , "" , "altivec" ) |
332 | TARGET_BUILTIN(__builtin_altivec_stvehx, "vV8sLiv*" , "" , "altivec" ) |
333 | TARGET_BUILTIN(__builtin_altivec_stvewx, "vV4iLiv*" , "" , "altivec" ) |
334 | |
335 | TARGET_BUILTIN(__builtin_altivec_vcmpbfp, "V4iV4fV4f" , "" , "altivec" ) |
336 | |
337 | TARGET_BUILTIN(__builtin_altivec_vcmpgefp, "V4iV4fV4f" , "" , "altivec" ) |
338 | |
339 | TARGET_BUILTIN(__builtin_altivec_vcmpequb, "V16cV16cV16c" , "" , "altivec" ) |
340 | TARGET_BUILTIN(__builtin_altivec_vcmpequh, "V8sV8sV8s" , "" , "altivec" ) |
341 | TARGET_BUILTIN(__builtin_altivec_vcmpequw, "V4iV4iV4i" , "" , "altivec" ) |
342 | TARGET_BUILTIN(__builtin_altivec_vcmpequd, "V2LLiV2LLiV2LLi" , "" , |
343 | "power8-vector" ) |
344 | TARGET_BUILTIN(__builtin_altivec_vcmpeqfp, "V4iV4fV4f" , "" , "altivec" ) |
345 | |
346 | TARGET_BUILTIN(__builtin_altivec_vcmpneb, "V16cV16cV16c" , "" , "power9-vector" ) |
347 | TARGET_BUILTIN(__builtin_altivec_vcmpneh, "V8sV8sV8s" , "" , "power9-vector" ) |
348 | TARGET_BUILTIN(__builtin_altivec_vcmpnew, "V4iV4iV4i" , "" , "power9-vector" ) |
349 | |
350 | TARGET_BUILTIN(__builtin_altivec_vcmpnezb, "V16cV16cV16c" , "" , "power9-vector" ) |
351 | TARGET_BUILTIN(__builtin_altivec_vcmpnezh, "V8sV8sV8s" , "" , "power9-vector" ) |
352 | TARGET_BUILTIN(__builtin_altivec_vcmpnezw, "V4iV4iV4i" , "" , "power9-vector" ) |
353 | |
354 | TARGET_BUILTIN(__builtin_altivec_vcmpgtsb, "V16cV16ScV16Sc" , "" , "altivec" ) |
355 | TARGET_BUILTIN(__builtin_altivec_vcmpgtub, "V16cV16UcV16Uc" , "" , "altivec" ) |
356 | TARGET_BUILTIN(__builtin_altivec_vcmpgtsh, "V8sV8SsV8Ss" , "" , "altivec" ) |
357 | TARGET_BUILTIN(__builtin_altivec_vcmpgtuh, "V8sV8UsV8Us" , "" , "altivec" ) |
358 | TARGET_BUILTIN(__builtin_altivec_vcmpgtsw, "V4iV4SiV4Si" , "" , "altivec" ) |
359 | TARGET_BUILTIN(__builtin_altivec_vcmpgtuw, "V4iV4UiV4Ui" , "" , "altivec" ) |
360 | TARGET_BUILTIN(__builtin_altivec_vcmpgtsd, "V2LLiV2LLiV2LLi" , "" , |
361 | "power8-vector" ) |
362 | TARGET_BUILTIN(__builtin_altivec_vcmpgtud, "V2LLiV2ULLiV2ULLi" , "" , |
363 | "power8-vector" ) |
364 | TARGET_BUILTIN(__builtin_altivec_vcmpgtfp, "V4iV4fV4f" , "" , "altivec" ) |
365 | |
366 | // P10 Vector compare builtins. |
367 | TARGET_BUILTIN(__builtin_altivec_vcmpequq, "V1LLLiV1ULLLiV1ULLLi" , "" , |
368 | "power10-vector" ) |
369 | TARGET_BUILTIN(__builtin_altivec_vcmpgtsq, "V1LLLiV1SLLLiV1SLLLi" , "" , |
370 | "power10-vector" ) |
371 | TARGET_BUILTIN(__builtin_altivec_vcmpgtuq, "V1LLLiV1ULLLiV1ULLLi" , "" , |
372 | "power10-vector" ) |
373 | TARGET_BUILTIN(__builtin_altivec_vcmpequq_p, "iiV1ULLLiV1LLLi" , "" , "altivec" ) |
374 | TARGET_BUILTIN(__builtin_altivec_vcmpgtsq_p, "iiV1SLLLiV1SLLLi" , "" , |
375 | "power10-vector" ) |
376 | TARGET_BUILTIN(__builtin_altivec_vcmpgtuq_p, "iiV1ULLLiV1ULLLi" , "" , |
377 | "power10-vector" ) |
378 | |
379 | TARGET_BUILTIN(__builtin_altivec_vmaxsb, "V16ScV16ScV16Sc" , "" , "altivec" ) |
380 | TARGET_BUILTIN(__builtin_altivec_vmaxub, "V16UcV16UcV16Uc" , "" , "altivec" ) |
381 | TARGET_BUILTIN(__builtin_altivec_vmaxsh, "V8SsV8SsV8Ss" , "" , "altivec" ) |
382 | TARGET_BUILTIN(__builtin_altivec_vmaxuh, "V8UsV8UsV8Us" , "" , "altivec" ) |
383 | TARGET_BUILTIN(__builtin_altivec_vmaxsw, "V4SiV4SiV4Si" , "" , "altivec" ) |
384 | TARGET_BUILTIN(__builtin_altivec_vmaxuw, "V4UiV4UiV4Ui" , "" , "altivec" ) |
385 | TARGET_BUILTIN(__builtin_altivec_vmaxsd, "V2LLiV2LLiV2LLi" , "" , "power8-vector" ) |
386 | TARGET_BUILTIN(__builtin_altivec_vmaxud, "V2ULLiV2ULLiV2ULLi" , "" , |
387 | "power8-vector" ) |
388 | TARGET_BUILTIN(__builtin_altivec_vmaxfp, "V4fV4fV4f" , "" , "altivec" ) |
389 | |
390 | TARGET_BUILTIN(__builtin_altivec_mfvscr, "V8Us" , "" , "altivec" ) |
391 | |
392 | TARGET_BUILTIN(__builtin_altivec_vminsb, "V16ScV16ScV16Sc" , "" , "altivec" ) |
393 | TARGET_BUILTIN(__builtin_altivec_vminub, "V16UcV16UcV16Uc" , "" , "altivec" ) |
394 | TARGET_BUILTIN(__builtin_altivec_vminsh, "V8SsV8SsV8Ss" , "" , "altivec" ) |
395 | TARGET_BUILTIN(__builtin_altivec_vminuh, "V8UsV8UsV8Us" , "" , "altivec" ) |
396 | TARGET_BUILTIN(__builtin_altivec_vminsw, "V4SiV4SiV4Si" , "" , "altivec" ) |
397 | TARGET_BUILTIN(__builtin_altivec_vminuw, "V4UiV4UiV4Ui" , "" , "altivec" ) |
398 | TARGET_BUILTIN(__builtin_altivec_vminsd, "V2LLiV2LLiV2LLi" , "" , "power8-vector" ) |
399 | TARGET_BUILTIN(__builtin_altivec_vminud, "V2ULLiV2ULLiV2ULLi" , "" , |
400 | "power8-vector" ) |
401 | TARGET_BUILTIN(__builtin_altivec_vminfp, "V4fV4fV4f" , "" , "altivec" ) |
402 | |
403 | TARGET_BUILTIN(__builtin_altivec_mtvscr, "vV4i" , "" , "altivec" ) |
404 | |
405 | TARGET_BUILTIN(__builtin_altivec_vrefp, "V4fV4f" , "" , "altivec" ) |
406 | |
407 | TARGET_BUILTIN(__builtin_altivec_vrlb, "V16cV16cV16Uc" , "" , "altivec" ) |
408 | TARGET_BUILTIN(__builtin_altivec_vrlh, "V8sV8sV8Us" , "" , "altivec" ) |
409 | TARGET_BUILTIN(__builtin_altivec_vrlw, "V4iV4iV4Ui" , "" , "altivec" ) |
410 | TARGET_BUILTIN(__builtin_altivec_vrld, "V2LLiV2LLiV2ULLi" , "" , "power8-vector" ) |
411 | |
412 | TARGET_BUILTIN(__builtin_altivec_vsel_4si, "V4iV4iV4iV4Ui" , "" , "altivec" ) |
413 | |
414 | TARGET_BUILTIN(__builtin_altivec_vsl, "V4iV4iV4i" , "" , "altivec" ) |
415 | TARGET_BUILTIN(__builtin_altivec_vslo, "V4iV4iV4i" , "" , "altivec" ) |
416 | |
417 | TARGET_BUILTIN(__builtin_altivec_vsrab, "V16cV16cV16Uc" , "" , "altivec" ) |
418 | TARGET_BUILTIN(__builtin_altivec_vsrah, "V8sV8sV8Us" , "" , "altivec" ) |
419 | TARGET_BUILTIN(__builtin_altivec_vsraw, "V4iV4iV4Ui" , "" , "altivec" ) |
420 | |
421 | TARGET_BUILTIN(__builtin_altivec_vsr, "V4iV4iV4i" , "" , "altivec" ) |
422 | TARGET_BUILTIN(__builtin_altivec_vsro, "V4iV4iV4i" , "" , "altivec" ) |
423 | |
424 | TARGET_BUILTIN(__builtin_altivec_vrfin, "V4fV4f" , "" , "altivec" ) |
425 | |
426 | TARGET_BUILTIN(__builtin_altivec_vrsqrtefp, "V4fV4f" , "" , "altivec" ) |
427 | |
428 | TARGET_BUILTIN(__builtin_altivec_vsubcuw, "V4UiV4UiV4Ui" , "" , "altivec" ) |
429 | |
430 | TARGET_BUILTIN(__builtin_altivec_vsum4sbs, "V4SiV16ScV4Si" , "" , "altivec" ) |
431 | TARGET_BUILTIN(__builtin_altivec_vsum4ubs, "V4UiV16UcV4Ui" , "" , "altivec" ) |
432 | TARGET_BUILTIN(__builtin_altivec_vsum4shs, "V4SiV8SsV4Si" , "" , "altivec" ) |
433 | |
434 | TARGET_BUILTIN(__builtin_altivec_vsum2sws, "V4SiV4SiV4Si" , "" , "altivec" ) |
435 | |
436 | TARGET_BUILTIN(__builtin_altivec_vsumsws, "V4SiV4SiV4Si" , "" , "altivec" ) |
437 | |
438 | TARGET_BUILTIN(__builtin_altivec_vrfiz, "V4fV4f" , "" , "altivec" ) |
439 | |
440 | TARGET_BUILTIN(__builtin_altivec_vupkhsb, "V8sV16c" , "" , "altivec" ) |
441 | TARGET_BUILTIN(__builtin_altivec_vupkhpx, "V4UiV8s" , "" , "altivec" ) |
442 | TARGET_BUILTIN(__builtin_altivec_vupkhsh, "V4iV8s" , "" , "altivec" ) |
443 | TARGET_BUILTIN(__builtin_altivec_vupkhsw, "V2LLiV4i" , "" , "power8-vector" ) |
444 | |
445 | TARGET_BUILTIN(__builtin_altivec_vupklsb, "V8sV16c" , "" , "altivec" ) |
446 | TARGET_BUILTIN(__builtin_altivec_vupklpx, "V4UiV8s" , "" , "altivec" ) |
447 | TARGET_BUILTIN(__builtin_altivec_vupklsh, "V4iV8s" , "" , "altivec" ) |
448 | TARGET_BUILTIN(__builtin_altivec_vupklsw, "V2LLiV4i" , "" , "power8-vector" ) |
449 | |
450 | TARGET_BUILTIN(__builtin_altivec_vcmpbfp_p, "iiV4fV4f" , "" , "altivec" ) |
451 | |
452 | TARGET_BUILTIN(__builtin_altivec_vcmpgefp_p, "iiV4fV4f" , "" , "altivec" ) |
453 | |
454 | TARGET_BUILTIN(__builtin_altivec_vcmpequb_p, "iiV16cV16c" , "" , "altivec" ) |
455 | TARGET_BUILTIN(__builtin_altivec_vcmpequh_p, "iiV8sV8s" , "" , "altivec" ) |
456 | TARGET_BUILTIN(__builtin_altivec_vcmpequw_p, "iiV4iV4i" , "" , "altivec" ) |
457 | TARGET_BUILTIN(__builtin_altivec_vcmpequd_p, "iiV2LLiV2LLi" , "" , "vsx" ) |
458 | TARGET_BUILTIN(__builtin_altivec_vcmpeqfp_p, "iiV4fV4f" , "" , "altivec" ) |
459 | |
460 | TARGET_BUILTIN(__builtin_altivec_vcmpneb_p, "iiV16cV16c" , "" , "power9-vector" ) |
461 | TARGET_BUILTIN(__builtin_altivec_vcmpneh_p, "iiV8sV8s" , "" , "power9-vector" ) |
462 | TARGET_BUILTIN(__builtin_altivec_vcmpnew_p, "iiV4iV4i" , "" , "power9-vector" ) |
463 | TARGET_BUILTIN(__builtin_altivec_vcmpned_p, "iiV2LLiV2LLi" , "" , "vsx" ) |
464 | |
465 | TARGET_BUILTIN(__builtin_altivec_vcmpgtsb_p, "iiV16ScV16Sc" , "" , "altivec" ) |
466 | TARGET_BUILTIN(__builtin_altivec_vcmpgtub_p, "iiV16UcV16Uc" , "" , "altivec" ) |
467 | TARGET_BUILTIN(__builtin_altivec_vcmpgtsh_p, "iiV8SsV8Ss" , "" , "altivec" ) |
468 | TARGET_BUILTIN(__builtin_altivec_vcmpgtuh_p, "iiV8UsV8Us" , "" , "altivec" ) |
469 | TARGET_BUILTIN(__builtin_altivec_vcmpgtsw_p, "iiV4SiV4Si" , "" , "altivec" ) |
470 | TARGET_BUILTIN(__builtin_altivec_vcmpgtuw_p, "iiV4UiV4Ui" , "" , "altivec" ) |
471 | TARGET_BUILTIN(__builtin_altivec_vcmpgtsd_p, "iiV2LLiV2LLi" , "" , "vsx" ) |
472 | TARGET_BUILTIN(__builtin_altivec_vcmpgtud_p, "iiV2ULLiV2ULLi" , "" , "vsx" ) |
473 | TARGET_BUILTIN(__builtin_altivec_vcmpgtfp_p, "iiV4fV4f" , "" , "altivec" ) |
474 | |
475 | TARGET_BUILTIN(__builtin_altivec_vgbbd, "V16UcV16Uc" , "" , "power8-vector" ) |
476 | TARGET_BUILTIN(__builtin_altivec_vbpermq, "V2ULLiV16UcV16Uc" , "" , |
477 | "power8-vector" ) |
478 | TARGET_BUILTIN(__builtin_altivec_vbpermd, "V2ULLiV2ULLiV16Uc" , "" , |
479 | "power9-vector" ) |
480 | |
481 | // P8 Crypto built-ins. |
482 | TARGET_BUILTIN(__builtin_altivec_crypto_vsbox, "V16UcV16Uc" , "" , |
483 | "power8-vector" ) |
484 | TARGET_BUILTIN(__builtin_altivec_crypto_vpermxor, "V16UcV16UcV16UcV16Uc" , "" , |
485 | "power8-vector" ) |
486 | TARGET_BUILTIN(__builtin_altivec_crypto_vpermxor_be, "V16UcV16UcV16UcV16Uc" , "" , |
487 | "power8-vector" ) |
488 | TARGET_BUILTIN(__builtin_altivec_crypto_vshasigmaw, "V4UiV4UiIiIi" , "" , |
489 | "power8-vector" ) |
490 | TARGET_BUILTIN(__builtin_altivec_crypto_vshasigmad, "V2ULLiV2ULLiIiIi" , "" , |
491 | "power8-vector" ) |
492 | TARGET_BUILTIN(__builtin_altivec_crypto_vcipher, "V16UcV16UcV16Uc" , "" , |
493 | "power8-vector" ) |
494 | TARGET_BUILTIN(__builtin_altivec_crypto_vcipherlast, "V16UcV16UcV16Uc" , "" , |
495 | "power8-vector" ) |
496 | TARGET_BUILTIN(__builtin_altivec_crypto_vncipher, "V16UcV16UcV16Uc" , "" , |
497 | "power8-vector" ) |
498 | TARGET_BUILTIN(__builtin_altivec_crypto_vncipherlast, "V16UcV16UcV16Uc" , "" , |
499 | "power8-vector" ) |
500 | TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumb, "V16UcV16UcV16Uc" , "" , |
501 | "power8-vector" ) |
502 | TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumh, "V8UsV8UsV8Us" , "" , |
503 | "power8-vector" ) |
504 | TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumw, "V4UiV4UiV4Ui" , "" , |
505 | "power8-vector" ) |
506 | TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumd, "V2ULLiV2ULLiV2ULLi" , "" , |
507 | "power8-vector" ) |
508 | |
509 | TARGET_BUILTIN(__builtin_altivec_vclzb, "V16UcV16Uc" , "" , "power8-vector" ) |
510 | TARGET_BUILTIN(__builtin_altivec_vclzh, "V8UsV8Us" , "" , "power8-vector" ) |
511 | TARGET_BUILTIN(__builtin_altivec_vclzw, "V4UiV4Ui" , "" , "power8-vector" ) |
512 | TARGET_BUILTIN(__builtin_altivec_vclzd, "V2ULLiV2ULLi" , "" , "power8-vector" ) |
513 | TARGET_BUILTIN(__builtin_altivec_vctzb, "V16UcV16Uc" , "" , "power9-vector" ) |
514 | TARGET_BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us" , "" , "power9-vector" ) |
515 | TARGET_BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui" , "" , "power9-vector" ) |
516 | TARGET_BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi" , "" , "power9-vector" ) |
517 | |
518 | // P8 BCD builtins. |
519 | TARGET_BUILTIN(__builtin_ppc_bcdadd, "V16UcV16UcV16UcIi" , "" , |
520 | "isa-v207-instructions" ) |
521 | TARGET_BUILTIN(__builtin_ppc_bcdsub, "V16UcV16UcV16UcIi" , "" , |
522 | "isa-v207-instructions" ) |
523 | TARGET_BUILTIN(__builtin_ppc_bcdadd_p, "iiV16UcV16Uc" , "" , |
524 | "isa-v207-instructions" ) |
525 | TARGET_BUILTIN(__builtin_ppc_bcdsub_p, "iiV16UcV16Uc" , "" , |
526 | "isa-v207-instructions" ) |
527 | |
528 | TARGET_BUILTIN(__builtin_altivec_vclzlsbb, "SiV16Uc" , "" , "power9-vector" ) |
529 | TARGET_BUILTIN(__builtin_altivec_vctzlsbb, "SiV16Uc" , "" , "power9-vector" ) |
530 | TARGET_BUILTIN(__builtin_altivec_vprtybw, "V4UiV4Ui" , "" , "power9-vector" ) |
531 | TARGET_BUILTIN(__builtin_altivec_vprtybd, "V2ULLiV2ULLi" , "" , "power9-vector" ) |
532 | TARGET_BUILTIN(__builtin_altivec_vprtybq, "V1ULLLiV1ULLLi" , "" , "power9-vector" ) |
533 | |
534 | // Vector population count built-ins |
535 | TARGET_BUILTIN(__builtin_altivec_vpopcntb, "V16UcV16Uc" , "" , "power8-vector" ) |
536 | TARGET_BUILTIN(__builtin_altivec_vpopcnth, "V8UsV8Us" , "" , "power8-vector" ) |
537 | TARGET_BUILTIN(__builtin_altivec_vpopcntw, "V4UiV4Ui" , "" , "power8-vector" ) |
538 | TARGET_BUILTIN(__builtin_altivec_vpopcntd, "V2ULLiV2ULLi" , "" , "power8-vector" ) |
539 | |
540 | // Absolute difference built-ins |
541 | TARGET_BUILTIN(__builtin_altivec_vabsdub, "V16UcV16UcV16Uc" , "" , |
542 | "power9-vector" ) |
543 | TARGET_BUILTIN(__builtin_altivec_vabsduh, "V8UsV8UsV8Us" , "" , "power9-vector" ) |
544 | TARGET_BUILTIN(__builtin_altivec_vabsduw, "V4UiV4UiV4Ui" , "" , "power9-vector" ) |
545 | |
546 | // P9 Shift built-ins. |
547 | TARGET_BUILTIN(__builtin_altivec_vslv, "V16UcV16UcV16Uc" , "" , "power9-vector" ) |
548 | TARGET_BUILTIN(__builtin_altivec_vsrv, "V16UcV16UcV16Uc" , "" , "power9-vector" ) |
549 | |
550 | // P9 Vector rotate built-ins |
551 | TARGET_BUILTIN(__builtin_altivec_vrlwmi, "V4UiV4UiV4UiV4Ui" , "" , |
552 | "power9-vector" ) |
553 | TARGET_BUILTIN(__builtin_altivec_vrldmi, "V2ULLiV2ULLiV2ULLiV2ULLi" , "" , |
554 | "power9-vector" ) |
555 | TARGET_BUILTIN(__builtin_altivec_vrlwnm, "V4UiV4UiV4Ui" , "" , "power9-vector" ) |
556 | TARGET_BUILTIN(__builtin_altivec_vrldnm, "V2ULLiV2ULLiV2ULLi" , "" , |
557 | "power9-vector" ) |
558 | |
559 | // P9 Vector extend sign builtins. |
560 | TARGET_BUILTIN(__builtin_altivec_vextsb2w, "V4SiV16Sc" , "" , "power9-vector" ) |
561 | TARGET_BUILTIN(__builtin_altivec_vextsb2d, "V2SLLiV16Sc" , "" , "power9-vector" ) |
562 | TARGET_BUILTIN(__builtin_altivec_vextsh2w, "V4SiV8Ss" , "" , "power9-vector" ) |
563 | TARGET_BUILTIN(__builtin_altivec_vextsh2d, "V2SLLiV8Ss" , "" , "power9-vector" ) |
564 | TARGET_BUILTIN(__builtin_altivec_vextsw2d, "V2SLLiV4Si" , "" , "power9-vector" ) |
565 | |
566 | // P10 Vector extend sign builtins. |
567 | TARGET_BUILTIN(__builtin_altivec_vextsd2q, "V1SLLLiV2SLLi" , "" , |
568 | "power10-vector" ) |
569 | |
570 | // P10 Vector Extract with Mask built-ins. |
571 | TARGET_BUILTIN(__builtin_altivec_vextractbm, "UiV16Uc" , "" , "power10-vector" ) |
572 | TARGET_BUILTIN(__builtin_altivec_vextracthm, "UiV8Us" , "" , "power10-vector" ) |
573 | TARGET_BUILTIN(__builtin_altivec_vextractwm, "UiV4Ui" , "" , "power10-vector" ) |
574 | TARGET_BUILTIN(__builtin_altivec_vextractdm, "UiV2ULLi" , "" , "power10-vector" ) |
575 | TARGET_BUILTIN(__builtin_altivec_vextractqm, "UiV1ULLLi" , "" , "power10-vector" ) |
576 | |
577 | // P10 Vector Divide Extended built-ins. |
578 | TARGET_BUILTIN(__builtin_altivec_vdivesw, "V4SiV4SiV4Si" , "" , "power10-vector" ) |
579 | TARGET_BUILTIN(__builtin_altivec_vdiveuw, "V4UiV4UiV4Ui" , "" , "power10-vector" ) |
580 | TARGET_BUILTIN(__builtin_altivec_vdivesd, "V2LLiV2LLiV2LLi" , "" , |
581 | "power10-vector" ) |
582 | TARGET_BUILTIN(__builtin_altivec_vdiveud, "V2ULLiV2ULLiV2ULLi" , "" , |
583 | "power10-vector" ) |
584 | TARGET_BUILTIN(__builtin_altivec_vdivesq, "V1SLLLiV1SLLLiV1SLLLi" , "" , |
585 | "power10-vector" ) |
586 | TARGET_BUILTIN(__builtin_altivec_vdiveuq, "V1ULLLiV1ULLLiV1ULLLi" , "" , |
587 | "power10-vector" ) |
588 | |
589 | // P10 Vector Multiply High built-ins. |
590 | TARGET_BUILTIN(__builtin_altivec_vmulhsw, "V4SiV4SiV4Si" , "" , "power10-vector" ) |
591 | TARGET_BUILTIN(__builtin_altivec_vmulhuw, "V4UiV4UiV4Ui" , "" , "power10-vector" ) |
592 | TARGET_BUILTIN(__builtin_altivec_vmulhsd, "V2LLiV2LLiV2LLi" , "" , |
593 | "power10-vector" ) |
594 | TARGET_BUILTIN(__builtin_altivec_vmulhud, "V2ULLiV2ULLiV2ULLi" , "" , |
595 | "power10-vector" ) |
596 | |
597 | // P10 Vector Expand with Mask built-ins. |
598 | TARGET_BUILTIN(__builtin_altivec_vexpandbm, "V16UcV16Uc" , "" , "power10-vector" ) |
599 | TARGET_BUILTIN(__builtin_altivec_vexpandhm, "V8UsV8Us" , "" , "power10-vector" ) |
600 | TARGET_BUILTIN(__builtin_altivec_vexpandwm, "V4UiV4Ui" , "" , "power10-vector" ) |
601 | TARGET_BUILTIN(__builtin_altivec_vexpanddm, "V2ULLiV2ULLi" , "" , |
602 | "power10-vector" ) |
603 | TARGET_BUILTIN(__builtin_altivec_vexpandqm, "V1ULLLiV1ULLLi" , "" , |
604 | "power10-vector" ) |
605 | |
606 | // P10 Vector Count with Mask built-ins. |
607 | TARGET_BUILTIN(__builtin_altivec_vcntmbb, "ULLiV16UcUi" , "" , "power10-vector" ) |
608 | TARGET_BUILTIN(__builtin_altivec_vcntmbh, "ULLiV8UsUi" , "" , "power10-vector" ) |
609 | TARGET_BUILTIN(__builtin_altivec_vcntmbw, "ULLiV4UiUi" , "" , "power10-vector" ) |
610 | TARGET_BUILTIN(__builtin_altivec_vcntmbd, "ULLiV2ULLiUi" , "" , "power10-vector" ) |
611 | |
612 | // P10 Move to VSR with Mask built-ins. |
613 | TARGET_BUILTIN(__builtin_altivec_mtvsrbm, "V16UcULLi" , "" , "power10-vector" ) |
614 | TARGET_BUILTIN(__builtin_altivec_mtvsrhm, "V8UsULLi" , "" , "power10-vector" ) |
615 | TARGET_BUILTIN(__builtin_altivec_mtvsrwm, "V4UiULLi" , "" , "power10-vector" ) |
616 | TARGET_BUILTIN(__builtin_altivec_mtvsrdm, "V2ULLiULLi" , "" , "power10-vector" ) |
617 | TARGET_BUILTIN(__builtin_altivec_mtvsrqm, "V1ULLLiULLi" , "" , "power10-vector" ) |
618 | |
619 | // P10 Vector Parallel Bits built-ins. |
620 | TARGET_BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi" , "" , |
621 | "power10-vector" ) |
622 | TARGET_BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi" , "" , |
623 | "power10-vector" ) |
624 | |
625 | // P10 Vector String Isolate Built-ins. |
626 | TARGET_BUILTIN(__builtin_altivec_vstribr, "V16UcV16Uc" , "" , "power10-vector" ) |
627 | TARGET_BUILTIN(__builtin_altivec_vstribl, "V16UcV16Uc" , "" , "power10-vector" ) |
628 | TARGET_BUILTIN(__builtin_altivec_vstrihr, "V8sV8s" , "" , "power10-vector" ) |
629 | TARGET_BUILTIN(__builtin_altivec_vstrihl, "V8sV8s" , "" , "power10-vector" ) |
630 | TARGET_BUILTIN(__builtin_altivec_vstribr_p, "iiV16Uc" , "" , "power10-vector" ) |
631 | TARGET_BUILTIN(__builtin_altivec_vstribl_p, "iiV16Uc" , "" , "power10-vector" ) |
632 | TARGET_BUILTIN(__builtin_altivec_vstrihr_p, "iiV8s" , "" , "power10-vector" ) |
633 | TARGET_BUILTIN(__builtin_altivec_vstrihl_p, "iiV8s" , "" , "power10-vector" ) |
634 | |
635 | // P10 Vector Centrifuge built-in. |
636 | TARGET_BUILTIN(__builtin_altivec_vcfuged, "V2ULLiV2ULLiV2ULLi" , "" , |
637 | "power10-vector" ) |
638 | |
639 | // P10 Vector Gather Every N-th Bit built-in. |
640 | TARGET_BUILTIN(__builtin_altivec_vgnb, "ULLiV1ULLLiIi" , "" , "power10-vector" ) |
641 | |
642 | // P10 Vector Clear Bytes built-ins. |
643 | TARGET_BUILTIN(__builtin_altivec_vclrlb, "V16UcV16UcUi" , "" , "power10-vector" ) |
644 | TARGET_BUILTIN(__builtin_altivec_vclrrb, "V16UcV16UcUi" , "" , "power10-vector" ) |
645 | |
646 | // P10 Vector Count Leading / Trailing Zeroes under bit Mask built-ins. |
647 | TARGET_BUILTIN(__builtin_altivec_vclzdm, "V2ULLiV2ULLiV2ULLi" , "" , |
648 | "power10-vector" ) |
649 | TARGET_BUILTIN(__builtin_altivec_vctzdm, "V2ULLiV2ULLiV2ULLi" , "" , |
650 | "power10-vector" ) |
651 | |
652 | // P10 Vector Shift built-ins. |
653 | TARGET_BUILTIN(__builtin_altivec_vsldbi, "V16UcV16UcV16UcIi" , "" , |
654 | "power10-vector" ) |
655 | TARGET_BUILTIN(__builtin_altivec_vsrdbi, "V16UcV16UcV16UcIi" , "" , |
656 | "power10-vector" ) |
657 | |
658 | // P10 Vector Insert built-ins. |
659 | TARGET_BUILTIN(__builtin_altivec_vinsblx, "V16UcV16UcUiUi" , "" , |
660 | "power10-vector" ) |
661 | TARGET_BUILTIN(__builtin_altivec_vinsbrx, "V16UcV16UcUiUi" , "" , |
662 | "power10-vector" ) |
663 | TARGET_BUILTIN(__builtin_altivec_vinshlx, "V8UsV8UsUiUi" , "" , "power10-vector" ) |
664 | TARGET_BUILTIN(__builtin_altivec_vinshrx, "V8UsV8UsUiUi" , "" , "power10-vector" ) |
665 | TARGET_BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiUiUi" , "" , "power10-vector" ) |
666 | TARGET_BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiUiUi" , "" , "power10-vector" ) |
667 | TARGET_BUILTIN(__builtin_altivec_vinsdlx, "V2ULLiV2ULLiULLiULLi" , "" , |
668 | "power10-vector" ) |
669 | TARGET_BUILTIN(__builtin_altivec_vinsdrx, "V2ULLiV2ULLiULLiULLi" , "" , |
670 | "power10-vector" ) |
671 | TARGET_BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcUiV16Uc" , "" , |
672 | "power10-vector" ) |
673 | TARGET_BUILTIN(__builtin_altivec_vinsbvrx, "V16UcV16UcUiV16Uc" , "" , |
674 | "power10-vector" ) |
675 | TARGET_BUILTIN(__builtin_altivec_vinshvlx, "V8UsV8UsUiV8Us" , "" , |
676 | "power10-vector" ) |
677 | TARGET_BUILTIN(__builtin_altivec_vinshvrx, "V8UsV8UsUiV8Us" , "" , |
678 | "power10-vector" ) |
679 | TARGET_BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiUiV4Ui" , "" , |
680 | "power10-vector" ) |
681 | TARGET_BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiUiV4Ui" , "" , |
682 | "power10-vector" ) |
683 | TARGET_BUILTIN(__builtin_altivec_vinsw, "V16UcV16UcUiIi" , "" , "power10-vector" ) |
684 | TARGET_BUILTIN(__builtin_altivec_vinsd, "V16UcV16UcULLiIi" , "" , |
685 | "power10-vector" ) |
686 | TARGET_BUILTIN(__builtin_altivec_vinsw_elt, "V16UcV16UcUiiC" , "" , |
687 | "power10-vector" ) |
688 | TARGET_BUILTIN(__builtin_altivec_vinsd_elt, "V16UcV16UcULLiiC" , "" , |
689 | "power10-vector" ) |
690 | |
691 | // P10 Vector Extract built-ins. |
692 | TARGET_BUILTIN(__builtin_altivec_vextdubvlx, "V2ULLiV16UcV16UcUi" , "" , |
693 | "power10-vector" ) |
694 | TARGET_BUILTIN(__builtin_altivec_vextdubvrx, "V2ULLiV16UcV16UcUi" , "" , |
695 | "power10-vector" ) |
696 | TARGET_BUILTIN(__builtin_altivec_vextduhvlx, "V2ULLiV8UsV8UsUi" , "" , |
697 | "power10-vector" ) |
698 | TARGET_BUILTIN(__builtin_altivec_vextduhvrx, "V2ULLiV8UsV8UsUi" , "" , |
699 | "power10-vector" ) |
700 | TARGET_BUILTIN(__builtin_altivec_vextduwvlx, "V2ULLiV4UiV4UiUi" , "" , |
701 | "power10-vector" ) |
702 | TARGET_BUILTIN(__builtin_altivec_vextduwvrx, "V2ULLiV4UiV4UiUi" , "" , |
703 | "power10-vector" ) |
704 | TARGET_BUILTIN(__builtin_altivec_vextddvlx, "V2ULLiV2ULLiV2ULLiUi" , "" , |
705 | "power10-vector" ) |
706 | TARGET_BUILTIN(__builtin_altivec_vextddvrx, "V2ULLiV2ULLiV2ULLiUi" , "" , |
707 | "power10-vector" ) |
708 | |
709 | // P10 Vector rotate built-ins. |
710 | TARGET_BUILTIN(__builtin_altivec_vrlqmi, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi" , "" , |
711 | "power10-vector" ) |
712 | TARGET_BUILTIN(__builtin_altivec_vrlqnm, "V1ULLLiV1ULLLiV1ULLLi" , "" , |
713 | "power10-vector" ) |
714 | |
715 | // VSX built-ins. |
716 | |
717 | TARGET_BUILTIN(__builtin_vsx_lxvd2x, "V2dLivC*" , "" , "vsx" ) |
718 | TARGET_BUILTIN(__builtin_vsx_lxvw4x, "V4iLivC*" , "" , "vsx" ) |
719 | TARGET_BUILTIN(__builtin_vsx_lxvd2x_be, "V2dSLLivC*" , "" , "vsx" ) |
720 | TARGET_BUILTIN(__builtin_vsx_lxvw4x_be, "V4iSLLivC*" , "" , "vsx" ) |
721 | |
722 | TARGET_BUILTIN(__builtin_vsx_stxvd2x, "vV2dLiv*" , "" , "vsx" ) |
723 | TARGET_BUILTIN(__builtin_vsx_stxvw4x, "vV4iLiv*" , "" , "vsx" ) |
724 | TARGET_BUILTIN(__builtin_vsx_stxvd2x_be, "vV2dSLLivC*" , "" , "vsx" ) |
725 | TARGET_BUILTIN(__builtin_vsx_stxvw4x_be, "vV4iSLLivC*" , "" , "vsx" ) |
726 | |
727 | TARGET_BUILTIN(__builtin_vsx_lxvl, "V4ivC*ULLi" , "" , "power9-vector" ) |
728 | TARGET_BUILTIN(__builtin_vsx_lxvll, "V4ivC*ULLi" , "" , "power9-vector" ) |
729 | TARGET_BUILTIN(__builtin_vsx_stxvl, "vV4iv*ULLi" , "" , "power9-vector" ) |
730 | TARGET_BUILTIN(__builtin_vsx_stxvll, "vV4iv*ULLi" , "" , "power9-vector" ) |
731 | TARGET_BUILTIN(__builtin_vsx_ldrmb, "V16UcCc*Ii" , "" , "isa-v207-instructions" ) |
732 | TARGET_BUILTIN(__builtin_vsx_strmb, "vCc*IiV16Uc" , "" , "isa-v207-instructions" ) |
733 | |
734 | TARGET_BUILTIN(__builtin_vsx_xvmaxdp, "V2dV2dV2d" , "" , "vsx" ) |
735 | TARGET_BUILTIN(__builtin_vsx_xvmaxsp, "V4fV4fV4f" , "" , "vsx" ) |
736 | TARGET_BUILTIN(__builtin_vsx_xsmaxdp, "ddd" , "" , "vsx" ) |
737 | |
738 | TARGET_BUILTIN(__builtin_vsx_xvmindp, "V2dV2dV2d" , "" , "vsx" ) |
739 | TARGET_BUILTIN(__builtin_vsx_xvminsp, "V4fV4fV4f" , "" , "vsx" ) |
740 | TARGET_BUILTIN(__builtin_vsx_xsmindp, "ddd" , "" , "vsx" ) |
741 | |
742 | TARGET_BUILTIN(__builtin_vsx_xvdivdp, "V2dV2dV2d" , "" , "vsx" ) |
743 | TARGET_BUILTIN(__builtin_vsx_xvdivsp, "V4fV4fV4f" , "" , "vsx" ) |
744 | |
745 | TARGET_BUILTIN(__builtin_vsx_xvrdpip, "V2dV2d" , "" , "vsx" ) |
746 | TARGET_BUILTIN(__builtin_vsx_xvrspip, "V4fV4f" , "" , "vsx" ) |
747 | |
748 | TARGET_BUILTIN(__builtin_vsx_xvcmpeqdp, "V2ULLiV2dV2d" , "" , "vsx" ) |
749 | TARGET_BUILTIN(__builtin_vsx_xvcmpeqsp, "V4UiV4fV4f" , "" , "vsx" ) |
750 | |
751 | TARGET_BUILTIN(__builtin_vsx_xvcmpeqdp_p, "iiV2dV2d" , "" , "vsx" ) |
752 | TARGET_BUILTIN(__builtin_vsx_xvcmpeqsp_p, "iiV4fV4f" , "" , "vsx" ) |
753 | |
754 | TARGET_BUILTIN(__builtin_vsx_xvcmpgedp, "V2ULLiV2dV2d" , "" , "vsx" ) |
755 | TARGET_BUILTIN(__builtin_vsx_xvcmpgesp, "V4UiV4fV4f" , "" , "vsx" ) |
756 | |
757 | TARGET_BUILTIN(__builtin_vsx_xvcmpgedp_p, "iiV2dV2d" , "" , "vsx" ) |
758 | TARGET_BUILTIN(__builtin_vsx_xvcmpgesp_p, "iiV4fV4f" , "" , "vsx" ) |
759 | |
760 | TARGET_BUILTIN(__builtin_vsx_xvcmpgtdp, "V2ULLiV2dV2d" , "" , "vsx" ) |
761 | TARGET_BUILTIN(__builtin_vsx_xvcmpgtsp, "V4UiV4fV4f" , "" , "vsx" ) |
762 | |
763 | TARGET_BUILTIN(__builtin_vsx_xvcmpgtdp_p, "iiV2dV2d" , "" , "vsx" ) |
764 | TARGET_BUILTIN(__builtin_vsx_xvcmpgtsp_p, "iiV4fV4f" , "" , "vsx" ) |
765 | |
766 | TARGET_BUILTIN(__builtin_vsx_xvrdpim, "V2dV2d" , "" , "vsx" ) |
767 | TARGET_BUILTIN(__builtin_vsx_xvrspim, "V4fV4f" , "" , "vsx" ) |
768 | |
769 | TARGET_BUILTIN(__builtin_vsx_xvrdpi, "V2dV2d" , "" , "vsx" ) |
770 | TARGET_BUILTIN(__builtin_vsx_xvrspi, "V4fV4f" , "" , "vsx" ) |
771 | |
772 | TARGET_BUILTIN(__builtin_vsx_xvrdpic, "V2dV2d" , "" , "vsx" ) |
773 | TARGET_BUILTIN(__builtin_vsx_xvrspic, "V4fV4f" , "" , "vsx" ) |
774 | |
775 | TARGET_BUILTIN(__builtin_vsx_xvrdpiz, "V2dV2d" , "" , "vsx" ) |
776 | TARGET_BUILTIN(__builtin_vsx_xvrspiz, "V4fV4f" , "" , "vsx" ) |
777 | |
778 | TARGET_BUILTIN(__builtin_vsx_xvmaddadp, "V2dV2dV2dV2d" , "" , "vsx" ) |
779 | TARGET_BUILTIN(__builtin_vsx_xvmaddasp, "V4fV4fV4fV4f" , "" , "vsx" ) |
780 | |
781 | TARGET_BUILTIN(__builtin_vsx_xvmsubadp, "V2dV2dV2dV2d" , "" , "vsx" ) |
782 | TARGET_BUILTIN(__builtin_vsx_xvmsubasp, "V4fV4fV4fV4f" , "" , "vsx" ) |
783 | |
784 | TARGET_BUILTIN(__builtin_vsx_xvmuldp, "V2dV2dV2d" , "" , "vsx" ) |
785 | TARGET_BUILTIN(__builtin_vsx_xvmulsp, "V4fV4fV4f" , "" , "vsx" ) |
786 | |
787 | TARGET_BUILTIN(__builtin_vsx_xvnmaddadp, "V2dV2dV2dV2d" , "" , "vsx" ) |
788 | TARGET_BUILTIN(__builtin_vsx_xvnmaddasp, "V4fV4fV4fV4f" , "" , "vsx" ) |
789 | |
790 | TARGET_BUILTIN(__builtin_vsx_xvnmsubadp, "V2dV2dV2dV2d" , "" , "vsx" ) |
791 | TARGET_BUILTIN(__builtin_vsx_xvnmsubasp, "V4fV4fV4fV4f" , "" , "vsx" ) |
792 | |
793 | TARGET_BUILTIN(__builtin_vsx_xvredp, "V2dV2d" , "" , "vsx" ) |
794 | TARGET_BUILTIN(__builtin_vsx_xvresp, "V4fV4f" , "" , "vsx" ) |
795 | |
796 | TARGET_BUILTIN(__builtin_vsx_xvrsqrtedp, "V2dV2d" , "" , "vsx" ) |
797 | TARGET_BUILTIN(__builtin_vsx_xvrsqrtesp, "V4fV4f" , "" , "vsx" ) |
798 | |
799 | TARGET_BUILTIN(__builtin_vsx_xvsqrtdp, "V2dV2d" , "" , "vsx" ) |
800 | TARGET_BUILTIN(__builtin_vsx_xvsqrtsp, "V4fV4f" , "" , "vsx" ) |
801 | |
802 | TARGET_BUILTIN(__builtin_vsx_xxleqv, "V4UiV4UiV4Ui" , "" , "power8-vector" ) |
803 | |
804 | TARGET_BUILTIN(__builtin_vsx_xvcpsgndp, "V2dV2dV2d" , "" , "vsx" ) |
805 | TARGET_BUILTIN(__builtin_vsx_xvcpsgnsp, "V4fV4fV4f" , "" , "vsx" ) |
806 | |
807 | TARGET_BUILTIN(__builtin_vsx_xvabssp, "V4fV4f" , "" , "vsx" ) |
808 | TARGET_BUILTIN(__builtin_vsx_xvabsdp, "V2dV2d" , "" , "vsx" ) |
809 | |
810 | TARGET_BUILTIN(__builtin_vsx_xxgenpcvbm, "V16UcV16Uci" , "" , "power10-vector" ) |
811 | TARGET_BUILTIN(__builtin_vsx_xxgenpcvhm, "V8UsV8Usi" , "" , "power10-vector" ) |
812 | TARGET_BUILTIN(__builtin_vsx_xxgenpcvwm, "V4UiV4Uii" , "" , "power10-vector" ) |
813 | TARGET_BUILTIN(__builtin_vsx_xxgenpcvdm, "V2ULLiV2ULLii" , "" , "power10-vector" ) |
814 | |
815 | // vector Insert/Extract exponent/significand builtins |
816 | TARGET_BUILTIN(__builtin_vsx_xviexpdp, "V2dV2ULLiV2ULLi" , "" , "power9-vector" ) |
817 | TARGET_BUILTIN(__builtin_vsx_xviexpsp, "V4fV4UiV4Ui" , "" , "power9-vector" ) |
818 | TARGET_BUILTIN(__builtin_vsx_xvxexpdp, "V2ULLiV2d" , "" , "power9-vector" ) |
819 | TARGET_BUILTIN(__builtin_vsx_xvxexpsp, "V4UiV4f" , "" , "power9-vector" ) |
820 | TARGET_BUILTIN(__builtin_vsx_xvxsigdp, "V2ULLiV2d" , "" , "power9-vector" ) |
821 | TARGET_BUILTIN(__builtin_vsx_xvxsigsp, "V4UiV4f" , "" , "power9-vector" ) |
822 | |
823 | // Conversion builtins |
824 | TARGET_BUILTIN(__builtin_vsx_xvcvdpsxws, "V4SiV2d" , "" , "vsx" ) |
825 | TARGET_BUILTIN(__builtin_vsx_xvcvdpuxws, "V4UiV2d" , "" , "vsx" ) |
826 | TARGET_BUILTIN(__builtin_vsx_xvcvspsxds, "V2SLLiV4f" , "" , "vsx" ) |
827 | TARGET_BUILTIN(__builtin_vsx_xvcvspuxds, "V2ULLiV4f" , "" , "vsx" ) |
828 | TARGET_BUILTIN(__builtin_vsx_xvcvsxwdp, "V2dV4Si" , "" , "vsx" ) |
829 | TARGET_BUILTIN(__builtin_vsx_xvcvuxwdp, "V2dV4Ui" , "" , "vsx" ) |
830 | TARGET_BUILTIN(__builtin_vsx_xvcvspdp, "V2dV4f" , "" , "vsx" ) |
831 | TARGET_BUILTIN(__builtin_vsx_xvcvsxdsp, "V4fV2SLLi" , "" , "vsx" ) |
832 | TARGET_BUILTIN(__builtin_vsx_xvcvuxdsp, "V4fV2ULLi" , "" , "vsx" ) |
833 | TARGET_BUILTIN(__builtin_vsx_xvcvdpsp, "V4fV2d" , "" , "vsx" ) |
834 | |
835 | TARGET_BUILTIN(__builtin_vsx_xvcvsphp, "V4fV4f" , "" , "power9-vector" ) |
836 | TARGET_BUILTIN(__builtin_vsx_xvcvhpsp, "V4fV8Us" , "" , "power9-vector" ) |
837 | |
838 | TARGET_BUILTIN(__builtin_vsx_xvcvspbf16, "V16UcV16Uc" , "" , "power10-vector" ) |
839 | TARGET_BUILTIN(__builtin_vsx_xvcvbf16spn, "V16UcV16Uc" , "" , "power10-vector" ) |
840 | |
841 | // Vector Test Data Class builtins |
842 | TARGET_BUILTIN(__builtin_vsx_xvtstdcdp, "V2ULLiV2dIi" , "" , "power9-vector" ) |
843 | TARGET_BUILTIN(__builtin_vsx_xvtstdcsp, "V4UiV4fIi" , "" , "power9-vector" ) |
844 | |
845 | TARGET_BUILTIN(__builtin_vsx_insertword, "V16UcV4UiV16UcIi" , "" , "vsx" ) |
846 | TARGET_BUILTIN(__builtin_vsx_extractuword, "V2ULLiV16UcIi" , "" , "vsx" ) |
847 | |
848 | TARGET_BUILTIN(__builtin_vsx_xxpermdi, "v." , "t" , "vsx" ) |
849 | TARGET_BUILTIN(__builtin_vsx_xxsldwi, "v." , "t" , "vsx" ) |
850 | |
851 | TARGET_BUILTIN(__builtin_vsx_xxeval, "V2ULLiV2ULLiV2ULLiV2ULLiIi" , "" , |
852 | "power10-vector" ) |
853 | |
854 | TARGET_BUILTIN(__builtin_vsx_xvtlsbb, "iV16UcUi" , "" , "power10-vector" ) |
855 | |
856 | TARGET_BUILTIN(__builtin_vsx_xvtdivdp, "iV2dV2d" , "" , "vsx" ) |
857 | TARGET_BUILTIN(__builtin_vsx_xvtdivsp, "iV4fV4f" , "" , "vsx" ) |
858 | TARGET_BUILTIN(__builtin_vsx_xvtsqrtdp, "iV2d" , "" , "vsx" ) |
859 | TARGET_BUILTIN(__builtin_vsx_xvtsqrtsp, "iV4f" , "" , "vsx" ) |
860 | |
861 | // P10 Vector Permute Extended built-in. |
862 | TARGET_BUILTIN(__builtin_vsx_xxpermx, "V16UcV16UcV16UcV16UcIi" , "" , |
863 | "power10-vector" ) |
864 | |
865 | // P10 Vector Blend built-ins. |
866 | TARGET_BUILTIN(__builtin_vsx_xxblendvb, "V16UcV16UcV16UcV16Uc" , "" , |
867 | "power10-vector" ) |
868 | TARGET_BUILTIN(__builtin_vsx_xxblendvh, "V8UsV8UsV8UsV8Us" , "" , |
869 | "power10-vector" ) |
870 | TARGET_BUILTIN(__builtin_vsx_xxblendvw, "V4UiV4UiV4UiV4Ui" , "" , |
871 | "power10-vector" ) |
872 | TARGET_BUILTIN(__builtin_vsx_xxblendvd, "V2ULLiV2ULLiV2ULLiV2ULLi" , "" , |
873 | "power10-vector" ) |
874 | |
875 | // Float 128 built-ins |
876 | TARGET_BUILTIN(__builtin_sqrtf128_round_to_odd, "LLdLLd" , "" , "float128" ) |
877 | TARGET_BUILTIN(__builtin_addf128_round_to_odd, "LLdLLdLLd" , "" , "float128" ) |
878 | TARGET_BUILTIN(__builtin_subf128_round_to_odd, "LLdLLdLLd" , "" , "float128" ) |
879 | TARGET_BUILTIN(__builtin_mulf128_round_to_odd, "LLdLLdLLd" , "" , "float128" ) |
880 | TARGET_BUILTIN(__builtin_divf128_round_to_odd, "LLdLLdLLd" , "" , "float128" ) |
881 | TARGET_BUILTIN(__builtin_fmaf128_round_to_odd, "LLdLLdLLdLLd" , "" , "float128" ) |
882 | TARGET_BUILTIN(__builtin_truncf128_round_to_odd, "dLLd" , "" , "float128" ) |
883 | TARGET_BUILTIN(__builtin_vsx_scalar_extract_expq, "ULLiLLd" , "" , "float128" ) |
884 | TARGET_BUILTIN(__builtin_vsx_scalar_insert_exp_qp, "LLdLLdULLi" , "" , "float128" ) |
885 | |
886 | // Fastmath by default builtins |
887 | BUILTIN(__builtin_ppc_rsqrtf, "V4fV4f" , "" ) |
888 | BUILTIN(__builtin_ppc_rsqrtd, "V2dV2d" , "" ) |
889 | BUILTIN(__builtin_ppc_recipdivf, "V4fV4fV4f" , "" ) |
890 | BUILTIN(__builtin_ppc_recipdivd, "V2dV2dV2d" , "" ) |
891 | |
892 | // HTM builtins |
893 | TARGET_BUILTIN(__builtin_tbegin, "UiUIi" , "" , "htm" ) |
894 | TARGET_BUILTIN(__builtin_tend, "UiUIi" , "" , "htm" ) |
895 | |
896 | TARGET_BUILTIN(__builtin_tabort, "UiUi" , "" , "htm" ) |
897 | TARGET_BUILTIN(__builtin_tabortdc, "UiUiUiUi" , "" , "htm" ) |
898 | TARGET_BUILTIN(__builtin_tabortdci, "UiUiUii" , "" , "htm" ) |
899 | TARGET_BUILTIN(__builtin_tabortwc, "UiUiUiUi" , "" , "htm" ) |
900 | TARGET_BUILTIN(__builtin_tabortwci, "UiUiUii" , "" , "htm" ) |
901 | |
902 | TARGET_BUILTIN(__builtin_tcheck, "Ui" , "" , "htm" ) |
903 | TARGET_BUILTIN(__builtin_treclaim, "UiUi" , "" , "htm" ) |
904 | TARGET_BUILTIN(__builtin_trechkpt, "Ui" , "" , "htm" ) |
905 | TARGET_BUILTIN(__builtin_tsr, "UiUi" , "" , "htm" ) |
906 | |
907 | TARGET_BUILTIN(__builtin_tendall, "Ui" , "" , "htm" ) |
908 | TARGET_BUILTIN(__builtin_tresume, "Ui" , "" , "htm" ) |
909 | TARGET_BUILTIN(__builtin_tsuspend, "Ui" , "" , "htm" ) |
910 | |
911 | TARGET_BUILTIN(__builtin_get_texasr, "LUi" , "c" , "htm" ) |
912 | TARGET_BUILTIN(__builtin_get_texasru, "LUi" , "c" , "htm" ) |
913 | TARGET_BUILTIN(__builtin_get_tfhar, "LUi" , "c" , "htm" ) |
914 | TARGET_BUILTIN(__builtin_get_tfiar, "LUi" , "c" , "htm" ) |
915 | |
916 | TARGET_BUILTIN(__builtin_set_texasr, "vLUi" , "c" , "htm" ) |
917 | TARGET_BUILTIN(__builtin_set_texasru, "vLUi" , "c" , "htm" ) |
918 | TARGET_BUILTIN(__builtin_set_tfhar, "vLUi" , "c" , "htm" ) |
919 | TARGET_BUILTIN(__builtin_set_tfiar, "vLUi" , "c" , "htm" ) |
920 | |
921 | TARGET_BUILTIN(__builtin_ttest, "LUi" , "" , "htm" ) |
922 | |
923 | // Scalar built-ins |
924 | TARGET_BUILTIN(__builtin_divwe, "SiSiSi" , "" , "extdiv" ) |
925 | TARGET_BUILTIN(__builtin_divweu, "UiUiUi" , "" , "extdiv" ) |
926 | TARGET_BUILTIN(__builtin_divde, "SLLiSLLiSLLi" , "" , "extdiv" ) |
927 | TARGET_BUILTIN(__builtin_divdeu, "ULLiULLiULLi" , "" , "extdiv" ) |
928 | TARGET_BUILTIN(__builtin_bpermd, "SLLiSLLiSLLi" , "" , "bpermd" ) |
929 | TARGET_BUILTIN(__builtin_pdepd, "ULLiULLiULLi" , "" , "isa-v31-instructions" ) |
930 | TARGET_BUILTIN(__builtin_pextd, "ULLiULLiULLi" , "" , "isa-v31-instructions" ) |
931 | TARGET_BUILTIN(__builtin_cfuged, "ULLiULLiULLi" , "" , "isa-v31-instructions" ) |
932 | TARGET_BUILTIN(__builtin_cntlzdm, "ULLiULLiULLi" , "" , "isa-v31-instructions" ) |
933 | TARGET_BUILTIN(__builtin_cnttzdm, "ULLiULLiULLi" , "" , "isa-v31-instructions" ) |
934 | |
935 | // Double-double (un)pack |
936 | BUILTIN(__builtin_unpack_longdouble, "dLdIi" , "" ) |
937 | BUILTIN(__builtin_pack_longdouble, "Lddd" , "" ) |
938 | |
939 | // Generate random number |
940 | TARGET_BUILTIN(__builtin_darn, "LLi" , "" , "isa-v30-instructions" ) |
941 | TARGET_BUILTIN(__builtin_darn_raw, "LLi" , "" , "isa-v30-instructions" ) |
942 | TARGET_BUILTIN(__builtin_darn_32, "i" , "" , "isa-v30-instructions" ) |
943 | |
944 | // Vector int128 (un)pack |
945 | TARGET_BUILTIN(__builtin_unpack_vector_int128, "ULLiV1LLLii" , "" , "vsx" ) |
946 | TARGET_BUILTIN(__builtin_pack_vector_int128, "V1LLLiULLiULLi" , "" , "vsx" ) |
947 | |
948 | // Set the floating point rounding mode |
949 | BUILTIN(__builtin_setrnd, "di" , "" ) |
950 | |
951 | // Get content from current FPSCR |
952 | BUILTIN(__builtin_readflm, "d" , "" ) |
953 | |
954 | // Set content of FPSCR, and return its content before update |
955 | BUILTIN(__builtin_setflm, "dd" , "" ) |
956 | |
957 | // Cache built-ins |
958 | BUILTIN(__builtin_dcbf, "vvC*" , "" ) |
959 | |
960 | // Built-ins requiring custom code generation. |
961 | // Because these built-ins rely on target-dependent types and to avoid pervasive |
962 | // change, they are type checked manually in Sema using custom type descriptors. |
963 | // The first argument of the CUSTOM_BUILTIN macro is the name of the built-in |
964 | // with its prefix, the second argument is the name of the intrinsic this |
965 | // built-in generates, the third argument specifies the type of the function |
966 | // (result value, then each argument) as follows: |
967 | // i -> Unsigned integer followed by the greatest possible value for that |
968 | // argument or 0 if no constraint on the value. |
969 | // (e.g. i15 for a 4-bits value) |
970 | // V -> Vector type used with MMA built-ins (vector unsigned char) |
971 | // W -> PPC Vector type followed by the size of the vector type. |
972 | // (e.g. W512 for __vector_quad) |
973 | // any other descriptor -> Fall back to generic type descriptor decoding. |
974 | // The 'C' suffix can be used as a suffix to specify the const type. |
975 | // The '*' suffix can be used as a suffix to specify a pointer to a type. |
976 | // The fourth argument is set to true if the built-in accumulates its result into |
977 | // its given accumulator. |
978 | |
979 | // Provided builtins with _mma_ prefix for compatibility. |
980 | CUSTOM_BUILTIN(mma_lxvp, vsx_lxvp, "W256SLiW256C*" , false, |
981 | "paired-vector-memops" ) |
982 | CUSTOM_BUILTIN(mma_stxvp, vsx_stxvp, "vW256SLiW256*" , false, |
983 | "paired-vector-memops" ) |
984 | CUSTOM_BUILTIN(mma_assemble_pair, vsx_assemble_pair, "vW256*VV" , false, |
985 | "paired-vector-memops" ) |
986 | CUSTOM_BUILTIN(mma_disassemble_pair, vsx_disassemble_pair, "vv*W256*" , false, |
987 | "paired-vector-memops" ) |
988 | CUSTOM_BUILTIN(vsx_build_pair, vsx_assemble_pair, "vW256*VV" , false, |
989 | "paired-vector-memops" ) |
990 | CUSTOM_BUILTIN(mma_build_acc, mma_assemble_acc, "vW512*VVVV" , false, "mma" ) |
991 | |
992 | // UNALIASED_CUSTOM_BUILTIN macro is used for built-ins that have |
993 | // the same name as that of the intrinsic they generate, i.e. the |
994 | // ID and INTR are the same. |
995 | // This avoids repeating the ID and INTR in the macro expression. |
996 | |
997 | UNALIASED_CUSTOM_BUILTIN(vsx_lxvp, "W256SLiW256C*" , false, |
998 | "paired-vector-memops" ) |
999 | UNALIASED_CUSTOM_BUILTIN(vsx_stxvp, "vW256SLiW256*" , false, |
1000 | "paired-vector-memops" ) |
1001 | UNALIASED_CUSTOM_BUILTIN(vsx_assemble_pair, "vW256*VV" , false, |
1002 | "paired-vector-memops" ) |
1003 | UNALIASED_CUSTOM_BUILTIN(vsx_disassemble_pair, "vv*W256*" , false, |
1004 | "paired-vector-memops" ) |
1005 | |
1006 | // TODO: Require only mma after backend supports these without paired memops |
1007 | UNALIASED_CUSTOM_BUILTIN(mma_assemble_acc, "vW512*VVVV" , false, |
1008 | "mma,paired-vector-memops" ) |
1009 | UNALIASED_CUSTOM_BUILTIN(mma_disassemble_acc, "vv*W512*" , false, |
1010 | "mma,paired-vector-memops" ) |
1011 | UNALIASED_CUSTOM_BUILTIN(mma_xxmtacc, "vW512*" , true, |
1012 | "mma,paired-vector-memops" ) |
1013 | UNALIASED_CUSTOM_BUILTIN(mma_xxmfacc, "vW512*" , true, |
1014 | "mma,paired-vector-memops" ) |
1015 | UNALIASED_CUSTOM_BUILTIN(mma_xxsetaccz, "vW512*" , false, |
1016 | "mma,paired-vector-memops" ) |
1017 | UNALIASED_CUSTOM_BUILTIN(mma_xvi4ger8, "vW512*VV" , false, |
1018 | "mma,paired-vector-memops" ) |
1019 | UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4, "vW512*VV" , false, |
1020 | "mma,paired-vector-memops" ) |
1021 | UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2, "vW512*VV" , false, |
1022 | "mma,paired-vector-memops" ) |
1023 | UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2s, "vW512*VV" , false, |
1024 | "mma,paired-vector-memops" ) |
1025 | UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2, "vW512*VV" , false, |
1026 | "mma,paired-vector-memops" ) |
1027 | UNALIASED_CUSTOM_BUILTIN(mma_xvf32ger, "vW512*VV" , false, |
1028 | "mma,paired-vector-memops" ) |
1029 | UNALIASED_CUSTOM_BUILTIN(mma_xvf64ger, "vW512*W256V" , false, |
1030 | "mma,paired-vector-memops" ) |
1031 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvi4ger8, "vW512*VVi15i15i255" , false, |
1032 | "mma,paired-vector-memops" ) |
1033 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4, "vW512*VVi15i15i15" , false, |
1034 | "mma,paired-vector-memops" ) |
1035 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2, "vW512*VVi15i15i3" , false, |
1036 | "mma,paired-vector-memops" ) |
1037 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2s, "vW512*VVi15i15i3" , false, |
1038 | "mma,paired-vector-memops" ) |
1039 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2, "vW512*VVi15i15i3" , false, |
1040 | "mma,paired-vector-memops" ) |
1041 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32ger, "vW512*VVi15i15" , false, |
1042 | "mma,paired-vector-memops" ) |
1043 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64ger, "vW512*W256Vi15i3" , false, |
1044 | "mma,paired-vector-memops" ) |
1045 | UNALIASED_CUSTOM_BUILTIN(mma_xvi4ger8pp, "vW512*VV" , true, |
1046 | "mma,paired-vector-memops" ) |
1047 | UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4pp, "vW512*VV" , true, |
1048 | "mma,paired-vector-memops" ) |
1049 | UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4spp, "vW512*VV" , true, |
1050 | "mma,paired-vector-memops" ) |
1051 | UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2pp, "vW512*VV" , true, |
1052 | "mma,paired-vector-memops" ) |
1053 | UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2spp, "vW512*VV" , true, |
1054 | "mma,paired-vector-memops" ) |
1055 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvi4ger8pp, "vW512*VVi15i15i255" , true, |
1056 | "mma,paired-vector-memops" ) |
1057 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4pp, "vW512*VVi15i15i15" , true, |
1058 | "mma,paired-vector-memops" ) |
1059 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4spp, "vW512*VVi15i15i15" , true, |
1060 | "mma,paired-vector-memops" ) |
1061 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2pp, "vW512*VVi15i15i3" , true, |
1062 | "mma,paired-vector-memops" ) |
1063 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2spp, "vW512*VVi15i15i3" , true, |
1064 | "mma,paired-vector-memops" ) |
1065 | UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2pp, "vW512*VV" , true, |
1066 | "mma,paired-vector-memops" ) |
1067 | UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2pn, "vW512*VV" , true, |
1068 | "mma,paired-vector-memops" ) |
1069 | UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2np, "vW512*VV" , true, |
1070 | "mma,paired-vector-memops" ) |
1071 | UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2nn, "vW512*VV" , true, |
1072 | "mma,paired-vector-memops" ) |
1073 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2pp, "vW512*VVi15i15i3" , true, |
1074 | "mma,paired-vector-memops" ) |
1075 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2pn, "vW512*VVi15i15i3" , true, |
1076 | "mma,paired-vector-memops" ) |
1077 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2np, "vW512*VVi15i15i3" , true, |
1078 | "mma,paired-vector-memops" ) |
1079 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2nn, "vW512*VVi15i15i3" , true, |
1080 | "mma,paired-vector-memops" ) |
1081 | UNALIASED_CUSTOM_BUILTIN(mma_xvf32gerpp, "vW512*VV" , true, |
1082 | "mma,paired-vector-memops" ) |
1083 | UNALIASED_CUSTOM_BUILTIN(mma_xvf32gerpn, "vW512*VV" , true, |
1084 | "mma,paired-vector-memops" ) |
1085 | UNALIASED_CUSTOM_BUILTIN(mma_xvf32gernp, "vW512*VV" , true, |
1086 | "mma,paired-vector-memops" ) |
1087 | UNALIASED_CUSTOM_BUILTIN(mma_xvf32gernn, "vW512*VV" , true, |
1088 | "mma,paired-vector-memops" ) |
1089 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gerpp, "vW512*VVi15i15" , true, |
1090 | "mma,paired-vector-memops" ) |
1091 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gerpn, "vW512*VVi15i15" , true, |
1092 | "mma,paired-vector-memops" ) |
1093 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gernp, "vW512*VVi15i15" , true, |
1094 | "mma,paired-vector-memops" ) |
1095 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gernn, "vW512*VVi15i15" , true, |
1096 | "mma,paired-vector-memops" ) |
1097 | UNALIASED_CUSTOM_BUILTIN(mma_xvf64gerpp, "vW512*W256V" , true, |
1098 | "mma,paired-vector-memops" ) |
1099 | UNALIASED_CUSTOM_BUILTIN(mma_xvf64gerpn, "vW512*W256V" , true, |
1100 | "mma,paired-vector-memops" ) |
1101 | UNALIASED_CUSTOM_BUILTIN(mma_xvf64gernp, "vW512*W256V" , true, |
1102 | "mma,paired-vector-memops" ) |
1103 | UNALIASED_CUSTOM_BUILTIN(mma_xvf64gernn, "vW512*W256V" , true, |
1104 | "mma,paired-vector-memops" ) |
1105 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gerpp, "vW512*W256Vi15i3" , true, |
1106 | "mma,paired-vector-memops" ) |
1107 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gerpn, "vW512*W256Vi15i3" , true, |
1108 | "mma,paired-vector-memops" ) |
1109 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gernp, "vW512*W256Vi15i3" , true, |
1110 | "mma,paired-vector-memops" ) |
1111 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gernn, "vW512*W256Vi15i3" , true, |
1112 | "mma,paired-vector-memops" ) |
1113 | UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2, "vW512*VV" , false, |
1114 | "mma,paired-vector-memops" ) |
1115 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2, "vW512*VVi15i15i3" , false, |
1116 | "mma,paired-vector-memops" ) |
1117 | UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2pp, "vW512*VV" , true, |
1118 | "mma,paired-vector-memops" ) |
1119 | UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2pn, "vW512*VV" , true, |
1120 | "mma,paired-vector-memops" ) |
1121 | UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2np, "vW512*VV" , true, |
1122 | "mma,paired-vector-memops" ) |
1123 | UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2nn, "vW512*VV" , true, |
1124 | "mma,paired-vector-memops" ) |
1125 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2pp, "vW512*VVi15i15i3" , true, |
1126 | "mma,paired-vector-memops" ) |
1127 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2pn, "vW512*VVi15i15i3" , true, |
1128 | "mma,paired-vector-memops" ) |
1129 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2np, "vW512*VVi15i15i3" , true, |
1130 | "mma,paired-vector-memops" ) |
1131 | UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2nn, "vW512*VVi15i15i3" , true, |
1132 | "mma,paired-vector-memops" ) |
1133 | |
1134 | // FIXME: Obviously incomplete. |
1135 | |
1136 | #undef BUILTIN |
1137 | #undef CUSTOM_BUILTIN |
1138 | #undef UNALIASED_CUSTOM_BUILTIN |
1139 | |