1 | //===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file describes an abstract interface used to get information about a |
10 | // target machines register file. This information is used for a variety of |
11 | // purposed, especially register allocation. |
12 | // |
13 | //===----------------------------------------------------------------------===// |
14 | |
15 | #ifndef LLVM_MC_MCREGISTERINFO_H |
16 | #define LLVM_MC_MCREGISTERINFO_H |
17 | |
18 | #include "llvm/ADT/DenseMap.h" |
19 | #include "llvm/ADT/iterator.h" |
20 | #include "llvm/ADT/iterator_range.h" |
21 | #include "llvm/MC/LaneBitmask.h" |
22 | #include "llvm/MC/MCRegister.h" |
23 | #include <cassert> |
24 | #include <cstdint> |
25 | #include <iterator> |
26 | #include <utility> |
27 | |
28 | namespace llvm { |
29 | |
30 | class MCRegUnitIterator; |
31 | class MCSubRegIterator; |
32 | class MCSuperRegIterator; |
33 | |
34 | /// MCRegisterClass - Base class of TargetRegisterClass. |
35 | class MCRegisterClass { |
36 | public: |
37 | using iterator = const MCPhysReg*; |
38 | using const_iterator = const MCPhysReg*; |
39 | |
40 | const iterator RegsBegin; |
41 | const uint8_t *const RegSet; |
42 | const uint32_t NameIdx; |
43 | const uint16_t RegsSize; |
44 | const uint16_t RegSetSize; |
45 | const uint16_t ID; |
46 | const uint16_t RegSizeInBits; |
47 | const int8_t CopyCost; |
48 | const bool Allocatable; |
49 | const bool BaseClass; |
50 | |
51 | /// getID() - Return the register class ID number. |
52 | /// |
53 | unsigned getID() const { return ID; } |
54 | |
55 | /// begin/end - Return all of the registers in this class. |
56 | /// |
57 | iterator begin() const { return RegsBegin; } |
58 | iterator end() const { return RegsBegin + RegsSize; } |
59 | |
60 | /// getNumRegs - Return the number of registers in this class. |
61 | /// |
62 | unsigned getNumRegs() const { return RegsSize; } |
63 | |
64 | /// getRegister - Return the specified register in the class. |
65 | /// |
66 | unsigned getRegister(unsigned i) const { |
67 | assert(i < getNumRegs() && "Register number out of range!" ); |
68 | return RegsBegin[i]; |
69 | } |
70 | |
71 | /// contains - Return true if the specified register is included in this |
72 | /// register class. This does not include virtual registers. |
73 | bool contains(MCRegister Reg) const { |
74 | unsigned RegNo = unsigned(Reg); |
75 | unsigned InByte = RegNo % 8; |
76 | unsigned Byte = RegNo / 8; |
77 | if (Byte >= RegSetSize) |
78 | return false; |
79 | return (RegSet[Byte] & (1 << InByte)) != 0; |
80 | } |
81 | |
82 | /// contains - Return true if both registers are in this class. |
83 | bool contains(MCRegister Reg1, MCRegister Reg2) const { |
84 | return contains(Reg: Reg1) && contains(Reg: Reg2); |
85 | } |
86 | |
87 | /// Return the size of the physical register in bits if we are able to |
88 | /// determine it. This always returns zero for registers of targets that use |
89 | /// HW modes, as we need more information to determine the size of registers |
90 | /// in such cases. Use TargetRegisterInfo to cover them. |
91 | unsigned getSizeInBits() const { return RegSizeInBits; } |
92 | |
93 | /// getCopyCost - Return the cost of copying a value between two registers in |
94 | /// this class. A negative number means the register class is very expensive |
95 | /// to copy e.g. status flag register classes. |
96 | int getCopyCost() const { return CopyCost; } |
97 | |
98 | /// isAllocatable - Return true if this register class may be used to create |
99 | /// virtual registers. |
100 | bool isAllocatable() const { return Allocatable; } |
101 | |
102 | /// Return true if this register class has a defined BaseClassOrder. |
103 | bool isBaseClass() const { return BaseClass; } |
104 | }; |
105 | |
106 | /// MCRegisterDesc - This record contains information about a particular |
107 | /// register. The SubRegs field is a zero terminated array of registers that |
108 | /// are sub-registers of the specific register, e.g. AL, AH are sub-registers |
109 | /// of AX. The SuperRegs field is a zero terminated array of registers that are |
110 | /// super-registers of the specific register, e.g. RAX, EAX, are |
111 | /// super-registers of AX. |
112 | /// |
113 | struct MCRegisterDesc { |
114 | uint32_t Name; // Printable name for the reg (for debugging) |
115 | uint32_t SubRegs; // Sub-register set, described above |
116 | uint32_t SuperRegs; // Super-register set, described above |
117 | |
118 | // Offset into MCRI::SubRegIndices of a list of sub-register indices for each |
119 | // sub-register in SubRegs. |
120 | uint32_t SubRegIndices; |
121 | |
122 | // Points to the list of register units. The low bits hold the first regunit |
123 | // number, the high bits hold an offset into DiffLists. See MCRegUnitIterator. |
124 | uint32_t RegUnits; |
125 | |
126 | /// Index into list with lane mask sequences. The sequence contains a lanemask |
127 | /// for every register unit. |
128 | uint16_t RegUnitLaneMasks; |
129 | }; |
130 | |
131 | /// MCRegisterInfo base class - We assume that the target defines a static |
132 | /// array of MCRegisterDesc objects that represent all of the machine |
133 | /// registers that the target has. As such, we simply have to track a pointer |
134 | /// to this array so that we can turn register number into a register |
135 | /// descriptor. |
136 | /// |
137 | /// Note this class is designed to be a base class of TargetRegisterInfo, which |
138 | /// is the interface used by codegen. However, specific targets *should never* |
139 | /// specialize this class. MCRegisterInfo should only contain getters to access |
140 | /// TableGen generated physical register data. It must not be extended with |
141 | /// virtual methods. |
142 | /// |
143 | class MCRegisterInfo { |
144 | public: |
145 | using regclass_iterator = const MCRegisterClass *; |
146 | |
147 | /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be |
148 | /// performed with a binary search. |
149 | struct DwarfLLVMRegPair { |
150 | unsigned FromReg; |
151 | unsigned ToReg; |
152 | |
153 | bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; } |
154 | }; |
155 | |
156 | private: |
157 | const MCRegisterDesc *Desc; // Pointer to the descriptor array |
158 | unsigned NumRegs; // Number of entries in the array |
159 | MCRegister RAReg; // Return address register |
160 | MCRegister PCReg; // Program counter register |
161 | const MCRegisterClass *Classes; // Pointer to the regclass array |
162 | unsigned NumClasses; // Number of entries in the array |
163 | unsigned NumRegUnits; // Number of regunits. |
164 | const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table. |
165 | const int16_t *DiffLists; // Pointer to the difflists array |
166 | const LaneBitmask *RegUnitMaskSequences; // Pointer to lane mask sequences |
167 | // for register units. |
168 | const char *RegStrings; // Pointer to the string table. |
169 | const char *RegClassStrings; // Pointer to the class strings. |
170 | const uint16_t *SubRegIndices; // Pointer to the subreg lookup |
171 | // array. |
172 | unsigned NumSubRegIndices; // Number of subreg indices. |
173 | const uint16_t *RegEncodingTable; // Pointer to array of register |
174 | // encodings. |
175 | |
176 | unsigned L2DwarfRegsSize; |
177 | unsigned EHL2DwarfRegsSize; |
178 | unsigned Dwarf2LRegsSize; |
179 | unsigned EHDwarf2LRegsSize; |
180 | const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping |
181 | const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH |
182 | const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping |
183 | const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH |
184 | DenseMap<MCRegister, int> L2SEHRegs; // LLVM to SEH regs mapping |
185 | DenseMap<MCRegister, int> L2CVRegs; // LLVM to CV regs mapping |
186 | |
187 | /// Iterator class that can traverse the differentially encoded values in |
188 | /// DiffLists. Don't use this class directly, use one of the adaptors below. |
189 | class DiffListIterator |
190 | : public iterator_facade_base<DiffListIterator, std::forward_iterator_tag, |
191 | unsigned> { |
192 | unsigned Val = 0; |
193 | const int16_t *List = nullptr; |
194 | |
195 | public: |
196 | /// Constructs an invalid iterator, which is also the end iterator. |
197 | /// Call init() to point to something useful. |
198 | DiffListIterator() = default; |
199 | |
200 | /// Point the iterator to InitVal, decoding subsequent values from DiffList. |
201 | void init(unsigned InitVal, const int16_t *DiffList) { |
202 | Val = InitVal; |
203 | List = DiffList; |
204 | } |
205 | |
206 | /// Returns true if this iterator is not yet at the end. |
207 | bool isValid() const { return List; } |
208 | |
209 | /// Dereference the iterator to get the value at the current position. |
210 | const unsigned &operator*() const { return Val; } |
211 | |
212 | using DiffListIterator::iterator_facade_base::operator++; |
213 | /// Pre-increment to move to the next position. |
214 | DiffListIterator &operator++() { |
215 | assert(isValid() && "Cannot move off the end of the list." ); |
216 | int16_t D = *List++; |
217 | Val += D; |
218 | // The end of the list is encoded as a 0 differential. |
219 | if (!D) |
220 | List = nullptr; |
221 | return *this; |
222 | } |
223 | |
224 | bool operator==(const DiffListIterator &Other) const { |
225 | return List == Other.List; |
226 | } |
227 | }; |
228 | |
229 | public: |
230 | /// Return an iterator range over all sub-registers of \p Reg, excluding \p |
231 | /// Reg. |
232 | iterator_range<MCSubRegIterator> subregs(MCRegister Reg) const; |
233 | |
234 | /// Return an iterator range over all sub-registers of \p Reg, including \p |
235 | /// Reg. |
236 | iterator_range<MCSubRegIterator> subregs_inclusive(MCRegister Reg) const; |
237 | |
238 | /// Return an iterator range over all super-registers of \p Reg, excluding \p |
239 | /// Reg. |
240 | iterator_range<MCSuperRegIterator> superregs(MCRegister Reg) const; |
241 | |
242 | /// Return an iterator range over all super-registers of \p Reg, including \p |
243 | /// Reg. |
244 | iterator_range<MCSuperRegIterator> superregs_inclusive(MCRegister Reg) const; |
245 | |
246 | /// Return an iterator range over all sub- and super-registers of \p Reg, |
247 | /// including \p Reg. |
248 | detail::concat_range<const MCPhysReg, iterator_range<MCSubRegIterator>, |
249 | iterator_range<MCSuperRegIterator>> |
250 | sub_and_superregs_inclusive(MCRegister Reg) const; |
251 | |
252 | /// Returns an iterator range over all regunits for \p Reg. |
253 | iterator_range<MCRegUnitIterator> regunits(MCRegister Reg) const; |
254 | |
255 | // These iterators are allowed to sub-class DiffListIterator and access |
256 | // internal list pointers. |
257 | friend class MCSubRegIterator; |
258 | friend class MCSubRegIndexIterator; |
259 | friend class MCSuperRegIterator; |
260 | friend class MCRegUnitIterator; |
261 | friend class MCRegUnitMaskIterator; |
262 | friend class MCRegUnitRootIterator; |
263 | |
264 | /// Initialize MCRegisterInfo, called by TableGen |
265 | /// auto-generated routines. *DO NOT USE*. |
266 | void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, |
267 | unsigned PC, const MCRegisterClass *C, unsigned NC, |
268 | const MCPhysReg (*RURoots)[2], unsigned NRU, |
269 | const int16_t *DL, const LaneBitmask *RUMS, |
270 | const char *Strings, const char *ClassStrings, |
271 | const uint16_t *SubIndices, unsigned NumIndices, |
272 | const uint16_t *RET) { |
273 | Desc = D; |
274 | NumRegs = NR; |
275 | RAReg = RA; |
276 | PCReg = PC; |
277 | Classes = C; |
278 | DiffLists = DL; |
279 | RegUnitMaskSequences = RUMS; |
280 | RegStrings = Strings; |
281 | RegClassStrings = ClassStrings; |
282 | NumClasses = NC; |
283 | RegUnitRoots = RURoots; |
284 | NumRegUnits = NRU; |
285 | SubRegIndices = SubIndices; |
286 | NumSubRegIndices = NumIndices; |
287 | RegEncodingTable = RET; |
288 | |
289 | // Initialize DWARF register mapping variables |
290 | EHL2DwarfRegs = nullptr; |
291 | EHL2DwarfRegsSize = 0; |
292 | L2DwarfRegs = nullptr; |
293 | L2DwarfRegsSize = 0; |
294 | EHDwarf2LRegs = nullptr; |
295 | EHDwarf2LRegsSize = 0; |
296 | Dwarf2LRegs = nullptr; |
297 | Dwarf2LRegsSize = 0; |
298 | } |
299 | |
300 | /// Used to initialize LLVM register to Dwarf |
301 | /// register number mapping. Called by TableGen auto-generated routines. |
302 | /// *DO NOT USE*. |
303 | void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, |
304 | bool isEH) { |
305 | if (isEH) { |
306 | EHL2DwarfRegs = Map; |
307 | EHL2DwarfRegsSize = Size; |
308 | } else { |
309 | L2DwarfRegs = Map; |
310 | L2DwarfRegsSize = Size; |
311 | } |
312 | } |
313 | |
314 | /// Used to initialize Dwarf register to LLVM |
315 | /// register number mapping. Called by TableGen auto-generated routines. |
316 | /// *DO NOT USE*. |
317 | void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, |
318 | bool isEH) { |
319 | if (isEH) { |
320 | EHDwarf2LRegs = Map; |
321 | EHDwarf2LRegsSize = Size; |
322 | } else { |
323 | Dwarf2LRegs = Map; |
324 | Dwarf2LRegsSize = Size; |
325 | } |
326 | } |
327 | |
328 | /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register |
329 | /// number mapping. By default the SEH register number is just the same |
330 | /// as the LLVM register number. |
331 | /// FIXME: TableGen these numbers. Currently this requires target specific |
332 | /// initialization code. |
333 | void mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg) { |
334 | L2SEHRegs[LLVMReg] = SEHReg; |
335 | } |
336 | |
337 | void mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg) { |
338 | L2CVRegs[LLVMReg] = CVReg; |
339 | } |
340 | |
341 | /// This method should return the register where the return |
342 | /// address can be found. |
343 | MCRegister getRARegister() const { |
344 | return RAReg; |
345 | } |
346 | |
347 | /// Return the register which is the program counter. |
348 | MCRegister getProgramCounter() const { |
349 | return PCReg; |
350 | } |
351 | |
352 | const MCRegisterDesc &operator[](MCRegister RegNo) const { |
353 | assert(RegNo < NumRegs && |
354 | "Attempting to access record for invalid register number!" ); |
355 | return Desc[RegNo]; |
356 | } |
357 | |
358 | /// Provide a get method, equivalent to [], but more useful with a |
359 | /// pointer to this object. |
360 | const MCRegisterDesc &get(MCRegister RegNo) const { |
361 | return operator[](RegNo); |
362 | } |
363 | |
364 | /// Returns the physical register number of sub-register "Index" |
365 | /// for physical register RegNo. Return zero if the sub-register does not |
366 | /// exist. |
367 | MCRegister getSubReg(MCRegister Reg, unsigned Idx) const; |
368 | |
369 | /// Return a super-register of the specified register |
370 | /// Reg so its sub-register of index SubIdx is Reg. |
371 | MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, |
372 | const MCRegisterClass *RC) const; |
373 | |
374 | /// For a given register pair, return the sub-register index |
375 | /// if the second register is a sub-register of the first. Return zero |
376 | /// otherwise. |
377 | unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const; |
378 | |
379 | /// Return the human-readable symbolic target-specific name for the |
380 | /// specified physical register. |
381 | const char *getName(MCRegister RegNo) const { |
382 | return RegStrings + get(RegNo).Name; |
383 | } |
384 | |
385 | /// Return the number of registers this target has (useful for |
386 | /// sizing arrays holding per register information) |
387 | unsigned getNumRegs() const { |
388 | return NumRegs; |
389 | } |
390 | |
391 | /// Return the number of sub-register indices |
392 | /// understood by the target. Index 0 is reserved for the no-op sub-register, |
393 | /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers. |
394 | unsigned getNumSubRegIndices() const { |
395 | return NumSubRegIndices; |
396 | } |
397 | |
398 | /// Return the number of (native) register units in the |
399 | /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They |
400 | /// can be accessed through MCRegUnitIterator defined below. |
401 | unsigned getNumRegUnits() const { |
402 | return NumRegUnits; |
403 | } |
404 | |
405 | /// Map a target register to an equivalent dwarf register |
406 | /// number. Returns -1 if there is no equivalent value. The second |
407 | /// parameter allows targets to use different numberings for EH info and |
408 | /// debugging info. |
409 | int getDwarfRegNum(MCRegister RegNum, bool isEH) const; |
410 | |
411 | /// Map a dwarf register back to a target register. Returns std::nullopt is |
412 | /// there is no mapping. |
413 | std::optional<unsigned> getLLVMRegNum(unsigned RegNum, bool isEH) const; |
414 | |
415 | /// Map a target EH register number to an equivalent DWARF register |
416 | /// number. |
417 | int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const; |
418 | |
419 | /// Map a target register to an equivalent SEH register |
420 | /// number. Returns LLVM register number if there is no equivalent value. |
421 | int getSEHRegNum(MCRegister RegNum) const; |
422 | |
423 | /// Map a target register to an equivalent CodeView register |
424 | /// number. |
425 | int getCodeViewRegNum(MCRegister RegNum) const; |
426 | |
427 | regclass_iterator regclass_begin() const { return Classes; } |
428 | regclass_iterator regclass_end() const { return Classes+NumClasses; } |
429 | iterator_range<regclass_iterator> regclasses() const { |
430 | return make_range(x: regclass_begin(), y: regclass_end()); |
431 | } |
432 | |
433 | unsigned getNumRegClasses() const { |
434 | return (unsigned)(regclass_end()-regclass_begin()); |
435 | } |
436 | |
437 | /// Returns the register class associated with the enumeration |
438 | /// value. See class MCOperandInfo. |
439 | const MCRegisterClass& getRegClass(unsigned i) const { |
440 | assert(i < getNumRegClasses() && "Register Class ID out of range" ); |
441 | return Classes[i]; |
442 | } |
443 | |
444 | const char *getRegClassName(const MCRegisterClass *Class) const { |
445 | return RegClassStrings + Class->NameIdx; |
446 | } |
447 | |
448 | /// Returns the encoding for RegNo |
449 | uint16_t getEncodingValue(MCRegister RegNo) const { |
450 | assert(RegNo < NumRegs && |
451 | "Attempting to get encoding for invalid register number!" ); |
452 | return RegEncodingTable[RegNo]; |
453 | } |
454 | |
455 | /// Returns true if RegB is a sub-register of RegA. |
456 | bool isSubRegister(MCRegister RegA, MCRegister RegB) const { |
457 | return isSuperRegister(RegA: RegB, RegB: RegA); |
458 | } |
459 | |
460 | /// Returns true if RegB is a super-register of RegA. |
461 | bool isSuperRegister(MCRegister RegA, MCRegister RegB) const; |
462 | |
463 | /// Returns true if RegB is a sub-register of RegA or if RegB == RegA. |
464 | bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const { |
465 | return isSuperRegisterEq(RegA: RegB, RegB: RegA); |
466 | } |
467 | |
468 | /// Returns true if RegB is a super-register of RegA or if |
469 | /// RegB == RegA. |
470 | bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const { |
471 | return RegA == RegB || isSuperRegister(RegA, RegB); |
472 | } |
473 | |
474 | /// Returns true if RegB is a super-register or sub-register of RegA |
475 | /// or if RegB == RegA. |
476 | bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const { |
477 | return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB); |
478 | } |
479 | |
480 | /// Returns true if the two registers are equal or alias each other. |
481 | bool regsOverlap(MCRegister RegA, MCRegister RegB) const; |
482 | }; |
483 | |
484 | //===----------------------------------------------------------------------===// |
485 | // Register List Iterators |
486 | //===----------------------------------------------------------------------===// |
487 | |
488 | // MCRegisterInfo provides lists of super-registers, sub-registers, and |
489 | // aliasing registers. Use these iterator classes to traverse the lists. |
490 | |
491 | /// MCSubRegIterator enumerates all sub-registers of Reg. |
492 | /// If IncludeSelf is set, Reg itself is included in the list. |
493 | class MCSubRegIterator |
494 | : public iterator_adaptor_base<MCSubRegIterator, |
495 | MCRegisterInfo::DiffListIterator, |
496 | std::forward_iterator_tag, const MCPhysReg> { |
497 | // Cache the current value, so that we can return a reference to it. |
498 | MCPhysReg Val; |
499 | |
500 | public: |
501 | /// Constructs an end iterator. |
502 | MCSubRegIterator() = default; |
503 | |
504 | MCSubRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, |
505 | bool IncludeSelf = false) { |
506 | assert(MCRegister::isPhysicalRegister(Reg.id())); |
507 | I.init(InitVal: Reg.id(), DiffList: MCRI->DiffLists + MCRI->get(RegNo: Reg).SubRegs); |
508 | // Initially, the iterator points to Reg itself. |
509 | Val = MCPhysReg(*I); |
510 | if (!IncludeSelf) |
511 | ++*this; |
512 | } |
513 | |
514 | const MCPhysReg &operator*() const { return Val; } |
515 | |
516 | using iterator_adaptor_base::operator++; |
517 | MCSubRegIterator &operator++() { |
518 | Val = MCPhysReg(*++I); |
519 | return *this; |
520 | } |
521 | |
522 | /// Returns true if this iterator is not yet at the end. |
523 | bool isValid() const { return I.isValid(); } |
524 | }; |
525 | |
526 | /// Iterator that enumerates the sub-registers of a Reg and the associated |
527 | /// sub-register indices. |
528 | class MCSubRegIndexIterator { |
529 | MCSubRegIterator SRIter; |
530 | const uint16_t *SRIndex; |
531 | |
532 | public: |
533 | /// Constructs an iterator that traverses subregisters and their |
534 | /// associated subregister indices. |
535 | MCSubRegIndexIterator(MCRegister Reg, const MCRegisterInfo *MCRI) |
536 | : SRIter(Reg, MCRI) { |
537 | SRIndex = MCRI->SubRegIndices + MCRI->get(RegNo: Reg).SubRegIndices; |
538 | } |
539 | |
540 | /// Returns current sub-register. |
541 | MCRegister getSubReg() const { |
542 | return *SRIter; |
543 | } |
544 | |
545 | /// Returns sub-register index of the current sub-register. |
546 | unsigned getSubRegIndex() const { |
547 | return *SRIndex; |
548 | } |
549 | |
550 | /// Returns true if this iterator is not yet at the end. |
551 | bool isValid() const { return SRIter.isValid(); } |
552 | |
553 | /// Moves to the next position. |
554 | MCSubRegIndexIterator &operator++() { |
555 | ++SRIter; |
556 | ++SRIndex; |
557 | return *this; |
558 | } |
559 | }; |
560 | |
561 | /// MCSuperRegIterator enumerates all super-registers of Reg. |
562 | /// If IncludeSelf is set, Reg itself is included in the list. |
563 | class MCSuperRegIterator |
564 | : public iterator_adaptor_base<MCSuperRegIterator, |
565 | MCRegisterInfo::DiffListIterator, |
566 | std::forward_iterator_tag, const MCPhysReg> { |
567 | // Cache the current value, so that we can return a reference to it. |
568 | MCPhysReg Val; |
569 | |
570 | public: |
571 | /// Constructs an end iterator. |
572 | MCSuperRegIterator() = default; |
573 | |
574 | MCSuperRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI, |
575 | bool IncludeSelf = false) { |
576 | assert(MCRegister::isPhysicalRegister(Reg.id())); |
577 | I.init(InitVal: Reg.id(), DiffList: MCRI->DiffLists + MCRI->get(RegNo: Reg).SuperRegs); |
578 | // Initially, the iterator points to Reg itself. |
579 | Val = MCPhysReg(*I); |
580 | if (!IncludeSelf) |
581 | ++*this; |
582 | } |
583 | |
584 | const MCPhysReg &operator*() const { return Val; } |
585 | |
586 | using iterator_adaptor_base::operator++; |
587 | MCSuperRegIterator &operator++() { |
588 | Val = MCPhysReg(*++I); |
589 | return *this; |
590 | } |
591 | |
592 | /// Returns true if this iterator is not yet at the end. |
593 | bool isValid() const { return I.isValid(); } |
594 | }; |
595 | |
596 | // Definition for isSuperRegister. Put it down here since it needs the |
597 | // iterator defined above in addition to the MCRegisterInfo class itself. |
598 | inline bool MCRegisterInfo::isSuperRegister(MCRegister RegA, MCRegister RegB) const{ |
599 | return is_contained(Range: superregs(Reg: RegA), Element: RegB); |
600 | } |
601 | |
602 | //===----------------------------------------------------------------------===// |
603 | // Register Units |
604 | //===----------------------------------------------------------------------===// |
605 | |
606 | // MCRegUnitIterator enumerates a list of register units for Reg. The list is |
607 | // in ascending numerical order. |
608 | class MCRegUnitIterator |
609 | : public iterator_adaptor_base<MCRegUnitIterator, |
610 | MCRegisterInfo::DiffListIterator, |
611 | std::forward_iterator_tag, const MCRegUnit> { |
612 | // The value must be kept in sync with RegisterInfoEmitter.cpp. |
613 | static constexpr unsigned RegUnitBits = 12; |
614 | // Cache the current value, so that we can return a reference to it. |
615 | MCRegUnit Val; |
616 | |
617 | public: |
618 | /// Constructs an end iterator. |
619 | MCRegUnitIterator() = default; |
620 | |
621 | MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI) { |
622 | assert(Reg && "Null register has no regunits" ); |
623 | assert(MCRegister::isPhysicalRegister(Reg.id())); |
624 | // Decode the RegUnits MCRegisterDesc field. |
625 | unsigned RU = MCRI->get(RegNo: Reg).RegUnits; |
626 | unsigned FirstRU = RU & ((1u << RegUnitBits) - 1); |
627 | unsigned Offset = RU >> RegUnitBits; |
628 | I.init(InitVal: FirstRU, DiffList: MCRI->DiffLists + Offset); |
629 | Val = MCRegUnit(*I); |
630 | } |
631 | |
632 | const MCRegUnit &operator*() const { return Val; } |
633 | |
634 | using iterator_adaptor_base::operator++; |
635 | MCRegUnitIterator &operator++() { |
636 | Val = MCRegUnit(*++I); |
637 | return *this; |
638 | } |
639 | |
640 | /// Returns true if this iterator is not yet at the end. |
641 | bool isValid() const { return I.isValid(); } |
642 | }; |
643 | |
644 | /// MCRegUnitMaskIterator enumerates a list of register units and their |
645 | /// associated lane masks for Reg. The register units are in ascending |
646 | /// numerical order. |
647 | class MCRegUnitMaskIterator { |
648 | MCRegUnitIterator RUIter; |
649 | const LaneBitmask *MaskListIter; |
650 | |
651 | public: |
652 | MCRegUnitMaskIterator() = default; |
653 | |
654 | /// Constructs an iterator that traverses the register units and their |
655 | /// associated LaneMasks in Reg. |
656 | MCRegUnitMaskIterator(MCRegister Reg, const MCRegisterInfo *MCRI) |
657 | : RUIter(Reg, MCRI) { |
658 | uint16_t Idx = MCRI->get(RegNo: Reg).RegUnitLaneMasks; |
659 | MaskListIter = &MCRI->RegUnitMaskSequences[Idx]; |
660 | } |
661 | |
662 | /// Returns a (RegUnit, LaneMask) pair. |
663 | std::pair<unsigned,LaneBitmask> operator*() const { |
664 | return std::make_pair(x: *RUIter, y: *MaskListIter); |
665 | } |
666 | |
667 | /// Returns true if this iterator is not yet at the end. |
668 | bool isValid() const { return RUIter.isValid(); } |
669 | |
670 | /// Moves to the next position. |
671 | MCRegUnitMaskIterator &operator++() { |
672 | ++MaskListIter; |
673 | ++RUIter; |
674 | return *this; |
675 | } |
676 | }; |
677 | |
678 | // Each register unit has one or two root registers. The complete set of |
679 | // registers containing a register unit is the union of the roots and their |
680 | // super-registers. All registers aliasing Unit can be visited like this: |
681 | // |
682 | // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) { |
683 | // for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI) |
684 | // visit(*SI); |
685 | // } |
686 | |
687 | /// MCRegUnitRootIterator enumerates the root registers of a register unit. |
688 | class MCRegUnitRootIterator { |
689 | uint16_t Reg0 = 0; |
690 | uint16_t Reg1 = 0; |
691 | |
692 | public: |
693 | MCRegUnitRootIterator() = default; |
694 | |
695 | MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { |
696 | assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit" ); |
697 | Reg0 = MCRI->RegUnitRoots[RegUnit][0]; |
698 | Reg1 = MCRI->RegUnitRoots[RegUnit][1]; |
699 | } |
700 | |
701 | /// Dereference to get the current root register. |
702 | unsigned operator*() const { |
703 | return Reg0; |
704 | } |
705 | |
706 | /// Check if the iterator is at the end of the list. |
707 | bool isValid() const { |
708 | return Reg0; |
709 | } |
710 | |
711 | /// Preincrement to move to the next root register. |
712 | MCRegUnitRootIterator &operator++() { |
713 | assert(isValid() && "Cannot move off the end of the list." ); |
714 | Reg0 = Reg1; |
715 | Reg1 = 0; |
716 | return *this; |
717 | } |
718 | }; |
719 | |
720 | /// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is |
721 | /// set, Reg itself is included in the list. This iterator does not guarantee |
722 | /// any ordering or that entries are unique. |
723 | class MCRegAliasIterator { |
724 | private: |
725 | MCRegister Reg; |
726 | const MCRegisterInfo *MCRI; |
727 | bool IncludeSelf; |
728 | |
729 | MCRegUnitIterator RI; |
730 | MCRegUnitRootIterator RRI; |
731 | MCSuperRegIterator SI; |
732 | |
733 | public: |
734 | MCRegAliasIterator(MCRegister Reg, const MCRegisterInfo *MCRI, |
735 | bool IncludeSelf) |
736 | : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) { |
737 | // Initialize the iterators. |
738 | for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) { |
739 | for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) { |
740 | for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) { |
741 | if (!(!IncludeSelf && Reg == *SI)) |
742 | return; |
743 | } |
744 | } |
745 | } |
746 | } |
747 | |
748 | bool isValid() const { return RI.isValid(); } |
749 | |
750 | MCRegister operator*() const { |
751 | assert(SI.isValid() && "Cannot dereference an invalid iterator." ); |
752 | return *SI; |
753 | } |
754 | |
755 | void advance() { |
756 | // Assuming SI is valid. |
757 | ++SI; |
758 | if (SI.isValid()) return; |
759 | |
760 | ++RRI; |
761 | if (RRI.isValid()) { |
762 | SI = MCSuperRegIterator(*RRI, MCRI, true); |
763 | return; |
764 | } |
765 | |
766 | ++RI; |
767 | if (RI.isValid()) { |
768 | RRI = MCRegUnitRootIterator(*RI, MCRI); |
769 | SI = MCSuperRegIterator(*RRI, MCRI, true); |
770 | } |
771 | } |
772 | |
773 | MCRegAliasIterator &operator++() { |
774 | assert(isValid() && "Cannot move off the end of the list." ); |
775 | do advance(); |
776 | while (!IncludeSelf && isValid() && *SI == Reg); |
777 | return *this; |
778 | } |
779 | }; |
780 | |
781 | inline iterator_range<MCSubRegIterator> |
782 | MCRegisterInfo::subregs(MCRegister Reg) const { |
783 | return make_range(x: {Reg, this, /*IncludeSelf=*/false}, y: MCSubRegIterator()); |
784 | } |
785 | |
786 | inline iterator_range<MCSubRegIterator> |
787 | MCRegisterInfo::subregs_inclusive(MCRegister Reg) const { |
788 | return make_range(x: {Reg, this, /*IncludeSelf=*/true}, y: MCSubRegIterator()); |
789 | } |
790 | |
791 | inline iterator_range<MCSuperRegIterator> |
792 | MCRegisterInfo::superregs(MCRegister Reg) const { |
793 | return make_range(x: {Reg, this, /*IncludeSelf=*/false}, y: MCSuperRegIterator()); |
794 | } |
795 | |
796 | inline iterator_range<MCSuperRegIterator> |
797 | MCRegisterInfo::superregs_inclusive(MCRegister Reg) const { |
798 | return make_range(x: {Reg, this, /*IncludeSelf=*/true}, y: MCSuperRegIterator()); |
799 | } |
800 | |
801 | inline detail::concat_range<const MCPhysReg, iterator_range<MCSubRegIterator>, |
802 | iterator_range<MCSuperRegIterator>> |
803 | MCRegisterInfo::sub_and_superregs_inclusive(MCRegister Reg) const { |
804 | return concat<const MCPhysReg>(Ranges: subregs_inclusive(Reg), Ranges: superregs(Reg)); |
805 | } |
806 | |
807 | inline iterator_range<MCRegUnitIterator> |
808 | MCRegisterInfo::regunits(MCRegister Reg) const { |
809 | return make_range(x: {Reg, this}, y: MCRegUnitIterator()); |
810 | } |
811 | |
812 | } // end namespace llvm |
813 | |
814 | #endif // LLVM_MC_MCREGISTERINFO_H |
815 | |