| 1 | //===- ARMTargetDefEmitter.cpp - Generate data about ARM Architectures ----===// |
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| 2 | // |
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| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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| 4 | // See https://llvm.org/LICENSE.txt for license information. |
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| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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| 6 | // |
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| 7 | //===----------------------------------------------------------------------===// |
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| 8 | // |
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| 9 | // This tablegen backend exports information about CPUs, FPUs, architectures, |
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| 10 | // and features into a common format that can be used by both TargetParser and |
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| 11 | // the ARM and AArch64 backends. |
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| 12 | // |
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| 13 | //===----------------------------------------------------------------------===// |
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| 14 | |
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| 15 | #include "llvm/ADT/StringSet.h" |
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| 16 | #include "llvm/TableGen/Record.h" |
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| 17 | #include "llvm/TableGen/TableGenBackend.h" |
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| 18 | |
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| 19 | using namespace llvm; |
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| 20 | |
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| 21 | static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) { |
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| 22 | OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n" ; |
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| 23 | |
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| 24 | // Look through all SubtargetFeature defs with the given FieldName, and |
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| 25 | // collect the set of all Values that that FieldName is set to. |
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| 26 | auto gatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) { |
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| 27 | llvm::StringSet<> Set; |
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| 28 | for (const Record *Rec : RK.getAllDerivedDefinitions(ClassName: "SubtargetFeature" )) { |
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| 29 | if (Rec->getValueAsString(FieldName: "FieldName" ) == FieldName) { |
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| 30 | Set.insert(key: Rec->getValueAsString(FieldName: "Value" )); |
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| 31 | } |
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| 32 | } |
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| 33 | return Set; |
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| 34 | }; |
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| 35 | |
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| 36 | // The ARMProcFamilyEnum values are initialised by SubtargetFeature defs |
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| 37 | // which set the ARMProcFamily field. We can generate the enum from these defs |
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| 38 | // which look like this: |
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| 39 | // |
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| 40 | // def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", |
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| 41 | // "Cortex-A5 ARM processors", []>; |
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| 42 | OS << "#ifndef ARM_PROCESSOR_FAMILY\n" |
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| 43 | << "#define ARM_PROCESSOR_FAMILY(ENUM)\n" |
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| 44 | << "#endif\n\n" ; |
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| 45 | const StringSet<> ARMProcFamilyVals = |
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| 46 | gatherSubtargetFeatureFieldValues("ARMProcFamily" ); |
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| 47 | for (const StringRef &Family : ARMProcFamilyVals.keys()) |
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| 48 | OS << "ARM_PROCESSOR_FAMILY(" << Family << ")\n" ; |
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| 49 | OS << "\n#undef ARM_PROCESSOR_FAMILY\n\n" ; |
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| 50 | |
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| 51 | OS << "#ifndef ARM_ARCHITECTURE\n" |
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| 52 | << "#define ARM_ARCHITECTURE(ENUM)\n" |
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| 53 | << "#endif\n\n" ; |
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| 54 | // This should correspond to instances of the Architecture tablegen class. |
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| 55 | const StringSet<> ARMArchVals = gatherSubtargetFeatureFieldValues("ARMArch" ); |
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| 56 | for (const StringRef &Arch : ARMArchVals.keys()) |
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| 57 | OS << "ARM_ARCHITECTURE(" << Arch << ")\n" ; |
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| 58 | OS << "\n#undef ARM_ARCHITECTURE\n\n" ; |
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| 59 | } |
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| 60 | |
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| 61 | static TableGen::Emitter::Opt |
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| 62 | X("gen-arm-target-def" , EmitARMTargetDef, |
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| 63 | "Generate the ARM or AArch64 Architecture information header." ); |
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| 64 | |
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