1/* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988-2017 Free Software Foundation, Inc.
3
4This file is part of GCC.
5
6GCC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 3, or (at your option)
9any later version.
10
11GCC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16Under Section 7 of GPL version 3, you are granted additional
17permissions described in the GCC Runtime Library Exception, version
183.1, as published by the Free Software Foundation.
19
20You should have received a copy of the GNU General Public License and
21a copy of the GCC Runtime Library Exception along with this program;
22see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
23<http://www.gnu.org/licenses/>. */
24
25/* The purpose of this file is to define the characteristics of the i386,
26 independent of assembler syntax or operating system.
27
28 Three other files build on this one to describe a specific assembler syntax:
29 bsd386.h, att386.h, and sun386.h.
30
31 The actual tm.h file for a particular system should include
32 this file, and then the file for the appropriate assembler syntax.
33
34 Many macros that specify assembler syntax are omitted entirely from
35 this file because they really belong in the files for particular
36 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
37 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
38 that start with ASM_ or end in ASM_OP. */
39
40/* Redefines for option macros. */
41
42#define TARGET_64BIT TARGET_ISA_64BIT
43#define TARGET_64BIT_P(x) TARGET_ISA_64BIT_P(x)
44#define TARGET_MMX TARGET_ISA_MMX
45#define TARGET_MMX_P(x) TARGET_ISA_MMX_P(x)
46#define TARGET_3DNOW TARGET_ISA_3DNOW
47#define TARGET_3DNOW_P(x) TARGET_ISA_3DNOW_P(x)
48#define TARGET_3DNOW_A TARGET_ISA_3DNOW_A
49#define TARGET_3DNOW_A_P(x) TARGET_ISA_3DNOW_A_P(x)
50#define TARGET_SSE TARGET_ISA_SSE
51#define TARGET_SSE_P(x) TARGET_ISA_SSE_P(x)
52#define TARGET_SSE2 TARGET_ISA_SSE2
53#define TARGET_SSE2_P(x) TARGET_ISA_SSE2_P(x)
54#define TARGET_SSE3 TARGET_ISA_SSE3
55#define TARGET_SSE3_P(x) TARGET_ISA_SSE3_P(x)
56#define TARGET_SSSE3 TARGET_ISA_SSSE3
57#define TARGET_SSSE3_P(x) TARGET_ISA_SSSE3_P(x)
58#define TARGET_SSE4_1 TARGET_ISA_SSE4_1
59#define TARGET_SSE4_1_P(x) TARGET_ISA_SSE4_1_P(x)
60#define TARGET_SSE4_2 TARGET_ISA_SSE4_2
61#define TARGET_SSE4_2_P(x) TARGET_ISA_SSE4_2_P(x)
62#define TARGET_AVX TARGET_ISA_AVX
63#define TARGET_AVX_P(x) TARGET_ISA_AVX_P(x)
64#define TARGET_AVX2 TARGET_ISA_AVX2
65#define TARGET_AVX2_P(x) TARGET_ISA_AVX2_P(x)
66#define TARGET_AVX512F TARGET_ISA_AVX512F
67#define TARGET_AVX512F_P(x) TARGET_ISA_AVX512F_P(x)
68#define TARGET_AVX512PF TARGET_ISA_AVX512PF
69#define TARGET_AVX512PF_P(x) TARGET_ISA_AVX512PF_P(x)
70#define TARGET_AVX512ER TARGET_ISA_AVX512ER
71#define TARGET_AVX512ER_P(x) TARGET_ISA_AVX512ER_P(x)
72#define TARGET_AVX512CD TARGET_ISA_AVX512CD
73#define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x)
74#define TARGET_AVX512DQ TARGET_ISA_AVX512DQ
75#define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x)
76#define TARGET_AVX512BW TARGET_ISA_AVX512BW
77#define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x)
78#define TARGET_AVX512VL TARGET_ISA_AVX512VL
79#define TARGET_AVX512VL_P(x) TARGET_ISA_AVX512VL_P(x)
80#define TARGET_AVX512VBMI TARGET_ISA_AVX512VBMI
81#define TARGET_AVX512VBMI_P(x) TARGET_ISA_AVX512VBMI_P(x)
82#define TARGET_AVX512IFMA TARGET_ISA_AVX512IFMA
83#define TARGET_AVX512IFMA_P(x) TARGET_ISA_AVX512IFMA_P(x)
84#define TARGET_AVX5124FMAPS TARGET_ISA_AVX5124FMAPS
85#define TARGET_AVX5124FMAPS_P(x) TARGET_ISA_AVX5124FMAPS_P(x)
86#define TARGET_AVX5124VNNIW TARGET_ISA_AVX5124VNNIW
87#define TARGET_AVX5124VNNIW_P(x) TARGET_ISA_AVX5124VNNIW_P(x)
88#define TARGET_AVX512VBMI2 TARGET_ISA_AVX512VBMI2
89#define TARGET_AVX512VBMI2_P(x) TARGET_ISA_AVX512VBMI2_P(x)
90#define TARGET_AVX512VPOPCNTDQ TARGET_ISA_AVX512VPOPCNTDQ
91#define TARGET_AVX512VPOPCNTDQ_P(x) TARGET_ISA_AVX512VPOPCNTDQ_P(x)
92#define TARGET_AVX512VNNI TARGET_ISA_AVX512VNNI
93#define TARGET_AVX512VNNI_P(x) TARGET_ISA_AVX512VNNI_P(x)
94#define TARGET_FMA TARGET_ISA_FMA
95#define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x)
96#define TARGET_SSE4A TARGET_ISA_SSE4A
97#define TARGET_SSE4A_P(x) TARGET_ISA_SSE4A_P(x)
98#define TARGET_FMA4 TARGET_ISA_FMA4
99#define TARGET_FMA4_P(x) TARGET_ISA_FMA4_P(x)
100#define TARGET_XOP TARGET_ISA_XOP
101#define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x)
102#define TARGET_LWP TARGET_ISA_LWP
103#define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x)
104#define TARGET_ABM TARGET_ISA_ABM
105#define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x)
106#define TARGET_SGX TARGET_ISA_SGX
107#define TARGET_SGX_P(x) TARGET_ISA_SGX_P(x)
108#define TARGET_RDPID TARGET_ISA_RDPID
109#define TARGET_RDPID_P(x) TARGET_ISA_RDPID_P(x)
110#define TARGET_GFNI TARGET_ISA_GFNI
111#define TARGET_GFNI_P(x) TARGET_ISA_GFNI_P(x)
112#define TARGET_VAES TARGET_ISA_VAES
113#define TARGET_VAES_P(x) TARGET_ISA_VAES_P(x)
114#define TARGET_BMI TARGET_ISA_BMI
115#define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x)
116#define TARGET_BMI2 TARGET_ISA_BMI2
117#define TARGET_BMI2_P(x) TARGET_ISA_BMI2_P(x)
118#define TARGET_LZCNT TARGET_ISA_LZCNT
119#define TARGET_LZCNT_P(x) TARGET_ISA_LZCNT_P(x)
120#define TARGET_TBM TARGET_ISA_TBM
121#define TARGET_TBM_P(x) TARGET_ISA_TBM_P(x)
122#define TARGET_POPCNT TARGET_ISA_POPCNT
123#define TARGET_POPCNT_P(x) TARGET_ISA_POPCNT_P(x)
124#define TARGET_SAHF TARGET_ISA_SAHF
125#define TARGET_SAHF_P(x) TARGET_ISA_SAHF_P(x)
126#define TARGET_MOVBE TARGET_ISA_MOVBE
127#define TARGET_MOVBE_P(x) TARGET_ISA_MOVBE_P(x)
128#define TARGET_CRC32 TARGET_ISA_CRC32
129#define TARGET_CRC32_P(x) TARGET_ISA_CRC32_P(x)
130#define TARGET_AES TARGET_ISA_AES
131#define TARGET_AES_P(x) TARGET_ISA_AES_P(x)
132#define TARGET_SHA TARGET_ISA_SHA
133#define TARGET_SHA_P(x) TARGET_ISA_SHA_P(x)
134#define TARGET_CLFLUSHOPT TARGET_ISA_CLFLUSHOPT
135#define TARGET_CLFLUSHOPT_P(x) TARGET_ISA_CLFLUSHOPT_P(x)
136#define TARGET_CLZERO TARGET_ISA_CLZERO
137#define TARGET_CLZERO_P(x) TARGET_ISA_CLZERO_P(x)
138#define TARGET_XSAVEC TARGET_ISA_XSAVEC
139#define TARGET_XSAVEC_P(x) TARGET_ISA_XSAVEC_P(x)
140#define TARGET_XSAVES TARGET_ISA_XSAVES
141#define TARGET_XSAVES_P(x) TARGET_ISA_XSAVES_P(x)
142#define TARGET_PCLMUL TARGET_ISA_PCLMUL
143#define TARGET_PCLMUL_P(x) TARGET_ISA_PCLMUL_P(x)
144#define TARGET_CMPXCHG16B TARGET_ISA_CX16
145#define TARGET_CMPXCHG16B_P(x) TARGET_ISA_CX16_P(x)
146#define TARGET_FSGSBASE TARGET_ISA_FSGSBASE
147#define TARGET_FSGSBASE_P(x) TARGET_ISA_FSGSBASE_P(x)
148#define TARGET_RDRND TARGET_ISA_RDRND
149#define TARGET_RDRND_P(x) TARGET_ISA_RDRND_P(x)
150#define TARGET_F16C TARGET_ISA_F16C
151#define TARGET_F16C_P(x) TARGET_ISA_F16C_P(x)
152#define TARGET_RTM TARGET_ISA_RTM
153#define TARGET_RTM_P(x) TARGET_ISA_RTM_P(x)
154#define TARGET_HLE TARGET_ISA_HLE
155#define TARGET_HLE_P(x) TARGET_ISA_HLE_P(x)
156#define TARGET_RDSEED TARGET_ISA_RDSEED
157#define TARGET_RDSEED_P(x) TARGET_ISA_RDSEED_P(x)
158#define TARGET_PRFCHW TARGET_ISA_PRFCHW
159#define TARGET_PRFCHW_P(x) TARGET_ISA_PRFCHW_P(x)
160#define TARGET_ADX TARGET_ISA_ADX
161#define TARGET_ADX_P(x) TARGET_ISA_ADX_P(x)
162#define TARGET_FXSR TARGET_ISA_FXSR
163#define TARGET_FXSR_P(x) TARGET_ISA_FXSR_P(x)
164#define TARGET_XSAVE TARGET_ISA_XSAVE
165#define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x)
166#define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT
167#define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x)
168#define TARGET_PREFETCHWT1 TARGET_ISA_PREFETCHWT1
169#define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x)
170#define TARGET_MPX TARGET_ISA_MPX
171#define TARGET_MPX_P(x) TARGET_ISA_MPX_P(x)
172#define TARGET_CLWB TARGET_ISA_CLWB
173#define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x)
174#define TARGET_MWAITX TARGET_ISA_MWAITX
175#define TARGET_MWAITX_P(x) TARGET_ISA_MWAITX_P(x)
176#define TARGET_PKU TARGET_ISA_PKU
177#define TARGET_PKU_P(x) TARGET_ISA_PKU_P(x)
178#define TARGET_IBT TARGET_ISA_IBT
179#define TARGET_IBT_P(x) TARGET_ISA_IBT_P(x)
180#define TARGET_SHSTK TARGET_ISA_SHSTK
181#define TARGET_SHSTK_P(x) TARGET_ISA_SHSTK_P(x)
182
183#define TARGET_LP64 TARGET_ABI_64
184#define TARGET_LP64_P(x) TARGET_ABI_64_P(x)
185#define TARGET_X32 TARGET_ABI_X32
186#define TARGET_X32_P(x) TARGET_ABI_X32_P(x)
187#define TARGET_16BIT TARGET_CODE16
188#define TARGET_16BIT_P(x) TARGET_CODE16_P(x)
189
190#include "config/vxworks-dummy.h"
191
192#include "config/i386/i386-opts.h"
193
194#define MAX_STRINGOP_ALGS 4
195
196/* Specify what algorithm to use for stringops on known size.
197 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
198 known at compile time or estimated via feedback, the SIZE array
199 is walked in order until MAX is greater then the estimate (or -1
200 means infinity). Corresponding ALG is used then.
201 When NOALIGN is true the code guaranting the alignment of the memory
202 block is skipped.
203
204 For example initializer:
205 {{256, loop}, {-1, rep_prefix_4_byte}}
206 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
207 be used otherwise. */
208struct stringop_algs
209{
210 const enum stringop_alg unknown_size;
211 const struct stringop_strategy {
212 const int max;
213 const enum stringop_alg alg;
214 int noalign;
215 } size [MAX_STRINGOP_ALGS];
216};
217
218/* Define the specific costs for a given cpu */
219
220struct processor_costs {
221 const int add; /* cost of an add instruction */
222 const int lea; /* cost of a lea instruction */
223 const int shift_var; /* variable shift costs */
224 const int shift_const; /* constant shift costs */
225 const int mult_init[5]; /* cost of starting a multiply
226 in QImode, HImode, SImode, DImode, TImode*/
227 const int mult_bit; /* cost of multiply per each bit set */
228 const int divide[5]; /* cost of a divide/mod
229 in QImode, HImode, SImode, DImode, TImode*/
230 int movsx; /* The cost of movsx operation. */
231 int movzx; /* The cost of movzx operation. */
232 const int large_insn; /* insns larger than this cost more */
233 const int move_ratio; /* The threshold of number of scalar
234 memory-to-memory move insns. */
235 const int movzbl_load; /* cost of loading using movzbl */
236 const int int_load[3]; /* cost of loading integer registers
237 in QImode, HImode and SImode relative
238 to reg-reg move (2). */
239 const int int_store[3]; /* cost of storing integer register
240 in QImode, HImode and SImode */
241 const int fp_move; /* cost of reg,reg fld/fst */
242 const int fp_load[3]; /* cost of loading FP register
243 in SFmode, DFmode and XFmode */
244 const int fp_store[3]; /* cost of storing FP register
245 in SFmode, DFmode and XFmode */
246 const int mmx_move; /* cost of moving MMX register. */
247 const int mmx_load[2]; /* cost of loading MMX register
248 in SImode and DImode */
249 const int mmx_store[2]; /* cost of storing MMX register
250 in SImode and DImode */
251 const int xmm_move, ymm_move, /* cost of moving XMM and YMM register. */
252 zmm_move;
253 const int sse_load[5]; /* cost of loading SSE register
254 in 32bit, 64bit, 128bit, 256bit and 512bit */
255 const int sse_unaligned_load[5];/* cost of unaligned load. */
256 const int sse_store[5]; /* cost of storing SSE register
257 in SImode, DImode and TImode. */
258 const int sse_unaligned_store[5];/* cost of unaligned store. */
259 const int mmxsse_to_integer; /* cost of moving mmxsse register to
260 integer. */
261 const int ssemmx_to_integer; /* cost of moving integer to mmxsse register. */
262 const int gather_static, gather_per_elt; /* Cost of gather load is computed
263 as static + per_item * nelts. */
264 const int scatter_static, scatter_per_elt; /* Cost of gather store is
265 computed as static + per_item * nelts. */
266 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
267 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
268 const int prefetch_block; /* bytes moved to cache for prefetch. */
269 const int simultaneous_prefetches; /* number of parallel prefetch
270 operations. */
271 const int branch_cost; /* Default value for BRANCH_COST. */
272 const int fadd; /* cost of FADD and FSUB instructions. */
273 const int fmul; /* cost of FMUL instruction. */
274 const int fdiv; /* cost of FDIV instruction. */
275 const int fabs; /* cost of FABS instruction. */
276 const int fchs; /* cost of FCHS instruction. */
277 const int fsqrt; /* cost of FSQRT instruction. */
278 /* Specify what algorithm
279 to use for stringops on unknown size. */
280 const int sse_op; /* cost of cheap SSE instruction. */
281 const int addss; /* cost of ADDSS/SD SUBSS/SD instructions. */
282 const int mulss; /* cost of MULSS instructions. */
283 const int mulsd; /* cost of MULSD instructions. */
284 const int fmass; /* cost of FMASS instructions. */
285 const int fmasd; /* cost of FMASD instructions. */
286 const int divss; /* cost of DIVSS instructions. */
287 const int divsd; /* cost of DIVSD instructions. */
288 const int sqrtss; /* cost of SQRTSS instructions. */
289 const int sqrtsd; /* cost of SQRTSD instructions. */
290 const int reassoc_int, reassoc_fp, reassoc_vec_int, reassoc_vec_fp;
291 /* Specify reassociation width for integer,
292 fp, vector integer and vector fp
293 operations. Generally should correspond
294 to number of instructions executed in
295 parallel. See also
296 ix86_reassociation_width. */
297 struct stringop_algs *memcpy, *memset;
298 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
299 cost model. */
300 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
301 vectorizer cost model. */
302};
303
304extern const struct processor_costs *ix86_cost;
305extern const struct processor_costs ix86_size_cost;
306
307#define ix86_cur_cost() \
308 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost)
309
310/* Macros used in the machine description to test the flags. */
311
312/* configure can arrange to change it. */
313
314#ifndef TARGET_CPU_DEFAULT
315#define TARGET_CPU_DEFAULT PROCESSOR_GENERIC
316#endif
317
318#ifndef TARGET_FPMATH_DEFAULT
319#define TARGET_FPMATH_DEFAULT \
320 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
321#endif
322
323#ifndef TARGET_FPMATH_DEFAULT_P
324#define TARGET_FPMATH_DEFAULT_P(x) \
325 (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387)
326#endif
327
328/* If the i387 is disabled or -miamcu is used , then do not return
329 values in it. */
330#define TARGET_FLOAT_RETURNS_IN_80387 \
331 (TARGET_FLOAT_RETURNS && TARGET_80387 && !TARGET_IAMCU)
332#define TARGET_FLOAT_RETURNS_IN_80387_P(x) \
333 (TARGET_FLOAT_RETURNS_P(x) && TARGET_80387_P(x) && !TARGET_IAMCU_P(x))
334
335/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
336 compile-time constant. */
337#ifdef IN_LIBGCC2
338#undef TARGET_64BIT
339#ifdef __x86_64__
340#define TARGET_64BIT 1
341#else
342#define TARGET_64BIT 0
343#endif
344#else
345#ifndef TARGET_BI_ARCH
346#undef TARGET_64BIT
347#undef TARGET_64BIT_P
348#if TARGET_64BIT_DEFAULT
349#define TARGET_64BIT 1
350#define TARGET_64BIT_P(x) 1
351#else
352#define TARGET_64BIT 0
353#define TARGET_64BIT_P(x) 0
354#endif
355#endif
356#endif
357
358#define HAS_LONG_COND_BRANCH 1
359#define HAS_LONG_UNCOND_BRANCH 1
360
361#define TARGET_386 (ix86_tune == PROCESSOR_I386)
362#define TARGET_486 (ix86_tune == PROCESSOR_I486)
363#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
364#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
365#define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
366#define TARGET_K6 (ix86_tune == PROCESSOR_K6)
367#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
368#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
369#define TARGET_K8 (ix86_tune == PROCESSOR_K8)
370#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
371#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
372#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
373#define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM)
374#define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE)
375#define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL)
376#define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL)
377#define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT)
378#define TARGET_KNL (ix86_tune == PROCESSOR_KNL)
379#define TARGET_KNM (ix86_tune == PROCESSOR_KNM)
380#define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512)
381#define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE)
382#define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
383#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
384#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
385#define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1)
386#define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2)
387#define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3)
388#define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4)
389#define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1)
390#define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2)
391#define TARGET_ZNVER1 (ix86_tune == PROCESSOR_ZNVER1)
392
393/* Feature tests against the various tunings. */
394enum ix86_tune_indices {
395#undef DEF_TUNE
396#define DEF_TUNE(tune, name, selector) tune,
397#include "x86-tune.def"
398#undef DEF_TUNE
399X86_TUNE_LAST
400};
401
402extern unsigned char ix86_tune_features[X86_TUNE_LAST];
403
404#define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
405#define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
406#define TARGET_ZERO_EXTEND_WITH_AND \
407 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
408#define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
409#define TARGET_BRANCH_PREDICTION_HINTS \
410 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
411#define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
412#define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
413#define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
414#define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
415#define TARGET_PARTIAL_FLAG_REG_STALL \
416 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
417#define TARGET_LCP_STALL \
418 ix86_tune_features[X86_TUNE_LCP_STALL]
419#define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
420#define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
421#define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
422#define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
423#define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
424#define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
425#define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
426#define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
427#define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
428#define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
429#define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
430#define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \
431 ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES]
432#define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
433#define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
434#define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
435#define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
436#define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP]
437#define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP]
438#define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH]
439#define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH]
440#define TARGET_INTEGER_DFMODE_MOVES \
441 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
442#define TARGET_PARTIAL_REG_DEPENDENCY \
443 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
444#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
445 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
446#define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
447 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL]
448#define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \
449 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL]
450#define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \
451 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL]
452#define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
453#define TARGET_SSE_TYPELESS_STORES \
454 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
455#define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
456#define TARGET_MEMORY_MISMATCH_STALL \
457 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
458#define TARGET_PROLOGUE_USING_MOVE \
459 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
460#define TARGET_EPILOGUE_USING_MOVE \
461 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
462#define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
463#define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
464#define TARGET_INTER_UNIT_MOVES_TO_VEC \
465 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC]
466#define TARGET_INTER_UNIT_MOVES_FROM_VEC \
467 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC]
468#define TARGET_INTER_UNIT_CONVERSIONS \
469 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
470#define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
471#define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
472#define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
473#define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
474#define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
475#define TARGET_PAD_SHORT_FUNCTION \
476 ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION]
477#define TARGET_EXT_80387_CONSTANTS \
478 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
479#define TARGET_AVOID_VECTOR_DECODE \
480 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
481#define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
482 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
483#define TARGET_SLOW_IMUL_IMM32_MEM \
484 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
485#define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
486#define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
487#define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
488#define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
489#define TARGET_USE_VECTOR_FP_CONVERTS \
490 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS]
491#define TARGET_USE_VECTOR_CONVERTS \
492 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
493#define TARGET_SLOW_PSHUFB \
494 ix86_tune_features[X86_TUNE_SLOW_PSHUFB]
495#define TARGET_AVOID_4BYTE_PREFIXES \
496 ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES]
497#define TARGET_FUSE_CMP_AND_BRANCH_32 \
498 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32]
499#define TARGET_FUSE_CMP_AND_BRANCH_64 \
500 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64]
501#define TARGET_FUSE_CMP_AND_BRANCH \
502 (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \
503 : TARGET_FUSE_CMP_AND_BRANCH_32)
504#define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \
505 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS]
506#define TARGET_FUSE_ALU_AND_BRANCH \
507 ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH]
508#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
509#define TARGET_AVOID_LEA_FOR_ADDR \
510 ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR]
511#define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \
512 ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL]
513#define TARGET_AVX128_OPTIMAL \
514 ix86_tune_features[X86_TUNE_AVX128_OPTIMAL]
515#define TARGET_GENERAL_REGS_SSE_SPILL \
516 ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL]
517#define TARGET_AVOID_MEM_OPND_FOR_CMOVE \
518 ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE]
519#define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \
520 ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS]
521#define TARGET_ADJUST_UNROLL \
522 ix86_tune_features[X86_TUNE_ADJUST_UNROLL]
523#define TARGET_AVOID_FALSE_DEP_FOR_BMI \
524 ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI]
525#define TARGET_ONE_IF_CONV_INSN \
526 ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN]
527#define TARGET_EMIT_VZEROUPPER \
528 ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER]
529
530/* Feature tests against the various architecture variations. */
531enum ix86_arch_indices {
532 X86_ARCH_CMOV,
533 X86_ARCH_CMPXCHG,
534 X86_ARCH_CMPXCHG8B,
535 X86_ARCH_XADD,
536 X86_ARCH_BSWAP,
537
538 X86_ARCH_LAST
539};
540
541extern unsigned char ix86_arch_features[X86_ARCH_LAST];
542
543#define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV]
544#define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
545#define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
546#define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
547#define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
548
549/* For sane SSE instruction set generation we need fcomi instruction.
550 It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
551 expands to a sequence that includes conditional move. */
552#define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND)
553
554#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
555
556extern unsigned char x86_prefetch_sse;
557#define TARGET_PREFETCH_SSE x86_prefetch_sse
558
559#define ASSEMBLER_DIALECT (ix86_asm_dialect)
560
561#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
562#define TARGET_MIX_SSE_I387 \
563 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
564
565#define TARGET_HARD_SF_REGS (TARGET_80387 || TARGET_MMX || TARGET_SSE)
566#define TARGET_HARD_DF_REGS (TARGET_80387 || TARGET_SSE)
567#define TARGET_HARD_XF_REGS (TARGET_80387)
568
569#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
570#define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
571#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
572#define TARGET_SUN_TLS 0
573
574#ifndef TARGET_64BIT_DEFAULT
575#define TARGET_64BIT_DEFAULT 0
576#endif
577#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
578#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
579#endif
580
581#define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL)
582#define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS)
583
584/* Fence to use after loop using storent. */
585
586extern tree x86_mfence;
587#define FENCE_FOLLOWING_MOVNT x86_mfence
588
589/* Once GDB has been enhanced to deal with functions without frame
590 pointers, we can change this to allow for elimination of
591 the frame pointer in leaf functions. */
592#define TARGET_DEFAULT 0
593
594/* Extra bits to force. */
595#define TARGET_SUBTARGET_DEFAULT 0
596#define TARGET_SUBTARGET_ISA_DEFAULT 0
597
598/* Extra bits to force on w/ 32-bit mode. */
599#define TARGET_SUBTARGET32_DEFAULT 0
600#define TARGET_SUBTARGET32_ISA_DEFAULT 0
601
602/* Extra bits to force on w/ 64-bit mode. */
603#define TARGET_SUBTARGET64_DEFAULT 0
604#define TARGET_SUBTARGET64_ISA_DEFAULT 0
605
606/* Replace MACH-O, ifdefs by in-line tests, where possible.
607 (a) Macros defined in config/i386/darwin.h */
608#define TARGET_MACHO 0
609#define TARGET_MACHO_BRANCH_ISLANDS 0
610#define MACHOPIC_ATT_STUB 0
611/* (b) Macros defined in config/darwin.h */
612#define MACHO_DYNAMIC_NO_PIC_P 0
613#define MACHOPIC_INDIRECT 0
614#define MACHOPIC_PURE 0
615
616/* For the RDOS */
617#define TARGET_RDOS 0
618
619/* For the Windows 64-bit ABI. */
620#define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
621
622/* For the Windows 32-bit ABI. */
623#define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
624
625/* This is re-defined by cygming.h. */
626#define TARGET_SEH 0
627
628/* The default abi used by target. */
629#define DEFAULT_ABI SYSV_ABI
630
631/* The default TLS segment register used by target. */
632#define DEFAULT_TLS_SEG_REG \
633 (TARGET_64BIT ? ADDR_SPACE_SEG_FS : ADDR_SPACE_SEG_GS)
634
635/* Subtargets may reset this to 1 in order to enable 96-bit long double
636 with the rounding mode forced to 53 bits. */
637#define TARGET_96_ROUND_53_LONG_DOUBLE 0
638
639/* -march=native handling only makes sense with compiler running on
640 an x86 or x86_64 chip. If changing this condition, also change
641 the condition in driver-i386.c. */
642#if defined(__i386__) || defined(__x86_64__)
643/* In driver-i386.c. */
644extern const char *host_detect_local_cpu (int argc, const char **argv);
645#define EXTRA_SPEC_FUNCTIONS \
646 { "local_cpu_detect", host_detect_local_cpu },
647#define HAVE_LOCAL_CPU_DETECT
648#endif
649
650#if TARGET_64BIT_DEFAULT
651#define OPT_ARCH64 "!m32"
652#define OPT_ARCH32 "m32"
653#else
654#define OPT_ARCH64 "m64|mx32"
655#define OPT_ARCH32 "m64|mx32:;"
656#endif
657
658/* Support for configure-time defaults of some command line options.
659 The order here is important so that -march doesn't squash the
660 tune or cpu values. */
661#define OPTION_DEFAULT_SPECS \
662 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
663 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
664 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
665 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
666 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
667 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
668 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
669 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \
670 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"},
671
672/* Specs for the compiler proper */
673
674#ifndef CC1_CPU_SPEC
675#define CC1_CPU_SPEC_1 ""
676
677#ifndef HAVE_LOCAL_CPU_DETECT
678#define CC1_CPU_SPEC CC1_CPU_SPEC_1
679#else
680#define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
681"%{march=native:%>march=native %:local_cpu_detect(arch) \
682 %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \
683%{mtune=native:%>mtune=native %:local_cpu_detect(tune)}"
684#endif
685#endif
686
687/* Target CPU builtins. */
688#define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
689
690/* Target Pragmas. */
691#define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
692
693#ifndef CC1_SPEC
694#define CC1_SPEC "%(cc1_cpu) "
695#endif
696
697/* This macro defines names of additional specifications to put in the
698 specs that can be used in various specifications like CC1_SPEC. Its
699 definition is an initializer with a subgrouping for each command option.
700
701 Each subgrouping contains a string constant, that defines the
702 specification name, and a string constant that used by the GCC driver
703 program.
704
705 Do not define this macro if it does not need to do anything. */
706
707#ifndef SUBTARGET_EXTRA_SPECS
708#define SUBTARGET_EXTRA_SPECS
709#endif
710
711#define EXTRA_SPECS \
712 { "cc1_cpu", CC1_CPU_SPEC }, \
713 SUBTARGET_EXTRA_SPECS
714
715
716/* Whether to allow x87 floating-point arithmetic on MODE (one of
717 SFmode, DFmode and XFmode) in the current excess precision
718 configuration. */
719#define X87_ENABLE_ARITH(MODE) \
720 (flag_unsafe_math_optimizations \
721 || flag_excess_precision == EXCESS_PRECISION_FAST \
722 || (MODE) == XFmode)
723
724/* Likewise, whether to allow direct conversions from integer mode
725 IMODE (HImode, SImode or DImode) to MODE. */
726#define X87_ENABLE_FLOAT(MODE, IMODE) \
727 (flag_unsafe_math_optimizations \
728 || flag_excess_precision == EXCESS_PRECISION_FAST \
729 || (MODE) == XFmode \
730 || ((MODE) == DFmode && (IMODE) == SImode) \
731 || (IMODE) == HImode)
732
733/* target machine storage layout */
734
735#define SHORT_TYPE_SIZE 16
736#define INT_TYPE_SIZE 32
737#define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
738#define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
739#define LONG_LONG_TYPE_SIZE 64
740#define FLOAT_TYPE_SIZE 32
741#define DOUBLE_TYPE_SIZE 64
742#define LONG_DOUBLE_TYPE_SIZE \
743 (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80))
744
745#define WIDEST_HARDWARE_FP_SIZE 80
746
747#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
748#define MAX_BITS_PER_WORD 64
749#else
750#define MAX_BITS_PER_WORD 32
751#endif
752
753/* Define this if most significant byte of a word is the lowest numbered. */
754/* That is true on the 80386. */
755
756#define BITS_BIG_ENDIAN 0
757
758/* Define this if most significant byte of a word is the lowest numbered. */
759/* That is not true on the 80386. */
760#define BYTES_BIG_ENDIAN 0
761
762/* Define this if most significant word of a multiword number is the lowest
763 numbered. */
764/* Not true for 80386 */
765#define WORDS_BIG_ENDIAN 0
766
767/* Width of a word, in units (bytes). */
768#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
769
770#ifndef IN_LIBGCC2
771#define MIN_UNITS_PER_WORD 4
772#endif
773
774/* Allocation boundary (in *bits*) for storing arguments in argument list. */
775#define PARM_BOUNDARY BITS_PER_WORD
776
777/* Boundary (in *bits*) on which stack pointer should be aligned. */
778#define STACK_BOUNDARY \
779 (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD)
780
781/* Stack boundary of the main function guaranteed by OS. */
782#define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
783
784/* Minimum stack boundary. */
785#define MIN_STACK_BOUNDARY BITS_PER_WORD
786
787/* Boundary (in *bits*) on which the stack pointer prefers to be
788 aligned; the compiler cannot rely on having this alignment. */
789#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
790
791/* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for
792 both 32bit and 64bit, to support codes that need 128 bit stack
793 alignment for SSE instructions, but can't realign the stack. */
794#define PREFERRED_STACK_BOUNDARY_DEFAULT \
795 (TARGET_IAMCU ? MIN_STACK_BOUNDARY : 128)
796
797/* 1 if -mstackrealign should be turned on by default. It will
798 generate an alternate prologue and epilogue that realigns the
799 runtime stack if nessary. This supports mixing codes that keep a
800 4-byte aligned stack, as specified by i386 psABI, with codes that
801 need a 16-byte aligned stack, as required by SSE instructions. */
802#define STACK_REALIGN_DEFAULT 0
803
804/* Boundary (in *bits*) on which the incoming stack is aligned. */
805#define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary
806
807/* According to Windows x64 software convention, the maximum stack allocatable
808 in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of
809 instructions allowed to adjust the stack pointer in the epilog, forcing the
810 use of frame pointer for frames larger than 2 GB. This theorical limit
811 is reduced by 256, an over-estimated upper bound for the stack use by the
812 prologue.
813 We define only one threshold for both the prolog and the epilog. When the
814 frame size is larger than this threshold, we allocate the area to save SSE
815 regs, then save them, and then allocate the remaining. There is no SEH
816 unwind info for this later allocation. */
817#define SEH_MAX_FRAME_SIZE ((2U << 30) - 256)
818
819/* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
820 mandatory for the 64-bit ABI, and may or may not be true for other
821 operating systems. */
822#define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
823
824/* Minimum allocation boundary for the code of a function. */
825#define FUNCTION_BOUNDARY 8
826
827/* C++ stores the virtual bit in the lowest bit of function pointers. */
828#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
829
830/* Minimum size in bits of the largest boundary to which any
831 and all fundamental data types supported by the hardware
832 might need to be aligned. No data type wants to be aligned
833 rounder than this.
834
835 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
836 and Pentium Pro XFmode values at 128 bit boundaries.
837
838 When increasing the maximum, also update
839 TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */
840
841#define BIGGEST_ALIGNMENT \
842 (TARGET_IAMCU ? 32 : (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128)))
843
844/* Maximum stack alignment. */
845#define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
846
847/* Alignment value for attribute ((aligned)). It is a constant since
848 it is the part of the ABI. We shouldn't change it with -mavx. */
849#define ATTRIBUTE_ALIGNED_VALUE (TARGET_IAMCU ? 32 : 128)
850
851/* Decide whether a variable of mode MODE should be 128 bit aligned. */
852#define ALIGN_MODE_128(MODE) \
853 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
854
855/* The published ABIs say that doubles should be aligned on word
856 boundaries, so lower the alignment for structure fields unless
857 -malign-double is set. */
858
859/* ??? Blah -- this macro is used directly by libobjc. Since it
860 supports no vector modes, cut out the complexity and fall back
861 on BIGGEST_FIELD_ALIGNMENT. */
862#ifdef IN_TARGET_LIBS
863#ifdef __x86_64__
864#define BIGGEST_FIELD_ALIGNMENT 128
865#else
866#define BIGGEST_FIELD_ALIGNMENT 32
867#endif
868#else
869#define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \
870 x86_field_alignment ((TYPE), (COMPUTED))
871#endif
872
873/* If defined, a C expression to compute the alignment for a static
874 variable. TYPE is the data type, and ALIGN is the alignment that
875 the object would ordinarily have. The value of this macro is used
876 instead of that alignment to align the object.
877
878 If this macro is not defined, then ALIGN is used.
879
880 One use of this macro is to increase alignment of medium-size
881 data to make it all fit in fewer cache lines. Another is to
882 cause character arrays to be word-aligned so that `strcpy' calls
883 that copy constants to character arrays can be done inline. */
884
885#define DATA_ALIGNMENT(TYPE, ALIGN) \
886 ix86_data_alignment ((TYPE), (ALIGN), true)
887
888/* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates
889 some alignment increase, instead of optimization only purposes. E.g.
890 AMD x86-64 psABI says that variables with array type larger than 15 bytes
891 must be aligned to 16 byte boundaries.
892
893 If this macro is not defined, then ALIGN is used. */
894
895#define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
896 ix86_data_alignment ((TYPE), (ALIGN), false)
897
898/* If defined, a C expression to compute the alignment for a local
899 variable. TYPE is the data type, and ALIGN is the alignment that
900 the object would ordinarily have. The value of this macro is used
901 instead of that alignment to align the object.
902
903 If this macro is not defined, then ALIGN is used.
904
905 One use of this macro is to increase alignment of medium-size
906 data to make it all fit in fewer cache lines. */
907
908#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
909 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))
910
911/* If defined, a C expression to compute the alignment for stack slot.
912 TYPE is the data type, MODE is the widest mode available, and ALIGN
913 is the alignment that the slot would ordinarily have. The value of
914 this macro is used instead of that alignment to align the slot.
915
916 If this macro is not defined, then ALIGN is used when TYPE is NULL,
917 Otherwise, LOCAL_ALIGNMENT will be used.
918
919 One use of this macro is to set alignment of stack slot to the
920 maximum alignment of all possible modes which the slot may have. */
921
922#define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \
923 ix86_local_alignment ((TYPE), (MODE), (ALIGN))
924
925/* If defined, a C expression to compute the alignment for a local
926 variable DECL.
927
928 If this macro is not defined, then
929 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used.
930
931 One use of this macro is to increase alignment of medium-size
932 data to make it all fit in fewer cache lines. */
933
934#define LOCAL_DECL_ALIGNMENT(DECL) \
935 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL))
936
937/* If defined, a C expression to compute the minimum required alignment
938 for dynamic stack realignment purposes for EXP (a TYPE or DECL),
939 MODE, assuming normal alignment ALIGN.
940
941 If this macro is not defined, then (ALIGN) will be used. */
942
943#define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \
944 ix86_minimum_alignment ((EXP), (MODE), (ALIGN))
945
946
947/* Set this nonzero if move instructions will actually fail to work
948 when given unaligned data. */
949#define STRICT_ALIGNMENT 0
950
951/* If bit field type is int, don't let it cross an int,
952 and give entire struct the alignment of an int. */
953/* Required on the 386 since it doesn't have bit-field insns. */
954#define PCC_BITFIELD_TYPE_MATTERS 1
955
956/* Standard register usage. */
957
958/* This processor has special stack-like registers. See reg-stack.c
959 for details. */
960
961#define STACK_REGS
962
963#define IS_STACK_MODE(MODE) \
964 (X87_FLOAT_MODE_P (MODE) \
965 && (!(SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \
966 || TARGET_MIX_SSE_I387))
967
968/* Number of actual hardware registers.
969 The hardware registers are assigned numbers for the compiler
970 from 0 to just below FIRST_PSEUDO_REGISTER.
971 All registers that the compiler knows about must be given numbers,
972 even those that are not normally considered general registers.
973
974 In the 80386 we give the 8 general purpose registers the numbers 0-7.
975 We number the floating point registers 8-15.
976 Note that registers 0-7 can be accessed as a short or int,
977 while only 0-3 may be used with byte `mov' instructions.
978
979 Reg 16 does not correspond to any hardware register, but instead
980 appears in the RTL as an argument pointer prior to reload, and is
981 eliminated during reloading in favor of either the stack or frame
982 pointer. */
983
984#define FIRST_PSEUDO_REGISTER FIRST_PSEUDO_REG
985
986/* Number of hardware registers that go into the DWARF-2 unwind info.
987 If not defined, equals FIRST_PSEUDO_REGISTER. */
988
989#define DWARF_FRAME_REGISTERS 17
990
991/* 1 for registers that have pervasive standard uses
992 and are not available for the register allocator.
993 On the 80386, the stack pointer is such, as is the arg pointer.
994
995 REX registers are disabled for 32bit targets in
996 TARGET_CONDITIONAL_REGISTER_USAGE. */
997
998#define FIXED_REGISTERS \
999/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
1000{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
1001/*arg,flags,fpsr,fpcr,frame*/ \
1002 1, 1, 1, 1, 1, \
1003/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
1004 0, 0, 0, 0, 0, 0, 0, 0, \
1005/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
1006 0, 0, 0, 0, 0, 0, 0, 0, \
1007/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
1008 0, 0, 0, 0, 0, 0, 0, 0, \
1009/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
1010 0, 0, 0, 0, 0, 0, 0, 0, \
1011/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
1012 0, 0, 0, 0, 0, 0, 0, 0, \
1013/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
1014 0, 0, 0, 0, 0, 0, 0, 0, \
1015/* k0, k1, k2, k3, k4, k5, k6, k7*/ \
1016 0, 0, 0, 0, 0, 0, 0, 0, \
1017/* b0, b1, b2, b3*/ \
1018 0, 0, 0, 0 }
1019
1020/* 1 for registers not available across function calls.
1021 These must include the FIXED_REGISTERS and also any
1022 registers that can be used without being saved.
1023 The latter must include the registers where values are returned
1024 and the register where structure-value addresses are passed.
1025 Aside from that, you can include as many other registers as you like.
1026
1027 Value is set to 1 if the register is call used unconditionally.
1028 Bit one is set if the register is call used on TARGET_32BIT ABI.
1029 Bit two is set if the register is call used on TARGET_64BIT ABI.
1030 Bit three is set if the register is call used on TARGET_64BIT_MS_ABI.
1031
1032 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */
1033
1034#define CALL_USED_REGISTERS_MASK(IS_64BIT_MS_ABI) \
1035 ((IS_64BIT_MS_ABI) ? (1 << 3) : TARGET_64BIT ? (1 << 2) : (1 << 1))
1036
1037#define CALL_USED_REGISTERS \
1038/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
1039{ 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1040/*arg,flags,fpsr,fpcr,frame*/ \
1041 1, 1, 1, 1, 1, \
1042/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
1043 1, 1, 1, 1, 1, 1, 6, 6, \
1044/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
1045 1, 1, 1, 1, 1, 1, 1, 1, \
1046/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
1047 1, 1, 1, 1, 2, 2, 2, 2, \
1048/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
1049 6, 6, 6, 6, 6, 6, 6, 6, \
1050/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
1051 6, 6, 6, 6, 6, 6, 6, 6, \
1052/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
1053 6, 6, 6, 6, 6, 6, 6, 6, \
1054 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \
1055 1, 1, 1, 1, 1, 1, 1, 1, \
1056/* b0, b1, b2, b3*/ \
1057 1, 1, 1, 1 }
1058
1059/* Order in which to allocate registers. Each register must be
1060 listed once, even those in FIXED_REGISTERS. List frame pointer
1061 late and fixed registers last. Note that, in general, we prefer
1062 registers listed in CALL_USED_REGISTERS, keeping the others
1063 available for storage of persistent values.
1064
1065 The ADJUST_REG_ALLOC_ORDER actually overwrite the order,
1066 so this is just empty initializer for array. */
1067
1068#define REG_ALLOC_ORDER \
1069{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
1070 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
1071 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1072 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \
1073 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, \
1074 78, 79, 80 }
1075
1076/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1077 to be rearranged based on a particular function. When using sse math,
1078 we want to allocate SSE before x87 registers and vice versa. */
1079
1080#define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc ()
1081
1082
1083#define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
1084
1085#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
1086 (TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT \
1087 && GENERAL_REGNO_P (REGNO) \
1088 && ((MODE) == XFmode || (MODE) == XCmode))
1089
1090#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1091
1092#define VALID_AVX256_REG_MODE(MODE) \
1093 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1094 || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \
1095 || (MODE) == V4DFmode)
1096
1097#define VALID_AVX256_REG_OR_OI_MODE(MODE) \
1098 (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode)
1099
1100#define VALID_AVX512F_SCALAR_MODE(MODE) \
1101 ((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode \
1102 || (MODE) == SFmode)
1103
1104#define VALID_AVX512F_REG_MODE(MODE) \
1105 ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \
1106 || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \
1107 || (MODE) == V4TImode)
1108
1109#define VALID_AVX512F_REG_OR_XI_MODE(MODE) \
1110 (VALID_AVX512F_REG_MODE (MODE) || (MODE) == XImode)
1111
1112#define VALID_AVX512VL_128_REG_MODE(MODE) \
1113 ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \
1114 || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \
1115 || (MODE) == TFmode || (MODE) == V1TImode)
1116
1117#define VALID_SSE2_REG_MODE(MODE) \
1118 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1119 || (MODE) == V2DImode || (MODE) == DFmode)
1120
1121#define VALID_SSE_REG_MODE(MODE) \
1122 ((MODE) == V1TImode || (MODE) == TImode \
1123 || (MODE) == V4SFmode || (MODE) == V4SImode \
1124 || (MODE) == SFmode || (MODE) == TFmode)
1125
1126#define VALID_MMX_REG_MODE_3DNOW(MODE) \
1127 ((MODE) == V2SFmode || (MODE) == SFmode)
1128
1129#define VALID_MMX_REG_MODE(MODE) \
1130 ((MODE == V1DImode) || (MODE) == DImode \
1131 || (MODE) == V2SImode || (MODE) == SImode \
1132 || (MODE) == V4HImode || (MODE) == V8QImode)
1133
1134#define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode)
1135
1136#define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode)
1137
1138#define VALID_BND_REG_MODE(MODE) \
1139 (TARGET_64BIT ? (MODE) == BND64mode : (MODE) == BND32mode)
1140
1141#define VALID_DFP_MODE_P(MODE) \
1142 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)
1143
1144#define VALID_FP_MODE_P(MODE) \
1145 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1146 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1147
1148#define VALID_INT_MODE_P(MODE) \
1149 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1150 || (MODE) == DImode \
1151 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1152 || (MODE) == CDImode \
1153 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1154 || (MODE) == TFmode || (MODE) == TCmode)))
1155
1156/* Return true for modes passed in SSE registers. */
1157#define SSE_REG_MODE_P(MODE) \
1158 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \
1159 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \
1160 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1161 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1162 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \
1163 || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \
1164 || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \
1165 || (MODE) == V16SFmode)
1166
1167#define X87_FLOAT_MODE_P(MODE) \
1168 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1169
1170#define SSE_FLOAT_MODE_P(MODE) \
1171 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1172
1173#define FMA4_VEC_FLOAT_MODE_P(MODE) \
1174 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
1175 || (MODE) == V8SFmode || (MODE) == V4DFmode))
1176
1177/* It is possible to write patterns to move flags; but until someone
1178 does it, */
1179#define AVOID_CCMODE_COPIES
1180
1181/* Specify the modes required to caller save a given hard regno.
1182 We do this on i386 to prevent flags from being saved at all.
1183
1184 Kill any attempts to combine saving of modes. */
1185
1186#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1187 (CC_REGNO_P (REGNO) ? VOIDmode \
1188 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1189 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \
1190 : (MODE) == HImode && !((GENERAL_REGNO_P (REGNO) \
1191 && TARGET_PARTIAL_REG_STALL) \
1192 || MASK_REGNO_P (REGNO)) ? SImode \
1193 : (MODE) == QImode && !(ANY_QI_REGNO_P (REGNO) \
1194 || MASK_REGNO_P (REGNO)) ? SImode \
1195 : (MODE))
1196
1197/* Specify the registers used for certain standard purposes.
1198 The values of these macros are register numbers. */
1199
1200/* on the 386 the pc register is %eip, and is not usable as a general
1201 register. The ordinary mov instructions won't work */
1202/* #define PC_REGNUM */
1203
1204/* Base register for access to arguments of the function. */
1205#define ARG_POINTER_REGNUM ARGP_REG
1206
1207/* Register to use for pushing function arguments. */
1208#define STACK_POINTER_REGNUM SP_REG
1209
1210/* Base register for access to local variables of the function. */
1211#define FRAME_POINTER_REGNUM FRAME_REG
1212#define HARD_FRAME_POINTER_REGNUM BP_REG
1213
1214#define FIRST_INT_REG AX_REG
1215#define LAST_INT_REG SP_REG
1216
1217#define FIRST_QI_REG AX_REG
1218#define LAST_QI_REG BX_REG
1219
1220/* First & last stack-like regs */
1221#define FIRST_STACK_REG ST0_REG
1222#define LAST_STACK_REG ST7_REG
1223
1224#define FIRST_SSE_REG XMM0_REG
1225#define LAST_SSE_REG XMM7_REG
1226
1227#define FIRST_MMX_REG MM0_REG
1228#define LAST_MMX_REG MM7_REG
1229
1230#define FIRST_REX_INT_REG R8_REG
1231#define LAST_REX_INT_REG R15_REG
1232
1233#define FIRST_REX_SSE_REG XMM8_REG
1234#define LAST_REX_SSE_REG XMM15_REG
1235
1236#define FIRST_EXT_REX_SSE_REG XMM16_REG
1237#define LAST_EXT_REX_SSE_REG XMM31_REG
1238
1239#define FIRST_MASK_REG MASK0_REG
1240#define LAST_MASK_REG MASK7_REG
1241
1242#define FIRST_BND_REG BND0_REG
1243#define LAST_BND_REG BND3_REG
1244
1245/* Override this in other tm.h files to cope with various OS lossage
1246 requiring a frame pointer. */
1247#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1248#define SUBTARGET_FRAME_POINTER_REQUIRED 0
1249#endif
1250
1251/* Make sure we can access arbitrary call frames. */
1252#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1253
1254/* Register to hold the addressing base for position independent
1255 code access to data items. We don't use PIC pointer for 64bit
1256 mode. Define the regnum to dummy value to prevent gcc from
1257 pessimizing code dealing with EBX.
1258
1259 To avoid clobbering a call-saved register unnecessarily, we renumber
1260 the pic register when possible. The change is visible after the
1261 prologue has been emitted. */
1262
1263#define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG)
1264
1265#define PIC_OFFSET_TABLE_REGNUM \
1266 (ix86_use_pseudo_pic_reg () \
1267 ? (pic_offset_table_rtx \
1268 ? INVALID_REGNUM \
1269 : REAL_PIC_OFFSET_TABLE_REGNUM) \
1270 : INVALID_REGNUM)
1271
1272#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1273
1274/* This is overridden by <cygwin.h>. */
1275#define MS_AGGREGATE_RETURN 0
1276
1277#define KEEP_AGGREGATE_RETURN_POINTER 0
1278
1279/* Define the classes of registers for register constraints in the
1280 machine description. Also define ranges of constants.
1281
1282 One of the classes must always be named ALL_REGS and include all hard regs.
1283 If there is more than one class, another class must be named NO_REGS
1284 and contain no registers.
1285
1286 The name GENERAL_REGS must be the name of a class (or an alias for
1287 another name such as ALL_REGS). This is the class of registers
1288 that is allowed by "g" or "r" in a register constraint.
1289 Also, registers outside this class are allocated only when
1290 instructions express preferences for them.
1291
1292 The classes must be numbered in nondecreasing order; that is,
1293 a larger-numbered class must never be contained completely
1294 in a smaller-numbered class. This is why CLOBBERED_REGS class
1295 is listed early, even though in 64-bit mode it contains more
1296 registers than just %eax, %ecx, %edx.
1297
1298 For any two classes, it is very desirable that there be another
1299 class that represents their union.
1300
1301 It might seem that class BREG is unnecessary, since no useful 386
1302 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1303 and the "b" register constraint is useful in asms for syscalls.
1304
1305 The flags, fpsr and fpcr registers are in no class. */
1306
1307enum reg_class
1308{
1309 NO_REGS,
1310 AREG, DREG, CREG, BREG, SIREG, DIREG,
1311 AD_REGS, /* %eax/%edx for DImode */
1312 CLOBBERED_REGS, /* call-clobbered integer registers */
1313 Q_REGS, /* %eax %ebx %ecx %edx */
1314 NON_Q_REGS, /* %esi %edi %ebp %esp */
1315 TLS_GOTBASE_REGS, /* %ebx %ecx %edx %esi %edi %ebp */
1316 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1317 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1318 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp
1319 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
1320 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1321 FLOAT_REGS,
1322 SSE_FIRST_REG,
1323 NO_REX_SSE_REGS,
1324 SSE_REGS,
1325 EVEX_SSE_REGS,
1326 BND_REGS,
1327 ALL_SSE_REGS,
1328 MMX_REGS,
1329 FP_TOP_SSE_REGS,
1330 FP_SECOND_SSE_REGS,
1331 FLOAT_SSE_REGS,
1332 FLOAT_INT_REGS,
1333 INT_SSE_REGS,
1334 FLOAT_INT_SSE_REGS,
1335 MASK_EVEX_REGS,
1336 MASK_REGS,
1337 MOD4_SSE_REGS,
1338 ALL_REGS, LIM_REG_CLASSES
1339};
1340
1341#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1342
1343#define INTEGER_CLASS_P(CLASS) \
1344 reg_class_subset_p ((CLASS), GENERAL_REGS)
1345#define FLOAT_CLASS_P(CLASS) \
1346 reg_class_subset_p ((CLASS), FLOAT_REGS)
1347#define SSE_CLASS_P(CLASS) \
1348 reg_class_subset_p ((CLASS), ALL_SSE_REGS)
1349#define MMX_CLASS_P(CLASS) \
1350 ((CLASS) == MMX_REGS)
1351#define MASK_CLASS_P(CLASS) \
1352 reg_class_subset_p ((CLASS), MASK_REGS)
1353#define MAYBE_INTEGER_CLASS_P(CLASS) \
1354 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1355#define MAYBE_FLOAT_CLASS_P(CLASS) \
1356 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1357#define MAYBE_SSE_CLASS_P(CLASS) \
1358 reg_classes_intersect_p ((CLASS), ALL_SSE_REGS)
1359#define MAYBE_MMX_CLASS_P(CLASS) \
1360 reg_classes_intersect_p ((CLASS), MMX_REGS)
1361#define MAYBE_MASK_CLASS_P(CLASS) \
1362 reg_classes_intersect_p ((CLASS), MASK_REGS)
1363
1364#define Q_CLASS_P(CLASS) \
1365 reg_class_subset_p ((CLASS), Q_REGS)
1366
1367#define MAYBE_NON_Q_CLASS_P(CLASS) \
1368 reg_classes_intersect_p ((CLASS), NON_Q_REGS)
1369
1370/* Give names of register classes as strings for dump file. */
1371
1372#define REG_CLASS_NAMES \
1373{ "NO_REGS", \
1374 "AREG", "DREG", "CREG", "BREG", \
1375 "SIREG", "DIREG", \
1376 "AD_REGS", \
1377 "CLOBBERED_REGS", \
1378 "Q_REGS", "NON_Q_REGS", \
1379 "TLS_GOTBASE_REGS", \
1380 "INDEX_REGS", \
1381 "LEGACY_REGS", \
1382 "GENERAL_REGS", \
1383 "FP_TOP_REG", "FP_SECOND_REG", \
1384 "FLOAT_REGS", \
1385 "SSE_FIRST_REG", \
1386 "NO_REX_SSE_REGS", \
1387 "SSE_REGS", \
1388 "EVEX_SSE_REGS", \
1389 "BND_REGS", \
1390 "ALL_SSE_REGS", \
1391 "MMX_REGS", \
1392 "FP_TOP_SSE_REGS", \
1393 "FP_SECOND_SSE_REGS", \
1394 "FLOAT_SSE_REGS", \
1395 "FLOAT_INT_REGS", \
1396 "INT_SSE_REGS", \
1397 "FLOAT_INT_SSE_REGS", \
1398 "MASK_EVEX_REGS", \
1399 "MASK_REGS", \
1400 "MOD4_SSE_REGS", \
1401 "ALL_REGS" }
1402
1403/* Define which registers fit in which classes. This is an initializer
1404 for a vector of HARD_REG_SET of length N_REG_CLASSES.
1405
1406 Note that CLOBBERED_REGS are calculated by
1407 TARGET_CONDITIONAL_REGISTER_USAGE. */
1408
1409#define REG_CLASS_CONTENTS \
1410{ { 0x00, 0x0, 0x0 }, \
1411 { 0x01, 0x0, 0x0 }, /* AREG */ \
1412 { 0x02, 0x0, 0x0 }, /* DREG */ \
1413 { 0x04, 0x0, 0x0 }, /* CREG */ \
1414 { 0x08, 0x0, 0x0 }, /* BREG */ \
1415 { 0x10, 0x0, 0x0 }, /* SIREG */ \
1416 { 0x20, 0x0, 0x0 }, /* DIREG */ \
1417 { 0x03, 0x0, 0x0 }, /* AD_REGS */ \
1418 { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \
1419 { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \
1420 { 0x1100f0, 0x1fe0, 0x0 }, /* NON_Q_REGS */ \
1421 { 0x7e, 0x1fe0, 0x0 }, /* TLS_GOTBASE_REGS */ \
1422 { 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \
1423 { 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \
1424 { 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \
1425 { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
1426 { 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
1427 { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
1428 { 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \
1429{ 0x1fe00000, 0x000000, 0x0 }, /* NO_REX_SSE_REGS */ \
1430{ 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \
1431 { 0x0,0xffe00000, 0x1f }, /* EVEX_SSE_REGS */ \
1432 { 0x0, 0x0,0x1e000 }, /* BND_REGS */ \
1433{ 0x1fe00000,0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \
1434{ 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \
1435{ 0x1fe00100,0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \
1436{ 0x1fe00200,0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \
1437{ 0x1fe0ff00,0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \
1438{ 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \
1439{ 0x1ff100ff,0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \
1440{ 0x1ff1ffff,0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \
1441 { 0x0, 0x0, 0x1fc0 }, /* MASK_EVEX_REGS */ \
1442 { 0x0, 0x0, 0x1fe0 }, /* MASK_REGS */ \
1443{ 0x1fe00000,0xffffe000, 0x1f }, /* MOD4_SSE_REGS */ \
1444{ 0xffffffff,0xffffffff,0x1ffff } \
1445}
1446
1447/* The same information, inverted:
1448 Return the class number of the smallest class containing
1449 reg number REGNO. This could be a conditional expression
1450 or could index an array. */
1451
1452#define REGNO_REG_CLASS(REGNO) (regclass_map[(REGNO)])
1453
1454/* When this hook returns true for MODE, the compiler allows
1455 registers explicitly used in the rtl to be used as spill registers
1456 but prevents the compiler from extending the lifetime of these
1457 registers. */
1458#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
1459
1460#define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X)))
1461#define QI_REGNO_P(N) IN_RANGE ((N), FIRST_QI_REG, LAST_QI_REG)
1462
1463#define LEGACY_INT_REG_P(X) (REG_P (X) && LEGACY_INT_REGNO_P (REGNO (X)))
1464#define LEGACY_INT_REGNO_P(N) (IN_RANGE ((N), FIRST_INT_REG, LAST_INT_REG))
1465
1466#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1467#define REX_INT_REGNO_P(N) \
1468 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1469
1470#define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1471#define GENERAL_REGNO_P(N) \
1472 (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N))
1473
1474#define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X)))
1475#define ANY_QI_REGNO_P(N) \
1476 (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N))
1477
1478#define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X)))
1479#define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1480
1481#define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X)))
1482#define SSE_REGNO_P(N) \
1483 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1484 || REX_SSE_REGNO_P (N) \
1485 || EXT_REX_SSE_REGNO_P (N))
1486
1487#define REX_SSE_REGNO_P(N) \
1488 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1489
1490#define EXT_REX_SSE_REG_P(X) (REG_P (X) && EXT_REX_SSE_REGNO_P (REGNO (X)))
1491
1492#define EXT_REX_SSE_REGNO_P(N) \
1493 IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG)
1494
1495#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1496#define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N))
1497
1498#define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X)))
1499#define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG)
1500
1501#define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X)))
1502#define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1503
1504#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1505#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1506
1507#define BND_REG_P(X) (REG_P (X) && BND_REGNO_P (REGNO (X)))
1508#define BND_REGNO_P(N) IN_RANGE ((N), FIRST_BND_REG, LAST_BND_REG)
1509
1510#define MOD4_SSE_REG_P(X) (REG_P (X) && MOD4_SSE_REGNO_P (REGNO (X)))
1511#define MOD4_SSE_REGNO_P(N) ((N) == XMM0_REG \
1512 || (N) == XMM4_REG \
1513 || (N) == XMM8_REG \
1514 || (N) == XMM12_REG \
1515 || (N) == XMM16_REG \
1516 || (N) == XMM20_REG \
1517 || (N) == XMM24_REG \
1518 || (N) == XMM28_REG)
1519
1520/* First floating point reg */
1521#define FIRST_FLOAT_REG FIRST_STACK_REG
1522#define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG)
1523
1524#define SSE_REGNO(N) \
1525 ((N) < 8 ? FIRST_SSE_REG + (N) \
1526 : (N) <= LAST_REX_SSE_REG ? (FIRST_REX_SSE_REG + (N) - 8) \
1527 : (FIRST_EXT_REX_SSE_REG + (N) - 16))
1528
1529/* The class value for index registers, and the one for base regs. */
1530
1531#define INDEX_REG_CLASS INDEX_REGS
1532#define BASE_REG_CLASS GENERAL_REGS
1533
1534/* Stack layout; function entry, exit and calling. */
1535
1536/* Define this if pushing a word on the stack
1537 makes the stack pointer a smaller address. */
1538#define STACK_GROWS_DOWNWARD 1
1539
1540/* Define this to nonzero if the nominal address of the stack frame
1541 is at the high-address end of the local variables;
1542 that is, each additional local variable allocated
1543 goes at a more negative offset in the frame. */
1544#define FRAME_GROWS_DOWNWARD 1
1545
1546/* If we generate an insn to push BYTES bytes, this says how many the stack
1547 pointer really advances by. On 386, we have pushw instruction that
1548 decrements by exactly 2 no matter what the position was, there is no pushb.
1549
1550 But as CIE data alignment factor on this arch is -4 for 32bit targets
1551 and -8 for 64bit targets, we need to make sure all stack pointer adjustments
1552 are in multiple of 4 for 32bit targets and 8 for 64bit targets. */
1553
1554#define PUSH_ROUNDING(BYTES) ROUND_UP ((BYTES), UNITS_PER_WORD)
1555
1556/* If defined, the maximum amount of space required for outgoing arguments
1557 will be computed and placed into the variable `crtl->outgoing_args_size'.
1558 No space will be pushed onto the stack for each call; instead, the
1559 function prologue should increase the stack frame size by this amount.
1560
1561 In 32bit mode enabling argument accumulation results in about 5% code size
1562 growth because move instructions are less compact than push. In 64bit
1563 mode the difference is less drastic but visible.
1564
1565 FIXME: Unlike earlier implementations, the size of unwind info seems to
1566 actually grow with accumulation. Is that because accumulated args
1567 unwind info became unnecesarily bloated?
1568
1569 With the 64-bit MS ABI, we can generate correct code with or without
1570 accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code
1571 generated without accumulated args is terrible.
1572
1573 If stack probes are required, the space used for large function
1574 arguments on the stack must also be probed, so enable
1575 -maccumulate-outgoing-args so this happens in the prologue.
1576
1577 We must use argument accumulation in interrupt function if stack
1578 may be realigned to avoid DRAP. */
1579
1580#define ACCUMULATE_OUTGOING_ARGS \
1581 ((TARGET_ACCUMULATE_OUTGOING_ARGS \
1582 && optimize_function_for_speed_p (cfun)) \
1583 || (cfun->machine->func_type != TYPE_NORMAL \
1584 && crtl->stack_realign_needed) \
1585 || TARGET_STACK_PROBE \
1586 || TARGET_64BIT_MS_ABI \
1587 || (TARGET_MACHO && crtl->profile))
1588
1589/* If defined, a C expression whose value is nonzero when we want to use PUSH
1590 instructions to pass outgoing arguments. */
1591
1592#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1593
1594/* We want the stack and args grow in opposite directions, even if
1595 PUSH_ARGS is 0. */
1596#define PUSH_ARGS_REVERSED 1
1597
1598/* Offset of first parameter from the argument pointer register value. */
1599#define FIRST_PARM_OFFSET(FNDECL) 0
1600
1601/* Define this macro if functions should assume that stack space has been
1602 allocated for arguments even when their values are passed in registers.
1603
1604 The value of this macro is the size, in bytes, of the area reserved for
1605 arguments passed in registers for the function represented by FNDECL.
1606
1607 This space can be allocated by the caller, or be a part of the
1608 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1609 which. */
1610#define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
1611
1612#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \
1613 (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI)
1614
1615/* Define how to find the value returned by a library function
1616 assuming the value has mode MODE. */
1617
1618#define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE)
1619
1620/* Define the size of the result block used for communication between
1621 untyped_call and untyped_return. The block contains a DImode value
1622 followed by the block used by fnsave and frstor. */
1623
1624#define APPLY_RESULT_SIZE (8+108)
1625
1626/* 1 if N is a possible register number for function argument passing. */
1627#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1628
1629/* Define a data type for recording info about an argument list
1630 during the scan of that argument list. This data type should
1631 hold all necessary information about the function itself
1632 and about the args processed so far, enough to enable macros
1633 such as FUNCTION_ARG to determine where the next arg should go. */
1634
1635typedef struct ix86_args {
1636 int words; /* # words passed so far */
1637 int nregs; /* # registers available for passing */
1638 int regno; /* next available register number */
1639 int fastcall; /* fastcall or thiscall calling convention
1640 is used */
1641 int sse_words; /* # sse words passed so far */
1642 int sse_nregs; /* # sse registers available for passing */
1643 int warn_avx512f; /* True when we want to warn
1644 about AVX512F ABI. */
1645 int warn_avx; /* True when we want to warn about AVX ABI. */
1646 int warn_sse; /* True when we want to warn about SSE ABI. */
1647 int warn_mmx; /* True when we want to warn about MMX ABI. */
1648 int warn_empty; /* True when we want to warn about empty classes
1649 passing ABI change. */
1650 int sse_regno; /* next available sse register number */
1651 int mmx_words; /* # mmx words passed so far */
1652 int mmx_nregs; /* # mmx registers available for passing */
1653 int mmx_regno; /* next available mmx register number */
1654 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1655 int caller; /* true if it is caller. */
1656 int float_in_sse; /* Set to 1 or 2 for 32bit targets if
1657 SFmode/DFmode arguments should be passed
1658 in SSE registers. Otherwise 0. */
1659 int bnd_regno; /* next available bnd register number */
1660 int bnds_in_bt; /* number of bounds expected in BT. */
1661 int force_bnd_pass; /* number of bounds expected for stdarg arg. */
1662 int stdarg; /* Set to 1 if function is stdarg. */
1663 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise
1664 MS_ABI for ms abi. */
1665 tree decl; /* Callee decl. */
1666} CUMULATIVE_ARGS;
1667
1668/* Initialize a variable CUM of type CUMULATIVE_ARGS
1669 for a call to a function whose data type is FNTYPE.
1670 For a library call, FNTYPE is 0. */
1671
1672#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1673 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \
1674 (N_NAMED_ARGS) != -1)
1675
1676/* Output assembler code to FILE to increment profiler label # LABELNO
1677 for profiling a function entry. */
1678
1679#define FUNCTION_PROFILER(FILE, LABELNO) \
1680 x86_function_profiler ((FILE), (LABELNO))
1681
1682#define MCOUNT_NAME "_mcount"
1683
1684#define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__"
1685
1686#define PROFILE_COUNT_REGISTER "edx"
1687
1688/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1689 the stack pointer does not matter. The value is tested only in
1690 functions that have frame pointers.
1691 No definition is equivalent to always zero. */
1692/* Note on the 386 it might be more efficient not to define this since
1693 we have to restore it ourselves from the frame pointer, in order to
1694 use pop */
1695
1696#define EXIT_IGNORE_STACK 1
1697
1698/* Define this macro as a C expression that is nonzero for registers
1699 used by the epilogue or the `return' pattern. */
1700
1701#define EPILOGUE_USES(REGNO) ix86_epilogue_uses (REGNO)
1702
1703/* Output assembler code for a block containing the constant parts
1704 of a trampoline, leaving space for the variable parts. */
1705
1706/* On the 386, the trampoline contains two instructions:
1707 mov #STATIC,ecx
1708 jmp FUNCTION
1709 The trampoline is generated entirely at runtime. The operand of JMP
1710 is the address of FUNCTION relative to the instruction following the
1711 JMP (which is 5 bytes long). */
1712
1713/* Length in units of the trampoline for entering a nested function. */
1714
1715#define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10)
1716
1717/* Definitions for register eliminations.
1718
1719 This is an array of structures. Each structure initializes one pair
1720 of eliminable registers. The "from" register number is given first,
1721 followed by "to". Eliminations of the same "from" register are listed
1722 in order of preference.
1723
1724 There are two registers that can always be eliminated on the i386.
1725 The frame pointer and the arg pointer can be replaced by either the
1726 hard frame pointer or to the stack pointer, depending upon the
1727 circumstances. The hard frame pointer is not used before reload and
1728 so it is not eligible for elimination. */
1729
1730#define ELIMINABLE_REGS \
1731{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1732 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1733 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1734 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1735
1736/* Define the offset between two registers, one to be eliminated, and the other
1737 its replacement, at the start of a routine. */
1738
1739#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1740 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1741
1742/* Addressing modes, and classification of registers for them. */
1743
1744/* Macros to check register numbers against specific register classes. */
1745
1746/* These assume that REGNO is a hard or pseudo reg number.
1747 They give nonzero only if REGNO is a hard reg of the suitable class
1748 or a pseudo reg currently allocated to a suitable hard reg.
1749 Since they use reg_renumber, they are safe only once reg_renumber
1750 has been allocated, which happens in reginfo.c during register
1751 allocation. */
1752
1753#define REGNO_OK_FOR_INDEX_P(REGNO) \
1754 ((REGNO) < STACK_POINTER_REGNUM \
1755 || REX_INT_REGNO_P (REGNO) \
1756 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1757 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1758
1759#define REGNO_OK_FOR_BASE_P(REGNO) \
1760 (GENERAL_REGNO_P (REGNO) \
1761 || (REGNO) == ARG_POINTER_REGNUM \
1762 || (REGNO) == FRAME_POINTER_REGNUM \
1763 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1764
1765/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1766 and check its validity for a certain class.
1767 We have two alternate definitions for each of them.
1768 The usual definition accepts all pseudo regs; the other rejects
1769 them unless they have been allocated suitable hard regs.
1770 The symbol REG_OK_STRICT causes the latter definition to be used.
1771
1772 Most source files want to accept pseudo regs in the hope that
1773 they will get allocated to the class that the insn wants them to be in.
1774 Source files for reload pass need to be strict.
1775 After reload, it makes no difference, since pseudo regs have
1776 been eliminated by then. */
1777
1778
1779/* Non strict versions, pseudos are ok. */
1780#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1781 (REGNO (X) < STACK_POINTER_REGNUM \
1782 || REX_INT_REGNO_P (REGNO (X)) \
1783 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1784
1785#define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1786 (GENERAL_REGNO_P (REGNO (X)) \
1787 || REGNO (X) == ARG_POINTER_REGNUM \
1788 || REGNO (X) == FRAME_POINTER_REGNUM \
1789 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1790
1791/* Strict versions, hard registers only */
1792#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1793#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1794
1795#ifndef REG_OK_STRICT
1796#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1797#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1798
1799#else
1800#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1801#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1802#endif
1803
1804/* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1805 that is a valid memory address for an instruction.
1806 The MODE argument is the machine mode for the MEM expression
1807 that wants to use this address.
1808
1809 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P,
1810 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1811
1812 See legitimize_pic_address in i386.c for details as to what
1813 constitutes a legitimate address when -fpic is used. */
1814
1815#define MAX_REGS_PER_ADDRESS 2
1816
1817#define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1818
1819/* If defined, a C expression to determine the base term of address X.
1820 This macro is used in only one place: `find_base_term' in alias.c.
1821
1822 It is always safe for this macro to not be defined. It exists so
1823 that alias analysis can understand machine-dependent addresses.
1824
1825 The typical use of this macro is to handle addresses containing
1826 a label_ref or symbol_ref within an UNSPEC. */
1827
1828#define FIND_BASE_TERM(X) ix86_find_base_term (X)
1829
1830/* Nonzero if the constant value X is a legitimate general operand
1831 when generating PIC code. It is given that flag_pic is on and
1832 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1833
1834#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1835
1836#define SYMBOLIC_CONST(X) \
1837 (GET_CODE (X) == SYMBOL_REF \
1838 || GET_CODE (X) == LABEL_REF \
1839 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1840
1841/* Max number of args passed in registers. If this is more than 3, we will
1842 have problems with ebx (register #4), since it is a caller save register and
1843 is also used as the pic register in ELF. So for now, don't allow more than
1844 3 registers to be passed in registers. */
1845
1846/* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */
1847#define X86_64_REGPARM_MAX 6
1848#define X86_64_MS_REGPARM_MAX 4
1849
1850#define X86_32_REGPARM_MAX 3
1851
1852#define REGPARM_MAX \
1853 (TARGET_64BIT \
1854 ? (TARGET_64BIT_MS_ABI \
1855 ? X86_64_MS_REGPARM_MAX \
1856 : X86_64_REGPARM_MAX) \
1857 : X86_32_REGPARM_MAX)
1858
1859#define X86_64_SSE_REGPARM_MAX 8
1860#define X86_64_MS_SSE_REGPARM_MAX 4
1861
1862#define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0)
1863
1864#define SSE_REGPARM_MAX \
1865 (TARGET_64BIT \
1866 ? (TARGET_64BIT_MS_ABI \
1867 ? X86_64_MS_SSE_REGPARM_MAX \
1868 : X86_64_SSE_REGPARM_MAX) \
1869 : X86_32_SSE_REGPARM_MAX)
1870
1871#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1872
1873/* Specify the machine mode that this machine uses
1874 for the index in the tablejump instruction. */
1875#define CASE_VECTOR_MODE \
1876 (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1877
1878/* Define this as 1 if `char' should by default be signed; else as 0. */
1879#define DEFAULT_SIGNED_CHAR 1
1880
1881/* Max number of bytes we can move from memory to memory
1882 in one reasonably fast instruction. */
1883#define MOVE_MAX 16
1884
1885/* MOVE_MAX_PIECES is the number of bytes at a time which we can
1886 move efficiently, as opposed to MOVE_MAX which is the maximum
1887 number of bytes we can move with a single instruction.
1888
1889 ??? We should use TImode in 32-bit mode and use OImode or XImode
1890 if they are available. But since by_pieces_ninsns determines the
1891 widest mode with MAX_FIXED_MODE_SIZE, we can only use TImode in
1892 64-bit mode. */
1893#define MOVE_MAX_PIECES \
1894 ((TARGET_64BIT \
1895 && TARGET_SSE2 \
1896 && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
1897 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \
1898 ? GET_MODE_SIZE (TImode) : UNITS_PER_WORD)
1899
1900/* If a memory-to-memory move would take MOVE_RATIO or more simple
1901 move-instruction pairs, we will do a movmem or libcall instead.
1902 Increasing the value will always make code faster, but eventually
1903 incurs high cost in increased code size.
1904
1905 If you don't define this, a reasonable default is used. */
1906
1907#define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3)
1908
1909/* If a clear memory operation would take CLEAR_RATIO or more simple
1910 move-instruction sequences, we will do a clrmem or libcall instead. */
1911
1912#define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2)
1913
1914/* Define if shifts truncate the shift count which implies one can
1915 omit a sign-extension or zero-extension of a shift count.
1916
1917 On i386, shifts do truncate the count. But bit test instructions
1918 take the modulo of the bit offset operand. */
1919
1920/* #define SHIFT_COUNT_TRUNCATED */
1921
1922/* A macro to update M and UNSIGNEDP when an object whose type is
1923 TYPE and which has the specified mode and signedness is to be
1924 stored in a register. This macro is only called when TYPE is a
1925 scalar type.
1926
1927 On i386 it is sometimes useful to promote HImode and QImode
1928 quantities to SImode. The choice depends on target type. */
1929
1930#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1931do { \
1932 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1933 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1934 (MODE) = SImode; \
1935} while (0)
1936
1937/* Specify the machine mode that pointers have.
1938 After generation of rtl, the compiler makes no further distinction
1939 between pointers and any other objects of this machine mode. */
1940#define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode)
1941
1942/* Specify the machine mode that bounds have. */
1943#define BNDmode (ix86_pmode == PMODE_DI ? BND64mode : BND32mode)
1944
1945/* A C expression whose value is zero if pointers that need to be extended
1946 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
1947 greater then zero if they are zero-extended and less then zero if the
1948 ptr_extend instruction should be used. */
1949
1950#define POINTERS_EXTEND_UNSIGNED 1
1951
1952/* A function address in a call instruction
1953 is a byte address (for indexing purposes)
1954 so give the MEM rtx a byte's mode. */
1955#define FUNCTION_MODE QImode
1956
1957
1958/* A C expression for the cost of a branch instruction. A value of 1
1959 is the default; other values are interpreted relative to that. */
1960
1961#define BRANCH_COST(speed_p, predictable_p) \
1962 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost)
1963
1964/* An integer expression for the size in bits of the largest integer machine
1965 mode that should actually be used. We allow pairs of registers. */
1966#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
1967
1968/* Define this macro as a C expression which is nonzero if accessing
1969 less than a word of memory (i.e. a `char' or a `short') is no
1970 faster than accessing a word of memory, i.e., if such access
1971 require more than one instruction or if there is no difference in
1972 cost between byte and (aligned) word loads.
1973
1974 When this macro is not defined, the compiler will access a field by
1975 finding the smallest containing object; when it is defined, a
1976 fullword load will be used if alignment permits. Unless bytes
1977 accesses are faster than word accesses, using word accesses is
1978 preferable since it may eliminate subsequent memory access if
1979 subsequent accesses occur to other fields in the same word of the
1980 structure, but to different bytes. */
1981
1982#define SLOW_BYTE_ACCESS 0
1983
1984/* Nonzero if access to memory by shorts is slow and undesirable. */
1985#define SLOW_SHORT_ACCESS 0
1986
1987/* Define this macro if it is as good or better to call a constant
1988 function address than to call an address kept in a register.
1989
1990 Desirable on the 386 because a CALL with a constant address is
1991 faster than one with a register address. */
1992
1993#define NO_FUNCTION_CSE 1
1994
1995/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1996 return the mode to be used for the comparison.
1997
1998 For floating-point equality comparisons, CCFPEQmode should be used.
1999 VOIDmode should be used in all other cases.
2000
2001 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2002 possible, to allow for more combinations. */
2003
2004#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2005
2006/* Return nonzero if MODE implies a floating point inequality can be
2007 reversed. */
2008
2009#define REVERSIBLE_CC_MODE(MODE) 1
2010
2011/* A C expression whose value is reversed condition code of the CODE for
2012 comparison done in CC_MODE mode. */
2013#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
2014
2015
2016/* Control the assembler format that we output, to the extent
2017 this does not vary between assemblers. */
2018
2019/* How to refer to registers in assembler output.
2020 This sequence is indexed by compiler's hard-register-number (see above). */
2021
2022/* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
2023 For non floating point regs, the following are the HImode names.
2024
2025 For float regs, the stack top is sometimes referred to as "%st(0)"
2026 instead of just "%st". TARGET_PRINT_OPERAND handles this with the
2027 "y" code. */
2028
2029#define HI_REGISTER_NAMES \
2030{"ax","dx","cx","bx","si","di","bp","sp", \
2031 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2032 "argp", "flags", "fpsr", "fpcr", "frame", \
2033 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2034 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
2035 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2036 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \
2037 "xmm16", "xmm17", "xmm18", "xmm19", \
2038 "xmm20", "xmm21", "xmm22", "xmm23", \
2039 "xmm24", "xmm25", "xmm26", "xmm27", \
2040 "xmm28", "xmm29", "xmm30", "xmm31", \
2041 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", \
2042 "bnd0", "bnd1", "bnd2", "bnd3" }
2043
2044#define REGISTER_NAMES HI_REGISTER_NAMES
2045
2046/* Table of additional register names to use in user input. */
2047
2048#define ADDITIONAL_REGISTER_NAMES \
2049{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2050 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2051 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2052 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2053 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2054 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2055 { "ymm0", 21}, { "ymm1", 22}, { "ymm2", 23}, { "ymm3", 24}, \
2056 { "ymm4", 25}, { "ymm5", 26}, { "ymm6", 27}, { "ymm7", 28}, \
2057 { "ymm8", 45}, { "ymm9", 46}, { "ymm10", 47}, { "ymm11", 48}, \
2058 { "ymm12", 49}, { "ymm13", 50}, { "ymm14", 51}, { "ymm15", 52}, \
2059 { "ymm16", 53}, { "ymm17", 54}, { "ymm18", 55}, { "ymm19", 56}, \
2060 { "ymm20", 57}, { "ymm21", 58}, { "ymm22", 59}, { "ymm23", 60}, \
2061 { "ymm24", 61}, { "ymm25", 62}, { "ymm26", 63}, { "ymm27", 64}, \
2062 { "ymm28", 65}, { "ymm29", 66}, { "ymm30", 67}, { "ymm31", 68}, \
2063 { "zmm0", 21}, { "zmm1", 22}, { "zmm2", 23}, { "zmm3", 24}, \
2064 { "zmm4", 25}, { "zmm5", 26}, { "zmm6", 27}, { "zmm7", 28}, \
2065 { "zmm8", 45}, { "zmm9", 46}, { "zmm10", 47}, { "zmm11", 48}, \
2066 { "zmm12", 49}, { "zmm13", 50}, { "zmm14", 51}, { "zmm15", 52}, \
2067 { "zmm16", 53}, { "zmm17", 54}, { "zmm18", 55}, { "zmm19", 56}, \
2068 { "zmm20", 57}, { "zmm21", 58}, { "zmm22", 59}, { "zmm23", 60}, \
2069 { "zmm24", 61}, { "zmm25", 62}, { "zmm26", 63}, { "zmm27", 64}, \
2070 { "zmm28", 65}, { "zmm29", 66}, { "zmm30", 67}, { "zmm31", 68} }
2071
2072/* Note we are omitting these since currently I don't know how
2073to get gcc to use these, since they want the same but different
2074number as al, and ax.
2075*/
2076
2077#define QI_REGISTER_NAMES \
2078{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2079
2080/* These parallel the array above, and can be used to access bits 8:15
2081 of regs 0 through 3. */
2082
2083#define QI_HIGH_REGISTER_NAMES \
2084{"ah", "dh", "ch", "bh", }
2085
2086/* How to renumber registers for dbx and gdb. */
2087
2088#define DBX_REGISTER_NUMBER(N) \
2089 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2090
2091extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2092extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2093extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2094
2095/* Before the prologue, RA is at 0(%esp). */
2096#define INCOMING_RETURN_ADDR_RTX \
2097 gen_rtx_MEM (Pmode, stack_pointer_rtx)
2098
2099/* After the prologue, RA is at -4(AP) in the current frame. */
2100#define RETURN_ADDR_RTX(COUNT, FRAME) \
2101 ((COUNT) == 0 \
2102 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \
2103 -UNITS_PER_WORD)) \
2104 : gen_rtx_MEM (Pmode, plus_constant (Pmode, (FRAME), UNITS_PER_WORD)))
2105
2106/* PC is dbx register 8; let's use that column for RA. */
2107#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2108
2109/* Before the prologue, there are return address and error code for
2110 exception handler on the top of the frame. */
2111#define INCOMING_FRAME_SP_OFFSET \
2112 (cfun->machine->func_type == TYPE_EXCEPTION \
2113 ? 2 * UNITS_PER_WORD : UNITS_PER_WORD)
2114
2115/* Describe how we implement __builtin_eh_return. */
2116#define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM)
2117#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG)
2118
2119
2120/* Select a format to encode pointers in exception handling data. CODE
2121 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2122 true if the symbol may be affected by dynamic relocations.
2123
2124 ??? All x86 object file formats are capable of representing this.
2125 After all, the relocation needed is the same as for the call insn.
2126 Whether or not a particular assembler allows us to enter such, I
2127 guess we'll have to see. */
2128#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2129 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2130
2131/* These are a couple of extensions to the formats accepted
2132 by asm_fprintf:
2133 %z prints out opcode suffix for word-mode instruction
2134 %r prints out word-mode name for reg_names[arg] */
2135#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
2136 case 'z': \
2137 fputc (TARGET_64BIT ? 'q' : 'l', (FILE)); \
2138 break; \
2139 \
2140 case 'r': \
2141 { \
2142 unsigned int regno = va_arg ((ARGS), int); \
2143 if (LEGACY_INT_REGNO_P (regno)) \
2144 fputc (TARGET_64BIT ? 'r' : 'e', (FILE)); \
2145 fputs (reg_names[regno], (FILE)); \
2146 break; \
2147 }
2148
2149/* This is how to output an insn to push a register on the stack. */
2150
2151#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2152 asm_fprintf ((FILE), "\tpush%z\t%%%r\n", (REGNO))
2153
2154/* This is how to output an insn to pop a register from the stack. */
2155
2156#define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2157 asm_fprintf ((FILE), "\tpop%z\t%%%r\n", (REGNO))
2158
2159/* This is how to output an element of a case-vector that is absolute. */
2160
2161#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2162 ix86_output_addr_vec_elt ((FILE), (VALUE))
2163
2164/* This is how to output an element of a case-vector that is relative. */
2165
2166#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2167 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2168
2169/* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */
2170
2171#define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \
2172{ \
2173 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \
2174 (PTR) += TARGET_AVX ? 1 : 2; \
2175}
2176
2177/* A C statement or statements which output an assembler instruction
2178 opcode to the stdio stream STREAM. The macro-operand PTR is a
2179 variable of type `char *' which points to the opcode name in
2180 its "internal" form--the form that is written in the machine
2181 description. */
2182
2183#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
2184 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR))
2185
2186/* A C statement to output to the stdio stream FILE an assembler
2187 command to pad the location counter to a multiple of 1<<LOG
2188 bytes if it is within MAX_SKIP bytes. */
2189
2190#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2191#undef ASM_OUTPUT_MAX_SKIP_PAD
2192#define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \
2193 if ((LOG) != 0) \
2194 { \
2195 if ((MAX_SKIP) == 0) \
2196 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2197 else \
2198 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
2199 }
2200#endif
2201
2202/* Write the extra assembler code needed to declare a function
2203 properly. */
2204
2205#undef ASM_OUTPUT_FUNCTION_LABEL
2206#define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \
2207 ix86_asm_output_function_label ((FILE), (NAME), (DECL))
2208
2209/* Under some conditions we need jump tables in the text section,
2210 because the assembler cannot handle label differences between
2211 sections. This is the case for x86_64 on Mach-O for example. */
2212
2213#define JUMP_TABLES_IN_TEXT_SECTION \
2214 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2215 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2216
2217/* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2218 and switch back. For x86 we do this only to save a few bytes that
2219 would otherwise be unused in the text section. */
2220#define CRT_MKSTR2(VAL) #VAL
2221#define CRT_MKSTR(x) CRT_MKSTR2(x)
2222
2223#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2224 asm (SECTION_OP "\n\t" \
2225 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \
2226 TEXT_SECTION_ASM_OP);
2227
2228/* Default threshold for putting data in large sections
2229 with x86-64 medium memory model */
2230#define DEFAULT_LARGE_SECTION_THRESHOLD 65536
2231
2232/* Adjust the length of the insn with the length of BND prefix. */
2233
2234#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2235do { \
2236 if (NONDEBUG_INSN_P (INSN) && INSN_CODE (INSN) >= 0 \
2237 && get_attr_maybe_prefix_bnd (INSN)) \
2238 LENGTH += ix86_bnd_prefixed_insn_p (INSN); \
2239} while (0)
2240
2241/* Which processor to tune code generation for. These must be in sync
2242 with processor_target_table in i386.c. */
2243
2244enum processor_type
2245{
2246 PROCESSOR_GENERIC = 0,
2247 PROCESSOR_I386, /* 80386 */
2248 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2249 PROCESSOR_PENTIUM,
2250 PROCESSOR_LAKEMONT,
2251 PROCESSOR_PENTIUMPRO,
2252 PROCESSOR_PENTIUM4,
2253 PROCESSOR_NOCONA,
2254 PROCESSOR_CORE2,
2255 PROCESSOR_NEHALEM,
2256 PROCESSOR_SANDYBRIDGE,
2257 PROCESSOR_HASWELL,
2258 PROCESSOR_BONNELL,
2259 PROCESSOR_SILVERMONT,
2260 PROCESSOR_KNL,
2261 PROCESSOR_KNM,
2262 PROCESSOR_SKYLAKE_AVX512,
2263 PROCESSOR_CANNONLAKE,
2264 PROCESSOR_INTEL,
2265 PROCESSOR_GEODE,
2266 PROCESSOR_K6,
2267 PROCESSOR_ATHLON,
2268 PROCESSOR_K8,
2269 PROCESSOR_AMDFAM10,
2270 PROCESSOR_BDVER1,
2271 PROCESSOR_BDVER2,
2272 PROCESSOR_BDVER3,
2273 PROCESSOR_BDVER4,
2274 PROCESSOR_BTVER1,
2275 PROCESSOR_BTVER2,
2276 PROCESSOR_ZNVER1,
2277 PROCESSOR_max
2278};
2279
2280extern enum processor_type ix86_tune;
2281extern enum processor_type ix86_arch;
2282
2283/* Size of the RED_ZONE area. */
2284#define RED_ZONE_SIZE 128
2285/* Reserved area of the red zone for temporaries. */
2286#define RED_ZONE_RESERVE 8
2287
2288extern unsigned int ix86_preferred_stack_boundary;
2289extern unsigned int ix86_incoming_stack_boundary;
2290
2291/* Smallest class containing REGNO. */
2292extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2293
2294enum ix86_fpcmp_strategy {
2295 IX86_FPCMP_SAHF,
2296 IX86_FPCMP_COMI,
2297 IX86_FPCMP_ARITH
2298};
2299
2300/* To properly truncate FP values into integers, we need to set i387 control
2301 word. We can't emit proper mode switching code before reload, as spills
2302 generated by reload may truncate values incorrectly, but we still can avoid
2303 redundant computation of new control word by the mode switching pass.
2304 The fldcw instructions are still emitted redundantly, but this is probably
2305 not going to be noticeable problem, as most CPUs do have fast path for
2306 the sequence.
2307
2308 The machinery is to emit simple truncation instructions and split them
2309 before reload to instructions having USEs of two memory locations that
2310 are filled by this code to old and new control word.
2311
2312 Post-reload pass may be later used to eliminate the redundant fildcw if
2313 needed. */
2314
2315enum ix86_stack_slot
2316{
2317 SLOT_TEMP = 0,
2318 SLOT_CW_STORED,
2319 SLOT_CW_TRUNC,
2320 SLOT_CW_FLOOR,
2321 SLOT_CW_CEIL,
2322 SLOT_CW_MASK_PM,
2323 SLOT_STV_TEMP,
2324 MAX_386_STACK_LOCALS
2325};
2326
2327enum ix86_entity
2328{
2329 X86_DIRFLAG = 0,
2330 AVX_U128,
2331 I387_TRUNC,
2332 I387_FLOOR,
2333 I387_CEIL,
2334 I387_MASK_PM,
2335 MAX_386_ENTITIES
2336};
2337
2338enum x86_dirflag_state
2339{
2340 X86_DIRFLAG_RESET,
2341 X86_DIRFLAG_ANY
2342};
2343
2344enum avx_u128_state
2345{
2346 AVX_U128_CLEAN,
2347 AVX_U128_DIRTY,
2348 AVX_U128_ANY
2349};
2350
2351/* Define this macro if the port needs extra instructions inserted
2352 for mode switching in an optimizing compilation. */
2353
2354#define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2355 ix86_optimize_mode_switching[(ENTITY)]
2356
2357/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2358 initializer for an array of integers. Each initializer element N
2359 refers to an entity that needs mode switching, and specifies the
2360 number of different modes that might need to be set for this
2361 entity. The position of the initializer in the initializer -
2362 starting counting at zero - determines the integer that is used to
2363 refer to the mode-switched entity in question. */
2364
2365#define NUM_MODES_FOR_MODE_SWITCHING \
2366 { X86_DIRFLAG_ANY, AVX_U128_ANY, \
2367 I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2368
2369
2370/* Avoid renaming of stack registers, as doing so in combination with
2371 scheduling just increases amount of live registers at time and in
2372 the turn amount of fxch instructions needed.
2373
2374 ??? Maybe Pentium chips benefits from renaming, someone can try....
2375
2376 Don't rename evex to non-evex sse registers. */
2377
2378#define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2379 (!STACK_REGNO_P (SRC) \
2380 && EXT_REX_SSE_REGNO_P (SRC) == EXT_REX_SSE_REGNO_P (TARGET))
2381
2382
2383#define FASTCALL_PREFIX '@'
2384
2385#ifndef USED_FOR_TARGET
2386/* Structure describing stack frame layout.
2387 Stack grows downward:
2388
2389 [arguments]
2390 <- ARG_POINTER
2391 saved pc
2392
2393 saved static chain if ix86_static_chain_on_stack
2394
2395 saved frame pointer if frame_pointer_needed
2396 <- HARD_FRAME_POINTER
2397 [saved regs]
2398 <- reg_save_offset
2399 [padding0]
2400 <- stack_realign_offset
2401 [saved SSE regs]
2402 OR
2403 [stub-saved registers for ms x64 --> sysv clobbers
2404 <- Start of out-of-line, stub-saved/restored regs
2405 (see libgcc/config/i386/(sav|res)ms64*.S)
2406 [XMM6-15]
2407 [RSI]
2408 [RDI]
2409 [?RBX] only if RBX is clobbered
2410 [?RBP] only if RBP and RBX are clobbered
2411 [?R12] only if R12 and all previous regs are clobbered
2412 [?R13] only if R13 and all previous regs are clobbered
2413 [?R14] only if R14 and all previous regs are clobbered
2414 [?R15] only if R15 and all previous regs are clobbered
2415 <- end of stub-saved/restored regs
2416 [padding1]
2417 ]
2418 <- sse_reg_save_offset
2419 [padding2]
2420 | <- FRAME_POINTER
2421 [va_arg registers] |
2422 |
2423 [frame] |
2424 |
2425 [padding2] | = to_allocate
2426 <- STACK_POINTER
2427 */
2428struct GTY(()) ix86_frame
2429{
2430 int nsseregs;
2431 int nregs;
2432 int va_arg_size;
2433 int red_zone_size;
2434 int outgoing_arguments_size;
2435
2436 /* The offsets relative to ARG_POINTER. */
2437 HOST_WIDE_INT frame_pointer_offset;
2438 HOST_WIDE_INT hard_frame_pointer_offset;
2439 HOST_WIDE_INT stack_pointer_offset;
2440 HOST_WIDE_INT hfp_save_offset;
2441 HOST_WIDE_INT reg_save_offset;
2442 HOST_WIDE_INT stack_realign_allocate;
2443 HOST_WIDE_INT stack_realign_offset;
2444 HOST_WIDE_INT sse_reg_save_offset;
2445
2446 /* When save_regs_using_mov is set, emit prologue using
2447 move instead of push instructions. */
2448 bool save_regs_using_mov;
2449};
2450
2451/* Machine specific frame tracking during prologue/epilogue generation. All
2452 values are positive, but since the x86 stack grows downward, are subtratced
2453 from the CFA to produce a valid address. */
2454
2455struct GTY(()) machine_frame_state
2456{
2457 /* This pair tracks the currently active CFA as reg+offset. When reg
2458 is drap_reg, we don't bother trying to record here the real CFA when
2459 it might really be a DW_CFA_def_cfa_expression. */
2460 rtx cfa_reg;
2461 HOST_WIDE_INT cfa_offset;
2462
2463 /* The current offset (canonically from the CFA) of ESP and EBP.
2464 When stack frame re-alignment is active, these may not be relative
2465 to the CFA. However, in all cases they are relative to the offsets
2466 of the saved registers stored in ix86_frame. */
2467 HOST_WIDE_INT sp_offset;
2468 HOST_WIDE_INT fp_offset;
2469
2470 /* The size of the red-zone that may be assumed for the purposes of
2471 eliding register restore notes in the epilogue. This may be zero
2472 if no red-zone is in effect, or may be reduced from the real
2473 red-zone value by a maximum runtime stack re-alignment value. */
2474 int red_zone_offset;
2475
2476 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid
2477 value within the frame. If false then the offset above should be
2478 ignored. Note that DRAP, if valid, *always* points to the CFA and
2479 thus has an offset of zero. */
2480 BOOL_BITFIELD sp_valid : 1;
2481 BOOL_BITFIELD fp_valid : 1;
2482 BOOL_BITFIELD drap_valid : 1;
2483
2484 /* Indicate whether the local stack frame has been re-aligned. When
2485 set, the SP/FP offsets above are relative to the aligned frame
2486 and not the CFA. */
2487 BOOL_BITFIELD realigned : 1;
2488
2489 /* Indicates whether the stack pointer has been re-aligned. When set,
2490 SP/FP continue to be relative to the CFA, but the stack pointer
2491 should only be used for offsets > sp_realigned_offset, while
2492 the frame pointer should be used for offsets <= sp_realigned_fp_last.
2493 The flags realigned and sp_realigned are mutually exclusive. */
2494 BOOL_BITFIELD sp_realigned : 1;
2495
2496 /* If sp_realigned is set, this is the last valid offset from the CFA
2497 that can be used for access with the frame pointer. */
2498 HOST_WIDE_INT sp_realigned_fp_last;
2499
2500 /* If sp_realigned is set, this is the offset from the CFA that the stack
2501 pointer was realigned, and may or may not be equal to sp_realigned_fp_last.
2502 Access via the stack pointer is only valid for offsets that are greater than
2503 this value. */
2504 HOST_WIDE_INT sp_realigned_offset;
2505};
2506
2507/* Private to winnt.c. */
2508struct seh_frame_state;
2509
2510enum function_type
2511{
2512 TYPE_UNKNOWN = 0,
2513 TYPE_NORMAL,
2514 /* The current function is an interrupt service routine with a
2515 pointer argument as specified by the "interrupt" attribute. */
2516 TYPE_INTERRUPT,
2517 /* The current function is an interrupt service routine with a
2518 pointer argument and an integer argument as specified by the
2519 "interrupt" attribute. */
2520 TYPE_EXCEPTION
2521};
2522
2523struct GTY(()) machine_function {
2524 struct stack_local_entry *stack_locals;
2525 int varargs_gpr_size;
2526 int varargs_fpr_size;
2527 int optimize_mode_switching[MAX_386_ENTITIES];
2528
2529 /* Cached initial frame layout for the current function. */
2530 struct ix86_frame frame;
2531
2532 /* For -fsplit-stack support: A stack local which holds a pointer to
2533 the stack arguments for a function with a variable number of
2534 arguments. This is set at the start of the function and is used
2535 to initialize the overflow_arg_area field of the va_list
2536 structure. */
2537 rtx split_stack_varargs_pointer;
2538
2539 /* This value is used for amd64 targets and specifies the current abi
2540 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */
2541 ENUM_BITFIELD(calling_abi) call_abi : 8;
2542
2543 /* Nonzero if the function accesses a previous frame. */
2544 BOOL_BITFIELD accesses_prev_frame : 1;
2545
2546 /* Set by ix86_compute_frame_layout and used by prologue/epilogue
2547 expander to determine the style used. */
2548 BOOL_BITFIELD use_fast_prologue_epilogue : 1;
2549
2550 /* Nonzero if the current function calls pc thunk and
2551 must not use the red zone. */
2552 BOOL_BITFIELD pc_thunk_call_expanded : 1;
2553
2554 /* If true, the current function needs the default PIC register, not
2555 an alternate register (on x86) and must not use the red zone (on
2556 x86_64), even if it's a leaf function. We don't want the
2557 function to be regarded as non-leaf because TLS calls need not
2558 affect register allocation. This flag is set when a TLS call
2559 instruction is expanded within a function, and never reset, even
2560 if all such instructions are optimized away. Use the
2561 ix86_current_function_calls_tls_descriptor macro for a better
2562 approximation. */
2563 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1;
2564
2565 /* If true, the current function has a STATIC_CHAIN is placed on the
2566 stack below the return address. */
2567 BOOL_BITFIELD static_chain_on_stack : 1;
2568
2569 /* If true, it is safe to not save/restore DRAP register. */
2570 BOOL_BITFIELD no_drap_save_restore : 1;
2571
2572 /* Function type. */
2573 ENUM_BITFIELD(function_type) func_type : 2;
2574
2575 /* If true, the current function is a function specified with
2576 the "interrupt" or "no_caller_saved_registers" attribute. */
2577 BOOL_BITFIELD no_caller_saved_registers : 1;
2578
2579 /* If true, there is register available for argument passing. This
2580 is used only in ix86_function_ok_for_sibcall by 32-bit to determine
2581 if there is scratch register available for indirect sibcall. In
2582 64-bit, rax, r10 and r11 are scratch registers which aren't used to
2583 pass arguments and can be used for indirect sibcall. */
2584 BOOL_BITFIELD arg_reg_available : 1;
2585
2586 /* If true, we're out-of-lining reg save/restore for regs clobbered
2587 by 64-bit ms_abi functions calling a sysv_abi function. */
2588 BOOL_BITFIELD call_ms2sysv : 1;
2589
2590 /* If true, the incoming 16-byte aligned stack has an offset (of 8) and
2591 needs padding prior to out-of-line stub save/restore area. */
2592 BOOL_BITFIELD call_ms2sysv_pad_in : 1;
2593
2594 /* This is the number of extra registers saved by stub (valid range is
2595 0-6). Each additional register is only saved/restored by the stubs
2596 if all successive ones are. (Will always be zero when using a hard
2597 frame pointer.) */
2598 unsigned int call_ms2sysv_extra_regs:3;
2599
2600 /* Nonzero if the function places outgoing arguments on stack. */
2601 BOOL_BITFIELD outgoing_args_on_stack : 1;
2602
2603 /* During prologue/epilogue generation, the current frame state.
2604 Otherwise, the frame state at the end of the prologue. */
2605 struct machine_frame_state fs;
2606
2607 /* During SEH output, this is non-null. */
2608 struct seh_frame_state * GTY((skip(""))) seh;
2609};
2610#endif
2611
2612#define ix86_stack_locals (cfun->machine->stack_locals)
2613#define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size)
2614#define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size)
2615#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2616#define ix86_pc_thunk_call_expanded (cfun->machine->pc_thunk_call_expanded)
2617#define ix86_tls_descriptor_calls_expanded_in_cfun \
2618 (cfun->machine->tls_descriptor_call_expanded_p)
2619/* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2620 calls are optimized away, we try to detect cases in which it was
2621 optimized away. Since such instructions (use (reg REG_SP)), we can
2622 verify whether there's any such instruction live by testing that
2623 REG_SP is live. */
2624#define ix86_current_function_calls_tls_descriptor \
2625 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2626#define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack)
2627#define ix86_red_zone_size (cfun->machine->frame.red_zone_size)
2628
2629/* Control behavior of x86_file_start. */
2630#define X86_FILE_START_VERSION_DIRECTIVE false
2631#define X86_FILE_START_FLTUSED false
2632
2633/* Flag to mark data that is in the large address area. */
2634#define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2635#define SYMBOL_REF_FAR_ADDR_P(X) \
2636 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2637
2638/* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2639 have defined always, to avoid ifdefing. */
2640#define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2641#define SYMBOL_REF_DLLIMPORT_P(X) \
2642 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2643
2644#define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2645#define SYMBOL_REF_DLLEXPORT_P(X) \
2646 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
2647
2648#define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4)
2649#define SYMBOL_REF_STUBVAR_P(X) \
2650 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0)
2651
2652extern void debug_ready_dispatch (void);
2653extern void debug_dispatch_window (int);
2654
2655/* The value at zero is only defined for the BMI instructions
2656 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */
2657#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2658 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 1 : 0)
2659#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2660 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 1 : 0)
2661
2662
2663/* Flags returned by ix86_get_callcvt (). */
2664#define IX86_CALLCVT_CDECL 0x1
2665#define IX86_CALLCVT_STDCALL 0x2
2666#define IX86_CALLCVT_FASTCALL 0x4
2667#define IX86_CALLCVT_THISCALL 0x8
2668#define IX86_CALLCVT_REGPARM 0x10
2669#define IX86_CALLCVT_SSEREGPARM 0x20
2670
2671#define IX86_BASE_CALLCVT(FLAGS) \
2672 ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \
2673 | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL))
2674
2675#define RECIP_MASK_NONE 0x00
2676#define RECIP_MASK_DIV 0x01
2677#define RECIP_MASK_SQRT 0x02
2678#define RECIP_MASK_VEC_DIV 0x04
2679#define RECIP_MASK_VEC_SQRT 0x08
2680#define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \
2681 | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
2682#define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
2683
2684#define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0)
2685#define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0)
2686#define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0)
2687#define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0)
2688
2689/* Use 128-bit AVX instructions in the auto-vectorizer. */
2690#define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128)
2691/* Use 256-bit AVX instructions in the auto-vectorizer. */
2692#define TARGET_PREFER_AVX256 (TARGET_PREFER_AVX128 \
2693 || prefer_vector_width_type == PVW_AVX256)
2694
2695#define IX86_HLE_ACQUIRE (1 << 16)
2696#define IX86_HLE_RELEASE (1 << 17)
2697
2698/* For switching between functions with different target attributes. */
2699#define SWITCHABLE_TARGET 1
2700
2701#define TARGET_SUPPORTS_WIDE_INT 1
2702
2703/*
2704Local variables:
2705version-control: t
2706End:
2707*/
2708