1 | // SPDX-License-Identifier: GPL-2.0 |
2 | #include <linux/kernel.h> |
3 | #include <linux/init.h> |
4 | #include <linux/clocksource.h> |
5 | #include <linux/clockchips.h> |
6 | #include <linux/sched_clock.h> |
7 | #include <linux/interrupt.h> |
8 | #include <linux/irq.h> |
9 | #include <linux/io.h> |
10 | #include <asm/mach/time.h> |
11 | #include "soc.h" |
12 | #include "platform.h" |
13 | |
14 | /************************************************************************* |
15 | * Timer handling for EP93xx |
16 | ************************************************************************* |
17 | * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and |
18 | * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate |
19 | * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz, |
20 | * is free-running, and can't generate interrupts. |
21 | * |
22 | * The 508 kHz timers are ideal for use for the timer interrupt, as the |
23 | * most common values of HZ divide 508 kHz nicely. We pick the 32 bit |
24 | * timer (timer 3) to get as long sleep intervals as possible when using |
25 | * CONFIG_NO_HZ. |
26 | * |
27 | * The higher clock rate of timer 4 makes it a better choice than the |
28 | * other timers for use as clock source and for sched_clock(), providing |
29 | * a stable 40 bit time base. |
30 | ************************************************************************* |
31 | */ |
32 | #define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) |
33 | #define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) |
34 | #define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) |
35 | #define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08) |
36 | #define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7) |
37 | #define EP93XX_TIMER123_CONTROL_MODE (1 << 6) |
38 | #define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3) |
39 | #define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c) |
40 | #define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20) |
41 | #define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24) |
42 | #define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28) |
43 | #define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c) |
44 | #define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60) |
45 | #define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64) |
46 | #define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8) |
47 | #define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80) |
48 | #define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84) |
49 | #define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) |
50 | #define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) |
51 | |
52 | #define EP93XX_TIMER123_RATE 508469 |
53 | #define EP93XX_TIMER4_RATE 983040 |
54 | |
55 | static u64 notrace ep93xx_read_sched_clock(void) |
56 | { |
57 | u64 ret; |
58 | |
59 | ret = readl(EP93XX_TIMER4_VALUE_LOW); |
60 | ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); |
61 | return ret; |
62 | } |
63 | |
64 | static u64 ep93xx_clocksource_read(struct clocksource *c) |
65 | { |
66 | u64 ret; |
67 | |
68 | ret = readl(EP93XX_TIMER4_VALUE_LOW); |
69 | ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); |
70 | return (u64) ret; |
71 | } |
72 | |
73 | static int ep93xx_clkevt_set_next_event(unsigned long next, |
74 | struct clock_event_device *evt) |
75 | { |
76 | /* Default mode: periodic, off, 508 kHz */ |
77 | u32 tmode = EP93XX_TIMER123_CONTROL_MODE | |
78 | EP93XX_TIMER123_CONTROL_CLKSEL; |
79 | |
80 | /* Clear timer */ |
81 | writel(val: tmode, EP93XX_TIMER3_CONTROL); |
82 | |
83 | /* Set next event */ |
84 | writel(val: next, EP93XX_TIMER3_LOAD); |
85 | writel(val: tmode | EP93XX_TIMER123_CONTROL_ENABLE, |
86 | EP93XX_TIMER3_CONTROL); |
87 | return 0; |
88 | } |
89 | |
90 | |
91 | static int ep93xx_clkevt_shutdown(struct clock_event_device *evt) |
92 | { |
93 | /* Disable timer */ |
94 | writel(val: 0, EP93XX_TIMER3_CONTROL); |
95 | |
96 | return 0; |
97 | } |
98 | |
99 | static struct clock_event_device ep93xx_clockevent = { |
100 | .name = "timer1" , |
101 | .features = CLOCK_EVT_FEAT_ONESHOT, |
102 | .set_state_shutdown = ep93xx_clkevt_shutdown, |
103 | .set_state_oneshot = ep93xx_clkevt_shutdown, |
104 | .tick_resume = ep93xx_clkevt_shutdown, |
105 | .set_next_event = ep93xx_clkevt_set_next_event, |
106 | .rating = 300, |
107 | }; |
108 | |
109 | static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) |
110 | { |
111 | struct clock_event_device *evt = dev_id; |
112 | |
113 | /* Writing any value clears the timer interrupt */ |
114 | writel(val: 1, EP93XX_TIMER3_CLEAR); |
115 | |
116 | evt->event_handler(evt); |
117 | |
118 | return IRQ_HANDLED; |
119 | } |
120 | |
121 | void __init ep93xx_timer_init(void) |
122 | { |
123 | int irq = IRQ_EP93XX_TIMER3; |
124 | unsigned long flags = IRQF_TIMER | IRQF_IRQPOLL; |
125 | |
126 | /* Enable and register clocksource and sched_clock on timer 4 */ |
127 | writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, |
128 | EP93XX_TIMER4_VALUE_HIGH); |
129 | clocksource_mmio_init(NULL, "timer4" , |
130 | EP93XX_TIMER4_RATE, 200, 40, |
131 | ep93xx_clocksource_read); |
132 | sched_clock_register(read: ep93xx_read_sched_clock, bits: 40, |
133 | EP93XX_TIMER4_RATE); |
134 | |
135 | /* Set up clockevent on timer 3 */ |
136 | if (request_irq(irq, handler: ep93xx_timer_interrupt, flags, name: "ep93xx timer" , |
137 | dev: &ep93xx_clockevent)) |
138 | pr_err("Failed to request irq %d (ep93xx timer)\n" , irq); |
139 | clockevents_config_and_register(dev: &ep93xx_clockevent, |
140 | EP93XX_TIMER123_RATE, |
141 | min_delta: 1, |
142 | max_delta: 0xffffffffU); |
143 | } |
144 | |