| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
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| 4 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__ |
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| 8 | #define __ARCH_ARM_MACH_MX3_CRM_REGS_H__ |
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| 9 | |
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| 10 | #define CKIH_CLK_FREQ 26000000 |
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| 11 | #define CKIH_CLK_FREQ_27MHZ 27000000 |
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| 12 | #define CKIL_CLK_FREQ 32768 |
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| 13 | |
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| 14 | extern void __iomem *mx3_ccm_base; |
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| 15 | |
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| 16 | /* Register addresses */ |
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| 17 | #define MXC_CCM_CCMR 0x00 |
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| 18 | #define MXC_CCM_PDR0 0x04 |
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| 19 | #define MXC_CCM_PDR1 0x08 |
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| 20 | #define MX35_CCM_PDR2 0x0C |
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| 21 | #define MXC_CCM_RCSR 0x0C |
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| 22 | #define MX35_CCM_PDR3 0x10 |
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| 23 | #define MXC_CCM_MPCTL 0x10 |
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| 24 | #define MX35_CCM_PDR4 0x14 |
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| 25 | #define MXC_CCM_UPCTL 0x14 |
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| 26 | #define MX35_CCM_RCSR 0x18 |
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| 27 | #define MXC_CCM_SRPCTL 0x18 |
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| 28 | #define MX35_CCM_MPCTL 0x1C |
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| 29 | #define MXC_CCM_COSR 0x1C |
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| 30 | #define MX35_CCM_PPCTL 0x20 |
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| 31 | #define MXC_CCM_CGR0 0x20 |
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| 32 | #define MX35_CCM_ACMR 0x24 |
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| 33 | #define MXC_CCM_CGR1 0x24 |
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| 34 | #define MX35_CCM_COSR 0x28 |
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| 35 | #define MXC_CCM_CGR2 0x28 |
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| 36 | #define MX35_CCM_CGR0 0x2C |
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| 37 | #define MXC_CCM_WIMR 0x2C |
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| 38 | #define MX35_CCM_CGR1 0x30 |
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| 39 | #define MXC_CCM_LDC 0x30 |
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| 40 | #define MX35_CCM_CGR2 0x34 |
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| 41 | #define MXC_CCM_DCVR0 0x34 |
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| 42 | #define MX35_CCM_CGR3 0x38 |
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| 43 | #define MXC_CCM_DCVR1 0x38 |
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| 44 | #define MXC_CCM_DCVR2 0x3C |
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| 45 | #define MXC_CCM_DCVR3 0x40 |
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| 46 | #define MXC_CCM_LTR0 0x44 |
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| 47 | #define MXC_CCM_LTR1 0x48 |
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| 48 | #define MXC_CCM_LTR2 0x4C |
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| 49 | #define MXC_CCM_LTR3 0x50 |
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| 50 | #define MXC_CCM_LTBR0 0x54 |
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| 51 | #define MXC_CCM_LTBR1 0x58 |
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| 52 | #define MXC_CCM_PMCR0 0x5C |
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| 53 | #define MXC_CCM_PMCR1 0x60 |
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| 54 | #define MXC_CCM_PDR2 0x64 |
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| 55 | |
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| 56 | /* Register bit definitions */ |
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| 57 | #define MXC_CCM_CCMR_WBEN (1 << 27) |
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| 58 | #define MXC_CCM_CCMR_CSCS (1 << 25) |
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| 59 | #define MXC_CCM_CCMR_PERCS (1 << 24) |
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| 60 | #define MXC_CCM_CCMR_SSI1S_OFFSET 18 |
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| 61 | #define MXC_CCM_CCMR_SSI1S_MASK (0x3 << 18) |
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| 62 | #define MXC_CCM_CCMR_SSI2S_OFFSET 21 |
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| 63 | #define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21) |
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| 64 | #define MXC_CCM_CCMR_LPM_OFFSET 14 |
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| 65 | #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) |
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| 66 | #define MXC_CCM_CCMR_LPM_WAIT_MX35 (0x1 << 14) |
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| 67 | #define MXC_CCM_CCMR_FIRS_OFFSET 11 |
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| 68 | #define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11) |
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| 69 | #define MXC_CCM_CCMR_UPE (1 << 9) |
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| 70 | #define MXC_CCM_CCMR_SPE (1 << 8) |
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| 71 | #define MXC_CCM_CCMR_MDS (1 << 7) |
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| 72 | #define MXC_CCM_CCMR_SBYCS (1 << 4) |
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| 73 | #define MXC_CCM_CCMR_MPE (1 << 3) |
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| 74 | #define MXC_CCM_CCMR_PRCS_OFFSET 1 |
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| 75 | #define MXC_CCM_CCMR_PRCS_MASK (0x3 << 1) |
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| 76 | |
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| 77 | #define MXC_CCM_PDR0_CSI_PODF_OFFSET 26 |
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| 78 | #define MXC_CCM_PDR0_CSI_PODF_MASK (0x3F << 26) |
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| 79 | #define MXC_CCM_PDR0_CSI_PRDF_OFFSET 23 |
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| 80 | #define MXC_CCM_PDR0_CSI_PRDF_MASK (0x7 << 23) |
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| 81 | #define MXC_CCM_PDR0_PER_PODF_OFFSET 16 |
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| 82 | #define MXC_CCM_PDR0_PER_PODF_MASK (0x1F << 16) |
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| 83 | #define MXC_CCM_PDR0_HSP_PODF_OFFSET 11 |
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| 84 | #define MXC_CCM_PDR0_HSP_PODF_MASK (0x7 << 11) |
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| 85 | #define MXC_CCM_PDR0_NFC_PODF_OFFSET 8 |
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| 86 | #define MXC_CCM_PDR0_NFC_PODF_MASK (0x7 << 8) |
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| 87 | #define MXC_CCM_PDR0_IPG_PODF_OFFSET 6 |
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| 88 | #define MXC_CCM_PDR0_IPG_PODF_MASK (0x3 << 6) |
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| 89 | #define MXC_CCM_PDR0_MAX_PODF_OFFSET 3 |
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| 90 | #define MXC_CCM_PDR0_MAX_PODF_MASK (0x7 << 3) |
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| 91 | #define MXC_CCM_PDR0_MCU_PODF_OFFSET 0 |
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| 92 | #define MXC_CCM_PDR0_MCU_PODF_MASK 0x7 |
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| 93 | |
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| 94 | #define MXC_CCM_PDR1_USB_PRDF_OFFSET 30 |
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| 95 | #define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) |
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| 96 | #define MXC_CCM_PDR1_USB_PODF_OFFSET 27 |
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| 97 | #define MXC_CCM_PDR1_USB_PODF_MASK (0x7 << 27) |
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| 98 | #define MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET 24 |
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| 99 | #define MXC_CCM_PDR1_FIRI_PRE_PODF_MASK (0x7 << 24) |
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| 100 | #define MXC_CCM_PDR1_FIRI_PODF_OFFSET 18 |
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| 101 | #define MXC_CCM_PDR1_FIRI_PODF_MASK (0x3F << 18) |
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| 102 | #define MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET 15 |
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| 103 | #define MXC_CCM_PDR1_SSI2_PRE_PODF_MASK (0x7 << 15) |
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| 104 | #define MXC_CCM_PDR1_SSI2_PODF_OFFSET 9 |
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| 105 | #define MXC_CCM_PDR1_SSI2_PODF_MASK (0x3F << 9) |
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| 106 | #define MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET 6 |
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| 107 | #define MXC_CCM_PDR1_SSI1_PRE_PODF_MASK (0x7 << 6) |
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| 108 | #define MXC_CCM_PDR1_SSI1_PODF_OFFSET 0 |
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| 109 | #define MXC_CCM_PDR1_SSI1_PODF_MASK 0x3F |
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| 110 | |
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| 111 | /* Bit definitions for RCSR */ |
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| 112 | #define MXC_CCM_RCSR_NF16B 0x80000000 |
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| 113 | |
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| 114 | /* |
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| 115 | * LTR0 register offsets |
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| 116 | */ |
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| 117 | #define MXC_CCM_LTR0_DIV3CK_OFFSET 1 |
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| 118 | #define MXC_CCM_LTR0_DIV3CK_MASK (0x3 << 1) |
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| 119 | #define MXC_CCM_LTR0_DNTHR_OFFSET 16 |
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| 120 | #define MXC_CCM_LTR0_DNTHR_MASK (0x3F << 16) |
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| 121 | #define MXC_CCM_LTR0_UPTHR_OFFSET 22 |
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| 122 | #define MXC_CCM_LTR0_UPTHR_MASK (0x3F << 22) |
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| 123 | |
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| 124 | /* |
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| 125 | * LTR1 register offsets |
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| 126 | */ |
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| 127 | #define MXC_CCM_LTR1_PNCTHR_OFFSET 0 |
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| 128 | #define MXC_CCM_LTR1_PNCTHR_MASK 0x3F |
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| 129 | #define MXC_CCM_LTR1_UPCNT_OFFSET 6 |
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| 130 | #define MXC_CCM_LTR1_UPCNT_MASK (0xFF << 6) |
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| 131 | #define MXC_CCM_LTR1_DNCNT_OFFSET 14 |
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| 132 | #define MXC_CCM_LTR1_DNCNT_MASK (0xFF << 14) |
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| 133 | #define MXC_CCM_LTR1_LTBRSR_MASK 0x400000 |
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| 134 | #define MXC_CCM_LTR1_LTBRSR_OFFSET 22 |
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| 135 | #define MXC_CCM_LTR1_LTBRSR 0x400000 |
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| 136 | #define MXC_CCM_LTR1_LTBRSH 0x800000 |
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| 137 | |
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| 138 | /* |
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| 139 | * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15 |
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| 140 | */ |
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| 141 | #define MXC_CCM_LTR2_WSW_OFFSET(x) (11 + (x) * 3) |
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| 142 | #define MXC_CCM_LTR2_WSW_MASK(x) (0x7 << \ |
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| 143 | MXC_CCM_LTR2_WSW_OFFSET((x))) |
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| 144 | #define MXC_CCM_LTR2_EMAC_OFFSET 0 |
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| 145 | #define MXC_CCM_LTR2_EMAC_MASK 0x1FF |
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| 146 | |
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| 147 | /* |
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| 148 | * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8 |
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| 149 | */ |
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| 150 | #define MXC_CCM_LTR3_WSW_OFFSET(x) (5 + (x) * 3) |
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| 151 | #define MXC_CCM_LTR3_WSW_MASK(x) (0x7 << \ |
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| 152 | MXC_CCM_LTR3_WSW_OFFSET((x))) |
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| 153 | |
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| 154 | #define MXC_CCM_PMCR0_DFSUP1 0x80000000 |
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| 155 | #define MXC_CCM_PMCR0_DFSUP1_SPLL (0 << 31) |
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| 156 | #define MXC_CCM_PMCR0_DFSUP1_MPLL (1 << 31) |
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| 157 | #define MXC_CCM_PMCR0_DFSUP0 0x40000000 |
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| 158 | #define MXC_CCM_PMCR0_DFSUP0_PLL (0 << 30) |
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| 159 | #define MXC_CCM_PMCR0_DFSUP0_PDR (1 << 30) |
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| 160 | #define MXC_CCM_PMCR0_DFSUP_MASK (0x3 << 30) |
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| 161 | |
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| 162 | #define DVSUP_TURBO 0 |
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| 163 | #define DVSUP_HIGH 1 |
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| 164 | #define DVSUP_MEDIUM 2 |
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| 165 | #define DVSUP_LOW 3 |
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| 166 | #define MXC_CCM_PMCR0_DVSUP_TURBO (DVSUP_TURBO << 28) |
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| 167 | #define MXC_CCM_PMCR0_DVSUP_HIGH (DVSUP_HIGH << 28) |
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| 168 | #define MXC_CCM_PMCR0_DVSUP_MEDIUM (DVSUP_MEDIUM << 28) |
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| 169 | #define MXC_CCM_PMCR0_DVSUP_LOW (DVSUP_LOW << 28) |
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| 170 | #define MXC_CCM_PMCR0_DVSUP_OFFSET 28 |
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| 171 | #define MXC_CCM_PMCR0_DVSUP_MASK (0x3 << 28) |
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| 172 | #define MXC_CCM_PMCR0_UDSC 0x08000000 |
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| 173 | #define MXC_CCM_PMCR0_UDSC_MASK (1 << 27) |
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| 174 | #define MXC_CCM_PMCR0_UDSC_UP (1 << 27) |
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| 175 | #define MXC_CCM_PMCR0_UDSC_DOWN (0 << 27) |
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| 176 | |
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| 177 | #define MXC_CCM_PMCR0_VSCNT_1 (0x0 << 24) |
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| 178 | #define MXC_CCM_PMCR0_VSCNT_2 (0x1 << 24) |
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| 179 | #define MXC_CCM_PMCR0_VSCNT_3 (0x2 << 24) |
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| 180 | #define MXC_CCM_PMCR0_VSCNT_4 (0x3 << 24) |
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| 181 | #define MXC_CCM_PMCR0_VSCNT_5 (0x4 << 24) |
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| 182 | #define MXC_CCM_PMCR0_VSCNT_6 (0x5 << 24) |
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| 183 | #define MXC_CCM_PMCR0_VSCNT_7 (0x6 << 24) |
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| 184 | #define MXC_CCM_PMCR0_VSCNT_8 (0x7 << 24) |
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| 185 | #define MXC_CCM_PMCR0_VSCNT_OFFSET 24 |
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| 186 | #define MXC_CCM_PMCR0_VSCNT_MASK (0x7 << 24) |
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| 187 | #define MXC_CCM_PMCR0_DVFEV 0x00800000 |
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| 188 | #define MXC_CCM_PMCR0_DVFIS 0x00400000 |
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| 189 | #define MXC_CCM_PMCR0_LBMI 0x00200000 |
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| 190 | #define MXC_CCM_PMCR0_LBFL 0x00100000 |
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| 191 | #define MXC_CCM_PMCR0_LBCF_4 (0x0 << 18) |
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| 192 | #define MXC_CCM_PMCR0_LBCF_8 (0x1 << 18) |
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| 193 | #define MXC_CCM_PMCR0_LBCF_12 (0x2 << 18) |
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| 194 | #define MXC_CCM_PMCR0_LBCF_16 (0x3 << 18) |
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| 195 | #define MXC_CCM_PMCR0_LBCF_OFFSET 18 |
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| 196 | #define MXC_CCM_PMCR0_LBCF_MASK (0x3 << 18) |
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| 197 | #define MXC_CCM_PMCR0_PTVIS 0x00020000 |
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| 198 | #define MXC_CCM_PMCR0_UPDTEN 0x00010000 |
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| 199 | #define MXC_CCM_PMCR0_UPDTEN_MASK (0x1 << 16) |
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| 200 | #define MXC_CCM_PMCR0_FSVAIM 0x00008000 |
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| 201 | #define MXC_CCM_PMCR0_FSVAI_OFFSET 13 |
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| 202 | #define MXC_CCM_PMCR0_FSVAI_MASK (0x3 << 13) |
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| 203 | #define MXC_CCM_PMCR0_DPVCR 0x00001000 |
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| 204 | #define MXC_CCM_PMCR0_DPVV 0x00000800 |
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| 205 | #define MXC_CCM_PMCR0_WFIM 0x00000400 |
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| 206 | #define MXC_CCM_PMCR0_DRCE3 0x00000200 |
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| 207 | #define MXC_CCM_PMCR0_DRCE2 0x00000100 |
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| 208 | #define MXC_CCM_PMCR0_DRCE1 0x00000080 |
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| 209 | #define MXC_CCM_PMCR0_DRCE0 0x00000040 |
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| 210 | #define MXC_CCM_PMCR0_DCR 0x00000020 |
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| 211 | #define MXC_CCM_PMCR0_DVFEN 0x00000010 |
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| 212 | #define MXC_CCM_PMCR0_PTVAIM 0x00000008 |
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| 213 | #define MXC_CCM_PMCR0_PTVAI_OFFSET 1 |
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| 214 | #define MXC_CCM_PMCR0_PTVAI_MASK (0x3 << 1) |
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| 215 | #define MXC_CCM_PMCR0_DPTEN 0x00000001 |
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| 216 | |
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| 217 | #define MXC_CCM_PMCR1_DVGP_OFFSET 0 |
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| 218 | #define MXC_CCM_PMCR1_DVGP_MASK (0xF) |
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| 219 | |
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| 220 | #define MXC_CCM_PMCR1_PLLRDIS (0x1 << 7) |
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| 221 | #define MXC_CCM_PMCR1_EMIRQ_EN (0x1 << 8) |
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| 222 | |
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| 223 | #define MXC_CCM_DCVR_ULV_MASK (0x3FF << 22) |
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| 224 | #define MXC_CCM_DCVR_ULV_OFFSET 22 |
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| 225 | #define MXC_CCM_DCVR_LLV_MASK (0x3FF << 12) |
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| 226 | #define MXC_CCM_DCVR_LLV_OFFSET 12 |
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| 227 | #define MXC_CCM_DCVR_ELV_MASK (0x3FF << 2) |
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| 228 | #define MXC_CCM_DCVR_ELV_OFFSET 2 |
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| 229 | |
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| 230 | #define MXC_CCM_PDR2_MST2_PDF_MASK (0x3F << 7) |
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| 231 | #define MXC_CCM_PDR2_MST2_PDF_OFFSET 7 |
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| 232 | #define MXC_CCM_PDR2_MST1_PDF_MASK 0x3F |
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| 233 | #define MXC_CCM_PDR2_MST1_PDF_OFFSET 0 |
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| 234 | |
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| 235 | #define MXC_CCM_COSR_CLKOSEL_MASK 0x0F |
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| 236 | #define MXC_CCM_COSR_CLKOSEL_OFFSET 0 |
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| 237 | #define MXC_CCM_COSR_CLKOUTDIV_MASK (0x07 << 6) |
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| 238 | #define MXC_CCM_COSR_CLKOUTDIV_OFFSET 6 |
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| 239 | #define MXC_CCM_COSR_CLKOEN (1 << 9) |
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| 240 | |
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| 241 | /* |
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| 242 | * PMCR0 register offsets |
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| 243 | */ |
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| 244 | #define MXC_CCM_PMCR0_LBFL_OFFSET 20 |
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| 245 | #define MXC_CCM_PMCR0_DFSUP0_OFFSET 30 |
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| 246 | #define MXC_CCM_PMCR0_DFSUP1_OFFSET 31 |
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| 247 | |
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| 248 | #endif /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */ |
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| 249 | |
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