| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Common address map definitions |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __ASM_MACH_ADDR_MAP_H |
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| 7 | #define __ASM_MACH_ADDR_MAP_H |
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| 8 | |
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| 9 | /* APB - Application Subsystem Peripheral Bus |
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| 10 | * |
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| 11 | * NOTE: the DMA controller registers are actually on the AXI fabric #1 |
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| 12 | * slave port to AHB/APB bridge, due to its close relationship to those |
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| 13 | * peripherals on APB, let's count it into the ABP mapping area. |
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| 14 | */ |
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| 15 | #define APB_PHYS_BASE 0xd4000000 |
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| 16 | #define APB_VIRT_BASE IOMEM(0xfe000000) |
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| 17 | #define APB_PHYS_SIZE 0x00200000 |
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| 18 | |
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| 19 | #define AXI_PHYS_BASE 0xd4200000 |
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| 20 | #define AXI_VIRT_BASE IOMEM(0xfe200000) |
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| 21 | #define AXI_PHYS_SIZE 0x00200000 |
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| 22 | |
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| 23 | #define PGU_PHYS_BASE 0xe0000000 |
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| 24 | #define PGU_VIRT_BASE IOMEM(0xfe400000) |
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| 25 | #define PGU_PHYS_SIZE 0x00100000 |
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| 26 | |
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| 27 | /* Static Memory Controller - Chip Select 0 and 1 */ |
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| 28 | #define SMC_CS0_PHYS_BASE 0x80000000 |
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| 29 | #define SMC_CS0_PHYS_SIZE 0x10000000 |
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| 30 | #define SMC_CS1_PHYS_BASE 0x90000000 |
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| 31 | #define SMC_CS1_PHYS_SIZE 0x10000000 |
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| 32 | |
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| 33 | #define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800) |
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| 34 | #define APMU_REG(x) (APMU_VIRT_BASE + (x)) |
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| 35 | |
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| 36 | #define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000) |
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| 37 | #define APBC_REG(x) (APBC_VIRT_BASE + (x)) |
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| 38 | |
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| 39 | #define MPMU_VIRT_BASE (APB_VIRT_BASE + 0x50000) |
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| 40 | #define MPMU_REG(x) (MPMU_VIRT_BASE + (x)) |
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| 41 | |
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| 42 | #define CIU_VIRT_BASE (AXI_VIRT_BASE + 0x82c00) |
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| 43 | #define CIU_REG(x) (CIU_VIRT_BASE + (x)) |
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| 44 | |
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| 45 | #define SCU_VIRT_BASE (PGU_VIRT_BASE) |
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| 46 | #define SCU_REG(x) (SCU_VIRT_BASE + (x)) |
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| 47 | |
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| 48 | #endif /* __ASM_MACH_ADDR_MAP_H */ |
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| 49 | |
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