| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Generic definitions for Marvell MV78xx0 SoC flavors: |
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| 4 | * MV781x0 and MV782x0. |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef __ASM_ARCH_MV78XX0_H |
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| 8 | #define __ASM_ARCH_MV78XX0_H |
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| 9 | |
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| 10 | #include "irqs.h" |
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| 11 | |
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| 12 | /* |
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| 13 | * Marvell MV78xx0 address maps. |
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| 14 | * |
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| 15 | * phys |
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| 16 | * c0000000 PCIe Memory space |
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| 17 | * f0800000 PCIe #0 I/O space |
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| 18 | * f0900000 PCIe #1 I/O space |
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| 19 | * f0a00000 PCIe #2 I/O space |
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| 20 | * f0b00000 PCIe #3 I/O space |
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| 21 | * f0c00000 PCIe #4 I/O space |
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| 22 | * f0d00000 PCIe #5 I/O space |
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| 23 | * f0e00000 PCIe #6 I/O space |
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| 24 | * f0f00000 PCIe #7 I/O space |
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| 25 | * f1000000 on-chip peripheral registers |
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| 26 | * |
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| 27 | * virt phys size |
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| 28 | * fe400000 f102x000 16K core-specific peripheral registers |
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| 29 | * fee00000 f0800000 64K PCIe #0 I/O space |
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| 30 | * fee10000 f0900000 64K PCIe #1 I/O space |
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| 31 | * fee20000 f0a00000 64K PCIe #2 I/O space |
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| 32 | * fee30000 f0b00000 64K PCIe #3 I/O space |
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| 33 | * fee40000 f0c00000 64K PCIe #4 I/O space |
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| 34 | * fee50000 f0d00000 64K PCIe #5 I/O space |
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| 35 | * fee60000 f0e00000 64K PCIe #6 I/O space |
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| 36 | * fee70000 f0f00000 64K PCIe #7 I/O space |
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| 37 | * fec00000 f1000000 1M on-chip peripheral registers |
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| 38 | */ |
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| 39 | #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 |
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| 40 | #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 |
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| 41 | #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000) |
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| 42 | #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 |
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| 43 | #define MV78XX0_CORE_REGS_SIZE SZ_16K |
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| 44 | |
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| 45 | #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) |
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| 46 | #define MV78XX0_PCIE_IO_SIZE SZ_1M |
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| 47 | |
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| 48 | #define MV78XX0_REGS_PHYS_BASE 0xf1000000 |
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| 49 | #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000) |
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| 50 | #define MV78XX0_REGS_SIZE SZ_1M |
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| 51 | |
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| 52 | #define MV78XX0_SRAM_PHYS_BASE (0xf2200000) |
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| 53 | #define MV78XX0_SRAM_SIZE SZ_8K |
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| 54 | |
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| 55 | #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 |
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| 56 | #define MV78XX0_PCIE_MEM_SIZE 0x30000000 |
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| 57 | |
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| 58 | #define MV78XX0_MBUS_SRAM_TARGET 0x09 |
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| 59 | #define MV78XX0_MBUS_SRAM_ATTR 0x00 |
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| 60 | |
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| 61 | /* |
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| 62 | * Core-specific peripheral registers. |
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| 63 | */ |
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| 64 | #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) |
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| 65 | #define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE) |
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| 66 | #define BRIDGE_WINS_CPU0_BASE (MV78XX0_CORE0_REGS_PHYS_BASE) |
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| 67 | #define BRIDGE_WINS_CPU1_BASE (MV78XX0_CORE1_REGS_PHYS_BASE) |
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| 68 | #define BRIDGE_WINS_SZ (0xA000) |
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| 69 | |
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| 70 | /* |
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| 71 | * Register Map |
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| 72 | */ |
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| 73 | #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000) |
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| 74 | #define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000) |
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| 75 | #define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500) |
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| 76 | #define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570) |
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| 77 | #define DDR_WINDOW_CPU_SZ (0x20) |
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| 78 | |
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| 79 | #define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000) |
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| 80 | #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000) |
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| 81 | #define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030) |
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| 82 | #define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034) |
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| 83 | #define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) |
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| 84 | #define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) |
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| 85 | #define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100) |
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| 86 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) |
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| 87 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) |
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| 88 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) |
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| 89 | #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) |
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| 90 | #define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200) |
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| 91 | #define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200) |
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| 92 | #define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300) |
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| 93 | #define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300) |
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| 94 | |
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| 95 | #define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000) |
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| 96 | #define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000) |
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| 97 | |
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| 98 | #define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000) |
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| 99 | #define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000) |
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| 100 | #define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000) |
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| 101 | #define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000) |
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| 102 | |
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| 103 | #define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000) |
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| 104 | #define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000) |
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| 105 | #define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000) |
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| 106 | |
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| 107 | #define XOR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x60900) |
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| 108 | |
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| 109 | #define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000) |
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| 110 | #define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000) |
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| 111 | |
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| 112 | #define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000) |
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| 113 | #define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000) |
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| 114 | #define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000) |
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| 115 | #define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000) |
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| 116 | |
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| 117 | #define CRYPTO_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x90000) |
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| 118 | |
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| 119 | #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000) |
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| 120 | |
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| 121 | /* |
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| 122 | * Supported devices and revisions. |
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| 123 | */ |
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| 124 | #define MV78X00_Z0_DEV_ID 0x6381 |
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| 125 | #define MV78X00_REV_Z0 1 |
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| 126 | |
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| 127 | #define MV78100_DEV_ID 0x7810 |
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| 128 | #define MV78100_REV_A0 1 |
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| 129 | #define MV78100_REV_A1 2 |
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| 130 | |
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| 131 | #define MV78200_DEV_ID 0x7820 |
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| 132 | #define MV78200_REV_A0 1 |
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| 133 | |
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| 134 | #endif |
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| 135 | |
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