| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2014 Marvell |
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| 4 | * |
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| 5 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
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| 6 | * Gregory Clement <gregory.clement@free-electrons.com> |
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| 7 | */ |
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| 8 | |
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| 9 | #include <linux/linkage.h> |
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| 10 | #include <asm/assembler.h> |
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| 11 | |
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| 12 | |
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| 13 | ENTRY(armada_38x_scu_power_up) |
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| 14 | mrc p15, 4, r1, c15, c0 @ get SCU base address |
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| 15 | orr r1, r1, #0x8 @ SCU CPU Power Status Register |
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| 16 | mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID |
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| 17 | and r0, r0, #15 |
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| 18 | add r1, r1, r0 |
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| 19 | mov r0, #0x0 |
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| 20 | strb r0, [r1] @ switch SCU power state to Normal mode |
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| 21 | ret lr |
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| 22 | ENDPROC(armada_38x_scu_power_up) |
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| 23 | |
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| 24 | /* |
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| 25 | * This is the entry point through which CPUs exiting cpuidle deep |
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| 26 | * idle state are going. |
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| 27 | */ |
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| 28 | ENTRY(armada_370_xp_cpu_resume) |
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| 29 | ARM_BE8(setend be ) @ go BE8 if entered LE |
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| 30 | /* |
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| 31 | * Disable the MMU that might have been enabled in BootROM if |
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| 32 | * this code is used in the resume path of a suspend/resume |
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| 33 | * cycle. |
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| 34 | */ |
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| 35 | mrc p15, 0, r1, c1, c0, 0 |
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| 36 | bic r1, #1 |
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| 37 | mcr p15, 0, r1, c1, c0, 0 |
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| 38 | bl ll_add_cpu_to_smp_group |
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| 39 | bl ll_enable_coherency |
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| 40 | b cpu_resume |
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| 41 | ENDPROC(armada_370_xp_cpu_resume) |
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| 42 | |
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| 43 | ENTRY(armada_38x_cpu_resume) |
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| 44 | /* do we need it for Armada 38x*/ |
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| 45 | ARM_BE8(setend be ) @ go BE8 if entered LE |
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| 46 | bl v7_invalidate_l1 |
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| 47 | bl armada_38x_scu_power_up |
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| 48 | b cpu_resume |
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| 49 | ENDPROC(armada_38x_cpu_resume) |
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| 50 | |
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| 51 | .global mvebu_boot_wa_start |
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| 52 | .global mvebu_boot_wa_end |
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| 53 | |
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| 54 | /* The following code will be executed from SRAM */ |
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| 55 | ENTRY(mvebu_boot_wa_start) |
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| 56 | ARM_BE8(setend be) |
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| 57 | adr r0, 1f |
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| 58 | ldr r0, [r0] @ load the address of the |
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| 59 | @ resume register |
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| 60 | ldr r0, [r0] @ load the value in the |
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| 61 | @ resume register |
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| 62 | ARM_BE8(rev r0, r0) @ the value is stored LE |
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| 63 | mov pc, r0 @ jump to this value |
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| 64 | /* |
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| 65 | * the last word of this piece of code will be filled by the physical |
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| 66 | * address of the boot address register just after being copied in SRAM |
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| 67 | */ |
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| 68 | 1: |
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| 69 | .long . |
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| 70 | mvebu_boot_wa_end: |
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| 71 | ENDPROC(mvebu_boot_wa_end) |
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| 72 | |
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