| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Copyright (C) Greg Lonnon 2001 |
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| 4 | * Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com> |
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| 5 | * |
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| 6 | * Copyright (C) 2009 Texas Instruments |
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| 7 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
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| 8 | * |
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| 9 | * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610 |
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| 10 | * are different. |
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| 11 | */ |
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| 12 | |
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| 13 | #ifndef __ASM_ARCH_OMAP15XX_IRQS_H |
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| 14 | #define __ASM_ARCH_OMAP15XX_IRQS_H |
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| 15 | |
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| 16 | /* |
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| 17 | * IRQ numbers for interrupt handler 1 |
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| 18 | * |
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| 19 | * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below |
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| 20 | * |
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| 21 | */ |
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| 22 | #define INT_CAMERA (NR_IRQS_LEGACY + 1) |
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| 23 | #define INT_FIQ (NR_IRQS_LEGACY + 3) |
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| 24 | #define INT_RTDX (NR_IRQS_LEGACY + 6) |
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| 25 | #define INT_DSP_MMU_ABORT (NR_IRQS_LEGACY + 7) |
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| 26 | #define INT_HOST (NR_IRQS_LEGACY + 8) |
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| 27 | #define INT_ABORT (NR_IRQS_LEGACY + 9) |
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| 28 | #define INT_BRIDGE_PRIV (NR_IRQS_LEGACY + 13) |
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| 29 | #define INT_GPIO_BANK1 (NR_IRQS_LEGACY + 14) |
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| 30 | #define INT_UART3 (NR_IRQS_LEGACY + 15) |
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| 31 | #define INT_TIMER3 (NR_IRQS_LEGACY + 16) |
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| 32 | #define INT_DMA_CH0_6 (NR_IRQS_LEGACY + 19) |
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| 33 | #define INT_DMA_CH1_7 (NR_IRQS_LEGACY + 20) |
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| 34 | #define INT_DMA_CH2_8 (NR_IRQS_LEGACY + 21) |
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| 35 | #define INT_DMA_CH3 (NR_IRQS_LEGACY + 22) |
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| 36 | #define INT_DMA_CH4 (NR_IRQS_LEGACY + 23) |
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| 37 | #define INT_DMA_CH5 (NR_IRQS_LEGACY + 24) |
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| 38 | #define INT_TIMER1 (NR_IRQS_LEGACY + 26) |
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| 39 | #define INT_WD_TIMER (NR_IRQS_LEGACY + 27) |
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| 40 | #define INT_BRIDGE_PUB (NR_IRQS_LEGACY + 28) |
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| 41 | #define INT_TIMER2 (NR_IRQS_LEGACY + 30) |
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| 42 | #define INT_LCD_CTRL (NR_IRQS_LEGACY + 31) |
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| 43 | |
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| 44 | /* |
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| 45 | * OMAP-1510 specific IRQ numbers for interrupt handler 1 |
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| 46 | */ |
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| 47 | #define INT_1510_IH2_IRQ (NR_IRQS_LEGACY + 0) |
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| 48 | #define INT_1510_RES2 (NR_IRQS_LEGACY + 2) |
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| 49 | #define INT_1510_SPI_TX (NR_IRQS_LEGACY + 4) |
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| 50 | #define INT_1510_SPI_RX (NR_IRQS_LEGACY + 5) |
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| 51 | #define INT_1510_DSP_MAILBOX1 (NR_IRQS_LEGACY + 10) |
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| 52 | #define INT_1510_DSP_MAILBOX2 (NR_IRQS_LEGACY + 11) |
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| 53 | #define INT_1510_RES12 (NR_IRQS_LEGACY + 12) |
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| 54 | #define INT_1510_LB_MMU (NR_IRQS_LEGACY + 17) |
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| 55 | #define INT_1510_RES18 (NR_IRQS_LEGACY + 18) |
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| 56 | #define INT_1510_LOCAL_BUS (NR_IRQS_LEGACY + 29) |
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| 57 | |
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| 58 | /* |
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| 59 | * OMAP-1610 specific IRQ numbers for interrupt handler 1 |
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| 60 | */ |
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| 61 | #define INT_1610_IH2_IRQ INT_1510_IH2_IRQ |
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| 62 | #define INT_1610_IH2_FIQ (NR_IRQS_LEGACY + 2) |
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| 63 | #define INT_1610_McBSP2_TX (NR_IRQS_LEGACY + 4) |
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| 64 | #define INT_1610_McBSP2_RX (NR_IRQS_LEGACY + 5) |
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| 65 | #define INT_1610_DSP_MAILBOX1 (NR_IRQS_LEGACY + 10) |
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| 66 | #define INT_1610_DSP_MAILBOX2 (NR_IRQS_LEGACY + 11) |
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| 67 | #define INT_1610_LCD_LINE (NR_IRQS_LEGACY + 12) |
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| 68 | #define INT_1610_GPTIMER1 (NR_IRQS_LEGACY + 17) |
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| 69 | #define INT_1610_GPTIMER2 (NR_IRQS_LEGACY + 18) |
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| 70 | #define INT_1610_SSR_FIFO_0 (NR_IRQS_LEGACY + 29) |
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| 71 | |
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| 72 | /* |
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| 73 | * OMAP-7xx specific IRQ numbers for interrupt handler 1 |
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| 74 | */ |
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| 75 | #define INT_7XX_IH2_FIQ (NR_IRQS_LEGACY + 0) |
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| 76 | #define INT_7XX_IH2_IRQ (NR_IRQS_LEGACY + 1) |
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| 77 | #define INT_7XX_USB_NON_ISO (NR_IRQS_LEGACY + 2) |
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| 78 | #define INT_7XX_USB_ISO (NR_IRQS_LEGACY + 3) |
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| 79 | #define INT_7XX_ICR (NR_IRQS_LEGACY + 4) |
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| 80 | #define INT_7XX_EAC (NR_IRQS_LEGACY + 5) |
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| 81 | #define INT_7XX_GPIO_BANK1 (NR_IRQS_LEGACY + 6) |
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| 82 | #define INT_7XX_GPIO_BANK2 (NR_IRQS_LEGACY + 7) |
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| 83 | #define INT_7XX_GPIO_BANK3 (NR_IRQS_LEGACY + 8) |
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| 84 | #define INT_7XX_McBSP2TX (NR_IRQS_LEGACY + 10) |
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| 85 | #define INT_7XX_McBSP2RX (NR_IRQS_LEGACY + 11) |
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| 86 | #define INT_7XX_McBSP2RX_OVF (NR_IRQS_LEGACY + 12) |
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| 87 | #define INT_7XX_LCD_LINE (NR_IRQS_LEGACY + 14) |
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| 88 | #define INT_7XX_GSM_PROTECT (NR_IRQS_LEGACY + 15) |
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| 89 | #define INT_7XX_TIMER3 (NR_IRQS_LEGACY + 16) |
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| 90 | #define INT_7XX_GPIO_BANK5 (NR_IRQS_LEGACY + 17) |
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| 91 | #define INT_7XX_GPIO_BANK6 (NR_IRQS_LEGACY + 18) |
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| 92 | #define INT_7XX_SPGIO_WR (NR_IRQS_LEGACY + 29) |
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| 93 | |
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| 94 | /* |
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| 95 | * IRQ numbers for interrupt handler 2 |
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| 96 | * |
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| 97 | * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below |
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| 98 | */ |
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| 99 | #define IH2_BASE (NR_IRQS_LEGACY + 32) |
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| 100 | |
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| 101 | #define INT_KEYBOARD (1 + IH2_BASE) |
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| 102 | #define INT_uWireTX (2 + IH2_BASE) |
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| 103 | #define INT_uWireRX (3 + IH2_BASE) |
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| 104 | #define INT_I2C (4 + IH2_BASE) |
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| 105 | #define INT_MPUIO (5 + IH2_BASE) |
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| 106 | #define INT_USB_HHC_1 (6 + IH2_BASE) |
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| 107 | #define INT_McBSP3TX (10 + IH2_BASE) |
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| 108 | #define INT_McBSP3RX (11 + IH2_BASE) |
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| 109 | #define INT_McBSP1TX (12 + IH2_BASE) |
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| 110 | #define INT_McBSP1RX (13 + IH2_BASE) |
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| 111 | #define INT_UART1 (14 + IH2_BASE) |
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| 112 | #define INT_UART2 (15 + IH2_BASE) |
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| 113 | #define INT_BT_MCSI1TX (16 + IH2_BASE) |
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| 114 | #define INT_BT_MCSI1RX (17 + IH2_BASE) |
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| 115 | #define INT_SOSSI_MATCH (19 + IH2_BASE) |
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| 116 | #define INT_USB_W2FC (20 + IH2_BASE) |
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| 117 | #define INT_1WIRE (21 + IH2_BASE) |
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| 118 | #define INT_OS_TIMER (22 + IH2_BASE) |
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| 119 | #define INT_MMC (23 + IH2_BASE) |
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| 120 | #define INT_GAUGE_32K (24 + IH2_BASE) |
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| 121 | #define INT_RTC_TIMER (25 + IH2_BASE) |
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| 122 | #define INT_RTC_ALARM (26 + IH2_BASE) |
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| 123 | #define INT_MEM_STICK (27 + IH2_BASE) |
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| 124 | |
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| 125 | /* |
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| 126 | * OMAP-1510 specific IRQ numbers for interrupt handler 2 |
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| 127 | */ |
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| 128 | #define INT_1510_DSP_MMU (28 + IH2_BASE) |
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| 129 | #define INT_1510_COM_SPI_RO (31 + IH2_BASE) |
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| 130 | |
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| 131 | /* |
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| 132 | * OMAP-1610 specific IRQ numbers for interrupt handler 2 |
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| 133 | */ |
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| 134 | #define INT_1610_FAC (0 + IH2_BASE) |
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| 135 | #define INT_1610_USB_HHC_2 (7 + IH2_BASE) |
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| 136 | #define INT_1610_USB_OTG (8 + IH2_BASE) |
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| 137 | #define INT_1610_SoSSI (9 + IH2_BASE) |
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| 138 | #define INT_1610_SoSSI_MATCH (19 + IH2_BASE) |
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| 139 | #define INT_1610_DSP_MMU (28 + IH2_BASE) |
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| 140 | #define INT_1610_McBSP2RX_OF (31 + IH2_BASE) |
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| 141 | #define INT_1610_STI (32 + IH2_BASE) |
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| 142 | #define INT_1610_STI_WAKEUP (33 + IH2_BASE) |
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| 143 | #define INT_1610_GPTIMER3 (34 + IH2_BASE) |
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| 144 | #define INT_1610_GPTIMER4 (35 + IH2_BASE) |
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| 145 | #define INT_1610_GPTIMER5 (36 + IH2_BASE) |
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| 146 | #define INT_1610_GPTIMER6 (37 + IH2_BASE) |
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| 147 | #define INT_1610_GPTIMER7 (38 + IH2_BASE) |
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| 148 | #define INT_1610_GPTIMER8 (39 + IH2_BASE) |
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| 149 | #define INT_1610_GPIO_BANK2 (40 + IH2_BASE) |
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| 150 | #define INT_1610_GPIO_BANK3 (41 + IH2_BASE) |
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| 151 | #define INT_1610_MMC2 (42 + IH2_BASE) |
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| 152 | #define INT_1610_CF (43 + IH2_BASE) |
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| 153 | #define INT_1610_WAKE_UP_REQ (46 + IH2_BASE) |
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| 154 | #define INT_1610_GPIO_BANK4 (48 + IH2_BASE) |
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| 155 | #define INT_1610_SPI (49 + IH2_BASE) |
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| 156 | #define INT_1610_DMA_CH6 (53 + IH2_BASE) |
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| 157 | #define INT_1610_DMA_CH7 (54 + IH2_BASE) |
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| 158 | #define INT_1610_DMA_CH8 (55 + IH2_BASE) |
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| 159 | #define INT_1610_DMA_CH9 (56 + IH2_BASE) |
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| 160 | #define INT_1610_DMA_CH10 (57 + IH2_BASE) |
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| 161 | #define INT_1610_DMA_CH11 (58 + IH2_BASE) |
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| 162 | #define INT_1610_DMA_CH12 (59 + IH2_BASE) |
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| 163 | #define INT_1610_DMA_CH13 (60 + IH2_BASE) |
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| 164 | #define INT_1610_DMA_CH14 (61 + IH2_BASE) |
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| 165 | #define INT_1610_DMA_CH15 (62 + IH2_BASE) |
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| 166 | #define INT_1610_NAND (63 + IH2_BASE) |
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| 167 | #define INT_1610_SHA1MD5 (91 + IH2_BASE) |
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| 168 | |
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| 169 | /* |
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| 170 | * OMAP-7xx specific IRQ numbers for interrupt handler 2 |
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| 171 | */ |
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| 172 | #define INT_7XX_HW_ERRORS (0 + IH2_BASE) |
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| 173 | #define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE) |
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| 174 | #define INT_7XX_CFCD (2 + IH2_BASE) |
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| 175 | #define INT_7XX_CFIREQ (3 + IH2_BASE) |
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| 176 | #define INT_7XX_I2C (4 + IH2_BASE) |
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| 177 | #define INT_7XX_PCC (5 + IH2_BASE) |
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| 178 | #define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE) |
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| 179 | #define INT_7XX_SPI_100K_1 (7 + IH2_BASE) |
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| 180 | #define INT_7XX_SYREN_SPI (8 + IH2_BASE) |
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| 181 | #define INT_7XX_VLYNQ (9 + IH2_BASE) |
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| 182 | #define INT_7XX_GPIO_BANK4 (10 + IH2_BASE) |
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| 183 | #define INT_7XX_McBSP1TX (11 + IH2_BASE) |
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| 184 | #define INT_7XX_McBSP1RX (12 + IH2_BASE) |
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| 185 | #define INT_7XX_McBSP1RX_OF (13 + IH2_BASE) |
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| 186 | #define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE) |
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| 187 | #define INT_7XX_UART_MODEM_1 (15 + IH2_BASE) |
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| 188 | #define INT_7XX_MCSI (16 + IH2_BASE) |
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| 189 | #define INT_7XX_uWireTX (17 + IH2_BASE) |
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| 190 | #define INT_7XX_uWireRX (18 + IH2_BASE) |
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| 191 | #define INT_7XX_SMC_CD (19 + IH2_BASE) |
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| 192 | #define INT_7XX_SMC_IREQ (20 + IH2_BASE) |
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| 193 | #define INT_7XX_HDQ_1WIRE (21 + IH2_BASE) |
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| 194 | #define INT_7XX_TIMER32K (22 + IH2_BASE) |
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| 195 | #define INT_7XX_MMC_SDIO (23 + IH2_BASE) |
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| 196 | #define INT_7XX_UPLD (24 + IH2_BASE) |
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| 197 | #define INT_7XX_USB_HHC_1 (27 + IH2_BASE) |
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| 198 | #define INT_7XX_USB_HHC_2 (28 + IH2_BASE) |
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| 199 | #define INT_7XX_USB_GENI (29 + IH2_BASE) |
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| 200 | #define INT_7XX_USB_OTG (30 + IH2_BASE) |
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| 201 | #define INT_7XX_CAMERA_IF (31 + IH2_BASE) |
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| 202 | #define INT_7XX_RNG (32 + IH2_BASE) |
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| 203 | #define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE) |
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| 204 | #define INT_7XX_DBB_RF_EN (34 + IH2_BASE) |
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| 205 | #define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE) |
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| 206 | #define INT_7XX_SHA1_MD5 (36 + IH2_BASE) |
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| 207 | #define INT_7XX_SPI_100K_2 (37 + IH2_BASE) |
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| 208 | #define INT_7XX_RNG_IDLE (38 + IH2_BASE) |
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| 209 | #define INT_7XX_MPUIO (39 + IH2_BASE) |
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| 210 | #define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) |
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| 211 | #define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE) |
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| 212 | #define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE) |
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| 213 | #define INT_7XX_LLPC_VSYNC (43 + IH2_BASE) |
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| 214 | #define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE) |
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| 215 | #define INT_7XX_DMA_CH6 (53 + IH2_BASE) |
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| 216 | #define INT_7XX_DMA_CH7 (54 + IH2_BASE) |
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| 217 | #define INT_7XX_DMA_CH8 (55 + IH2_BASE) |
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| 218 | #define INT_7XX_DMA_CH9 (56 + IH2_BASE) |
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| 219 | #define INT_7XX_DMA_CH10 (57 + IH2_BASE) |
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| 220 | #define INT_7XX_DMA_CH11 (58 + IH2_BASE) |
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| 221 | #define INT_7XX_DMA_CH12 (59 + IH2_BASE) |
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| 222 | #define INT_7XX_DMA_CH13 (60 + IH2_BASE) |
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| 223 | #define INT_7XX_DMA_CH14 (61 + IH2_BASE) |
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| 224 | #define INT_7XX_DMA_CH15 (62 + IH2_BASE) |
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| 225 | #define INT_7XX_NAND (63 + IH2_BASE) |
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| 226 | |
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| 227 | /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and |
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| 228 | * 16 MPUIO lines */ |
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| 229 | #define OMAP_MAX_GPIO_LINES 192 |
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| 230 | #define IH_GPIO_BASE (128 + IH2_BASE) |
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| 231 | #define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) |
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| 232 | #define OMAP_IRQ_END (IH_MPUIO_BASE + 16) |
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| 233 | |
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| 234 | #define OMAP_IRQ_BIT(irq) (1 << ((irq - NR_IRQS_LEGACY) % 32)) |
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| 235 | |
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| 236 | #ifdef CONFIG_FIQ |
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| 237 | #define FIQ_START 1024 |
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| 238 | #endif |
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| 239 | |
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| 240 | #endif |
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| 241 | |
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