| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * OMAP Traffic Controller |
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| 4 | * |
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| 5 | * Copyright (C) 2004 Nokia Corporation |
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| 6 | * Author: Imre Deak <imre.deak@nokia.com> |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __ASM_ARCH_TC_H |
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| 10 | #define __ASM_ARCH_TC_H |
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| 11 | |
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| 12 | #define TCMIF_BASE 0xfffecc00 |
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| 13 | #define OMAP_TC_OCPT1_PRIOR (TCMIF_BASE + 0x00) |
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| 14 | #define OMAP_TC_EMIFS_PRIOR (TCMIF_BASE + 0x04) |
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| 15 | #define OMAP_TC_EMIFF_PRIOR (TCMIF_BASE + 0x08) |
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| 16 | #define EMIFS_CONFIG (TCMIF_BASE + 0x0c) |
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| 17 | #define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10) |
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| 18 | #define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14) |
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| 19 | #define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18) |
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| 20 | #define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c) |
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| 21 | #define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20) |
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| 22 | #define EMIFF_MRS (TCMIF_BASE + 0x24) |
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| 23 | #define TC_TIMEOUT1 (TCMIF_BASE + 0x28) |
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| 24 | #define TC_TIMEOUT2 (TCMIF_BASE + 0x2c) |
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| 25 | #define TC_TIMEOUT3 (TCMIF_BASE + 0x30) |
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| 26 | #define TC_ENDIANISM (TCMIF_BASE + 0x34) |
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| 27 | #define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c) |
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| 28 | #define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40) |
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| 29 | #define EMIFS_ACS0 (TCMIF_BASE + 0x50) |
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| 30 | #define EMIFS_ACS1 (TCMIF_BASE + 0x54) |
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| 31 | #define EMIFS_ACS2 (TCMIF_BASE + 0x58) |
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| 32 | #define EMIFS_ACS3 (TCMIF_BASE + 0x5c) |
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| 33 | #define OMAP_TC_OCPT2_PRIOR (TCMIF_BASE + 0xd0) |
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| 34 | |
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| 35 | /* external EMIFS chipselect regions */ |
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| 36 | #define OMAP_CS0_PHYS 0x00000000 |
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| 37 | #define OMAP_CS0_SIZE SZ_64M |
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| 38 | |
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| 39 | #define OMAP_CS1_PHYS 0x04000000 |
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| 40 | #define OMAP_CS1_SIZE SZ_64M |
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| 41 | |
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| 42 | #define OMAP_CS1A_PHYS OMAP_CS1_PHYS |
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| 43 | #define OMAP_CS1A_SIZE SZ_32M |
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| 44 | |
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| 45 | #define OMAP_CS1B_PHYS (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE) |
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| 46 | #define OMAP_CS1B_SIZE SZ_32M |
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| 47 | |
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| 48 | #define OMAP_CS2_PHYS 0x08000000 |
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| 49 | #define OMAP_CS2_SIZE SZ_64M |
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| 50 | |
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| 51 | #define OMAP_CS2A_PHYS OMAP_CS2_PHYS |
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| 52 | #define OMAP_CS2A_SIZE SZ_32M |
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| 53 | |
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| 54 | #define OMAP_CS2B_PHYS (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE) |
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| 55 | #define OMAP_CS2B_SIZE SZ_32M |
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| 56 | |
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| 57 | #define OMAP_CS3_PHYS 0x0c000000 |
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| 58 | #define OMAP_CS3_SIZE SZ_64M |
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| 59 | |
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| 60 | #ifndef __ASSEMBLER__ |
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| 61 | |
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| 62 | /* EMIF Slow Interface Configuration Register */ |
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| 63 | #define OMAP_EMIFS_CONFIG_FR (1 << 4) |
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| 64 | #define OMAP_EMIFS_CONFIG_PDE (1 << 3) |
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| 65 | #define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) |
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| 66 | #define OMAP_EMIFS_CONFIG_BM (1 << 1) |
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| 67 | #define OMAP_EMIFS_CONFIG_WP (1 << 0) |
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| 68 | |
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| 69 | #define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n))) |
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| 70 | #define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n))) |
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| 71 | |
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| 72 | #endif /* __ASSEMBLER__ */ |
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| 73 | |
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| 74 | #endif /* __ASM_ARCH_TC_H */ |
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| 75 | |
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