1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * AM43xx Clock domains framework |
4 | * |
5 | * Copyright (C) 2013 Texas Instruments, Inc. |
6 | */ |
7 | |
8 | #include <linux/kernel.h> |
9 | #include <linux/io.h> |
10 | |
11 | #include "clockdomain.h" |
12 | #include "prcm44xx.h" |
13 | #include "prcm43xx.h" |
14 | |
15 | static struct clockdomain l4_cefuse_43xx_clkdm = { |
16 | .name = "l4_cefuse_clkdm" , |
17 | .pwrdm = { .name = "cefuse_pwrdm" }, |
18 | .prcm_partition = AM43XX_CM_PARTITION, |
19 | .cm_inst = AM43XX_CM_CEFUSE_INST, |
20 | .clkdm_offs = AM43XX_CM_CEFUSE_CEFUSE_CDOFFS, |
21 | .flags = CLKDM_CAN_SWSUP, |
22 | }; |
23 | |
24 | static struct clockdomain mpu_43xx_clkdm = { |
25 | .name = "mpu_clkdm" , |
26 | .pwrdm = { .name = "mpu_pwrdm" }, |
27 | .prcm_partition = AM43XX_CM_PARTITION, |
28 | .cm_inst = AM43XX_CM_MPU_INST, |
29 | .clkdm_offs = AM43XX_CM_MPU_MPU_CDOFFS, |
30 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
31 | }; |
32 | |
33 | static struct clockdomain l4ls_43xx_clkdm = { |
34 | .name = "l4ls_clkdm" , |
35 | .pwrdm = { .name = "per_pwrdm" }, |
36 | .prcm_partition = AM43XX_CM_PARTITION, |
37 | .cm_inst = AM43XX_CM_PER_INST, |
38 | .clkdm_offs = AM43XX_CM_PER_L4LS_CDOFFS, |
39 | .flags = CLKDM_CAN_SWSUP, |
40 | }; |
41 | |
42 | static struct clockdomain tamper_43xx_clkdm = { |
43 | .name = "tamper_clkdm" , |
44 | .pwrdm = { .name = "tamper_pwrdm" }, |
45 | .prcm_partition = AM43XX_CM_PARTITION, |
46 | .cm_inst = AM43XX_CM_TAMPER_INST, |
47 | .clkdm_offs = AM43XX_CM_TAMPER_TAMPER_CDOFFS, |
48 | .flags = CLKDM_CAN_SWSUP, |
49 | }; |
50 | |
51 | static struct clockdomain l4_rtc_43xx_clkdm = { |
52 | .name = "l4_rtc_clkdm" , |
53 | .pwrdm = { .name = "rtc_pwrdm" }, |
54 | .prcm_partition = AM43XX_CM_PARTITION, |
55 | .cm_inst = AM43XX_CM_RTC_INST, |
56 | .clkdm_offs = AM43XX_CM_RTC_RTC_CDOFFS, |
57 | .flags = CLKDM_CAN_SWSUP, |
58 | }; |
59 | |
60 | static struct clockdomain pruss_ocp_43xx_clkdm = { |
61 | .name = "pruss_ocp_clkdm" , |
62 | .pwrdm = { .name = "per_pwrdm" }, |
63 | .prcm_partition = AM43XX_CM_PARTITION, |
64 | .cm_inst = AM43XX_CM_PER_INST, |
65 | .clkdm_offs = AM43XX_CM_PER_ICSS_CDOFFS, |
66 | .flags = CLKDM_CAN_SWSUP, |
67 | }; |
68 | |
69 | static struct clockdomain ocpwp_l3_43xx_clkdm = { |
70 | .name = "ocpwp_l3_clkdm" , |
71 | .pwrdm = { .name = "per_pwrdm" }, |
72 | .prcm_partition = AM43XX_CM_PARTITION, |
73 | .cm_inst = AM43XX_CM_PER_INST, |
74 | .clkdm_offs = AM43XX_CM_PER_OCPWP_L3_CDOFFS, |
75 | .flags = CLKDM_CAN_SWSUP, |
76 | }; |
77 | |
78 | static struct clockdomain l3s_tsc_43xx_clkdm = { |
79 | .name = "l3s_tsc_clkdm" , |
80 | .pwrdm = { .name = "wkup_pwrdm" }, |
81 | .prcm_partition = AM43XX_CM_PARTITION, |
82 | .cm_inst = AM43XX_CM_WKUP_INST, |
83 | .clkdm_offs = AM43XX_CM_WKUP_L3S_TSC_CDOFFS, |
84 | .flags = CLKDM_CAN_SWSUP, |
85 | }; |
86 | |
87 | static struct clockdomain lcdc_43xx_clkdm = { |
88 | .name = "lcdc_clkdm" , |
89 | .pwrdm = { .name = "per_pwrdm" }, |
90 | .prcm_partition = AM43XX_CM_PARTITION, |
91 | .cm_inst = AM43XX_CM_PER_INST, |
92 | .clkdm_offs = AM43XX_CM_PER_LCDC_CDOFFS, |
93 | .flags = CLKDM_CAN_SWSUP, |
94 | }; |
95 | |
96 | static struct clockdomain dss_43xx_clkdm = { |
97 | .name = "dss_clkdm" , |
98 | .pwrdm = { .name = "per_pwrdm" }, |
99 | .prcm_partition = AM43XX_CM_PARTITION, |
100 | .cm_inst = AM43XX_CM_PER_INST, |
101 | .clkdm_offs = AM43XX_CM_PER_DSS_CDOFFS, |
102 | .flags = CLKDM_CAN_SWSUP, |
103 | }; |
104 | |
105 | static struct clockdomain l3_aon_43xx_clkdm = { |
106 | .name = "l3_aon_clkdm" , |
107 | .pwrdm = { .name = "wkup_pwrdm" }, |
108 | .prcm_partition = AM43XX_CM_PARTITION, |
109 | .cm_inst = AM43XX_CM_WKUP_INST, |
110 | .clkdm_offs = AM43XX_CM_WKUP_L3_AON_CDOFFS, |
111 | .flags = CLKDM_CAN_SWSUP, |
112 | }; |
113 | |
114 | static struct clockdomain emif_43xx_clkdm = { |
115 | .name = "emif_clkdm" , |
116 | .pwrdm = { .name = "per_pwrdm" }, |
117 | .prcm_partition = AM43XX_CM_PARTITION, |
118 | .cm_inst = AM43XX_CM_PER_INST, |
119 | .clkdm_offs = AM43XX_CM_PER_EMIF_CDOFFS, |
120 | .flags = CLKDM_CAN_SWSUP, |
121 | }; |
122 | |
123 | static struct clockdomain l4_wkup_aon_43xx_clkdm = { |
124 | .name = "l4_wkup_aon_clkdm" , |
125 | .pwrdm = { .name = "wkup_pwrdm" }, |
126 | .prcm_partition = AM43XX_CM_PARTITION, |
127 | .cm_inst = AM43XX_CM_WKUP_INST, |
128 | .clkdm_offs = AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS, |
129 | }; |
130 | |
131 | static struct clockdomain l3_43xx_clkdm = { |
132 | .name = "l3_clkdm" , |
133 | .pwrdm = { .name = "per_pwrdm" }, |
134 | .prcm_partition = AM43XX_CM_PARTITION, |
135 | .cm_inst = AM43XX_CM_PER_INST, |
136 | .clkdm_offs = AM43XX_CM_PER_L3_CDOFFS, |
137 | .flags = CLKDM_CAN_SWSUP, |
138 | }; |
139 | |
140 | static struct clockdomain l4_wkup_43xx_clkdm = { |
141 | .name = "l4_wkup_clkdm" , |
142 | .pwrdm = { .name = "wkup_pwrdm" }, |
143 | .prcm_partition = AM43XX_CM_PARTITION, |
144 | .cm_inst = AM43XX_CM_WKUP_INST, |
145 | .clkdm_offs = AM43XX_CM_WKUP_WKUP_CDOFFS, |
146 | .flags = CLKDM_CAN_SWSUP, |
147 | }; |
148 | |
149 | static struct clockdomain cpsw_125mhz_43xx_clkdm = { |
150 | .name = "cpsw_125mhz_clkdm" , |
151 | .pwrdm = { .name = "per_pwrdm" }, |
152 | .prcm_partition = AM43XX_CM_PARTITION, |
153 | .cm_inst = AM43XX_CM_PER_INST, |
154 | .clkdm_offs = AM43XX_CM_PER_CPSW_CDOFFS, |
155 | .flags = CLKDM_CAN_SWSUP, |
156 | }; |
157 | |
158 | static struct clockdomain gfx_l3_43xx_clkdm = { |
159 | .name = "gfx_l3_clkdm" , |
160 | .pwrdm = { .name = "gfx_pwrdm" }, |
161 | .prcm_partition = AM43XX_CM_PARTITION, |
162 | .cm_inst = AM43XX_CM_GFX_INST, |
163 | .clkdm_offs = AM43XX_CM_GFX_GFX_L3_CDOFFS, |
164 | .flags = CLKDM_CAN_SWSUP, |
165 | }; |
166 | |
167 | static struct clockdomain l3s_43xx_clkdm = { |
168 | .name = "l3s_clkdm" , |
169 | .pwrdm = { .name = "per_pwrdm" }, |
170 | .prcm_partition = AM43XX_CM_PARTITION, |
171 | .cm_inst = AM43XX_CM_PER_INST, |
172 | .clkdm_offs = AM43XX_CM_PER_L3S_CDOFFS, |
173 | .flags = CLKDM_CAN_SWSUP, |
174 | }; |
175 | |
176 | static struct clockdomain *clockdomains_am43xx[] __initdata = { |
177 | &l4_cefuse_43xx_clkdm, |
178 | &mpu_43xx_clkdm, |
179 | &l4ls_43xx_clkdm, |
180 | &tamper_43xx_clkdm, |
181 | &l4_rtc_43xx_clkdm, |
182 | &pruss_ocp_43xx_clkdm, |
183 | &ocpwp_l3_43xx_clkdm, |
184 | &l3s_tsc_43xx_clkdm, |
185 | &lcdc_43xx_clkdm, |
186 | &dss_43xx_clkdm, |
187 | &l3_aon_43xx_clkdm, |
188 | &emif_43xx_clkdm, |
189 | &l4_wkup_aon_43xx_clkdm, |
190 | &l3_43xx_clkdm, |
191 | &l4_wkup_43xx_clkdm, |
192 | &cpsw_125mhz_43xx_clkdm, |
193 | &gfx_l3_43xx_clkdm, |
194 | &l3s_43xx_clkdm, |
195 | NULL |
196 | }; |
197 | |
198 | void __init am43xx_clockdomains_init(void) |
199 | { |
200 | clkdm_register_platform_funcs(co: &am43xx_clkdm_operations); |
201 | clkdm_register_clkdms(c: clockdomains_am43xx); |
202 | clkdm_complete_init(); |
203 | } |
204 | |