| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * OMAP2/3 Clock Management (CM) register definitions |
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| 4 | * |
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| 5 | * Copyright (C) 2007-2009 Texas Instruments, Inc. |
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| 6 | * Copyright (C) 2007-2010 Nokia Corporation |
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| 7 | * Paul Walmsley |
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| 8 | * |
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| 9 | * The CM hardware modules on the OMAP2/3 are quite similar to each |
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| 10 | * other. The CM modules/instances on OMAP4 are quite different, so |
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| 11 | * they are handled in a separate file. |
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| 12 | */ |
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| 13 | #ifndef __ARCH_ASM_MACH_OMAP2_CM3XXX_H |
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| 14 | #define __ARCH_ASM_MACH_OMAP2_CM3XXX_H |
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| 15 | |
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| 16 | #include "prcm-common.h" |
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| 17 | #include "cm2xxx_3xxx.h" |
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| 18 | |
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| 19 | #define OMAP34XX_CM_REGADDR(module, reg) \ |
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| 20 | OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) |
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| 21 | |
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| 22 | |
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| 23 | /* |
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| 24 | * OMAP3-specific global CM registers |
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| 25 | * Use cm_{read,write}_reg() with these registers. |
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| 26 | * These registers appear once per CM module. |
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| 27 | */ |
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| 28 | |
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| 29 | #define OMAP3430_CM_SYSCONFIG 0x0010 |
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| 30 | #define OMAP3430_CM_POLCTRL 0x009c |
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| 31 | |
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| 32 | #define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 |
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| 33 | #define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) |
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| 34 | |
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| 35 | /* |
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| 36 | * Module specific CM register offsets from CM_BASE + domain offset |
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| 37 | * Use cm_{read,write}_mod_reg() with these registers. |
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| 38 | * These register offsets generally appear in more than one PRCM submodule. |
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| 39 | */ |
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| 40 | |
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| 41 | /* OMAP3-specific register offsets */ |
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| 42 | |
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| 43 | #define OMAP3430_CM_CLKEN_PLL 0x0004 |
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| 44 | #define OMAP3430ES2_CM_CLKEN2 0x0004 |
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| 45 | #define OMAP3430ES2_CM_FCLKEN3 0x0008 |
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| 46 | #define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 |
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| 47 | #define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 |
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| 48 | #define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2 |
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| 49 | #define OMAP3430_CM_CLKSEL1 CM_CLKSEL |
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| 50 | #define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL |
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| 51 | #define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 |
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| 52 | #define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 |
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| 53 | #define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL |
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| 54 | #define OMAP3430_CM_CLKSTST 0x004c |
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| 55 | #define OMAP3430ES2_CM_CLKSEL4 0x004c |
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| 56 | #define OMAP3430ES2_CM_CLKSEL5 0x0050 |
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| 57 | #define OMAP3430_CM_CLKSEL2_EMU 0x0050 |
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| 58 | #define OMAP3430_CM_CLKSEL3_EMU 0x0054 |
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| 59 | |
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| 60 | |
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| 61 | /* CM_IDLEST bit field values to indicate deasserted IdleReq */ |
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| 62 | |
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| 63 | #define OMAP34XX_CM_IDLEST_VAL 1 |
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| 64 | |
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| 65 | |
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| 66 | #ifndef __ASSEMBLER__ |
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| 67 | |
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| 68 | extern void omap3_cm_save_context(void); |
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| 69 | extern void omap3_cm_restore_context(void); |
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| 70 | extern void omap3_cm_save_scratchpad_contents(u32 *ptr); |
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| 71 | |
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| 72 | int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data); |
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| 73 | |
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| 74 | #endif |
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| 75 | |
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| 76 | #endif |
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| 77 | |
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