| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Created by: Dave Martin, 2012-06-22 |
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| 4 | * Copyright: (C) 2012-2013 Linaro Limited |
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| 5 | */ |
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| 6 | |
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| 7 | #include <linux/linkage.h> |
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| 8 | |
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| 9 | |
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| 10 | ENTRY(dcscb_power_up_setup) |
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| 11 | |
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| 12 | cmp r0, #0 @ check affinity level |
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| 13 | beq 2f |
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| 14 | |
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| 15 | /* |
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| 16 | * Enable cluster-level coherency, in preparation for turning on the MMU. |
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| 17 | * The ACTLR SMP bit does not need to be set here, because cpu_resume() |
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| 18 | * already restores that. |
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| 19 | * |
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| 20 | * A15/A7 may not require explicit L2 invalidation on reset, dependent |
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| 21 | * on hardware integration decisions. |
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| 22 | * For now, this code assumes that L2 is either already invalidated, |
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| 23 | * or invalidation is not required. |
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| 24 | */ |
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| 25 | |
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| 26 | b cci_enable_port_for_self |
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| 27 | |
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| 28 | 2: @ Implementation-specific local CPU setup operations should go here, |
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| 29 | @ if any. In this case, there is nothing to do. |
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| 30 | |
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| 31 | bx lr |
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| 32 | |
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| 33 | ENDPROC(dcscb_power_up_setup) |
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| 34 | |
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