| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * This file contains the hardware definitions of the Integrator. |
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| 4 | * |
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| 5 | * Copyright (C) 1998-1999 ARM Limited. |
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| 6 | */ |
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| 7 | #ifndef INTEGRATOR_HARDWARE_H |
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| 8 | #define INTEGRATOR_HARDWARE_H |
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| 9 | |
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| 10 | /* |
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| 11 | * Where in virtual memory the IO devices (timers, system controllers |
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| 12 | * and so on) |
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| 13 | */ |
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| 14 | #define IO_BASE 0xF0000000 // VA of IO |
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| 15 | #define IO_SIZE 0x0B000000 // How much? |
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| 16 | #define IO_START INTEGRATOR_HDR_BASE // PA of IO |
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| 17 | |
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| 18 | /* macro to get at IO space when running virtually */ |
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| 19 | #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE) |
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| 20 | #define __io_address(n) ((void __iomem *)IO_ADDRESS(n)) |
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| 21 | |
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| 22 | /* |
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| 23 | * Integrator memory map |
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| 24 | */ |
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| 25 | #define INTEGRATOR_BOOT_ROM_LO 0x00000000 |
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| 26 | #define INTEGRATOR_BOOT_ROM_HI 0x20000000 |
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| 27 | #define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */ |
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| 28 | #define INTEGRATOR_BOOT_ROM_SIZE SZ_512K |
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| 29 | |
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| 30 | /* |
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| 31 | * New Core Modules have different amounts of SSRAM, the amount of SSRAM |
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| 32 | * fitted can be found in HDR_STAT. |
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| 33 | * |
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| 34 | * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to |
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| 35 | * the minimum amount of SSRAM fitted on any core module. |
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| 36 | * |
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| 37 | * New Core Modules also alias the SSRAM. |
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| 38 | * |
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| 39 | */ |
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| 40 | #define INTEGRATOR_SSRAM_BASE 0x00000000 |
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| 41 | #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000 |
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| 42 | #define INTEGRATOR_SSRAM_SIZE SZ_256K |
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| 43 | |
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| 44 | #define INTEGRATOR_FLASH_BASE 0x24000000 |
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| 45 | #define INTEGRATOR_FLASH_SIZE SZ_32M |
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| 46 | |
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| 47 | #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000 |
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| 48 | #define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K |
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| 49 | |
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| 50 | /* |
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| 51 | * SDRAM is a SIMM therefore the size is not known. |
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| 52 | */ |
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| 53 | #define INTEGRATOR_SDRAM_BASE 0x00040000 |
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| 54 | |
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| 55 | #define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000 |
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| 56 | #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 |
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| 57 | #define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000 |
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| 58 | #define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000 |
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| 59 | #define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000 |
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| 60 | |
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| 61 | /* |
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| 62 | * Logic expansion modules |
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| 63 | * |
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| 64 | */ |
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| 65 | #define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000 |
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| 66 | #define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000 |
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| 67 | #define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000 |
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| 68 | #define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000 |
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| 69 | #define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000 |
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| 70 | |
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| 71 | /* |
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| 72 | * Integrator header card registers |
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| 73 | */ |
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| 74 | #define INTEGRATOR_HDR_ID_OFFSET 0x00 |
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| 75 | #define INTEGRATOR_HDR_PROC_OFFSET 0x04 |
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| 76 | #define INTEGRATOR_HDR_OSC_OFFSET 0x08 |
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| 77 | #define INTEGRATOR_HDR_CTRL_OFFSET 0x0C |
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| 78 | #define INTEGRATOR_HDR_STAT_OFFSET 0x10 |
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| 79 | #define INTEGRATOR_HDR_LOCK_OFFSET 0x14 |
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| 80 | #define INTEGRATOR_HDR_SDRAM_OFFSET 0x20 |
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| 81 | #define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */ |
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| 82 | #define INTEGRATOR_HDR_IC_OFFSET 0x40 |
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| 83 | #define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100 |
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| 84 | #define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200 |
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| 85 | |
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| 86 | #define INTEGRATOR_HDR_BASE 0x10000000 |
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| 87 | #define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET) |
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| 88 | #define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET) |
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| 89 | #define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET) |
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| 90 | #define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET) |
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| 91 | #define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET) |
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| 92 | #define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET) |
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| 93 | #define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET) |
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| 94 | #define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET) |
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| 95 | #define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET) |
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| 96 | #define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET) |
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| 97 | #define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET) |
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| 98 | |
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| 99 | #define INTEGRATOR_HDR_CTRL_LED 0x01 |
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| 100 | #define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02 |
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| 101 | #define INTEGRATOR_HDR_CTRL_REMAP 0x04 |
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| 102 | #define INTEGRATOR_HDR_CTRL_RESET 0x08 |
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| 103 | #define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10 |
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| 104 | #define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20 |
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| 105 | #define INTEGRATOR_HDR_CTRL_FASTBUS 0x40 |
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| 106 | #define INTEGRATOR_HDR_CTRL_SYNC 0x80 |
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| 107 | |
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| 108 | #define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102 |
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| 109 | #define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107 |
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| 110 | #define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C |
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| 111 | #define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111 |
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| 112 | #define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116 |
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| 113 | #define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B |
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| 114 | #define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120 |
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| 115 | #define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125 |
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| 116 | #define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A |
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| 117 | #define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F |
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| 118 | #define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134 |
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| 119 | #define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139 |
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| 120 | #define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E |
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| 121 | #define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143 |
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| 122 | #define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148 |
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| 123 | #define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D |
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| 124 | #define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152 |
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| 125 | #define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157 |
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| 126 | #define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C |
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| 127 | #define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161 |
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| 128 | #define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166 |
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| 129 | #define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B |
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| 130 | #define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170 |
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| 131 | #define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175 |
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| 132 | #define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A |
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| 133 | #define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F |
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| 134 | #define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184 |
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| 135 | #define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189 |
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| 136 | #define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E |
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| 137 | #define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193 |
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| 138 | #define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198 |
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| 139 | #define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF |
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| 140 | |
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| 141 | #define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000 |
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| 142 | #define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000 |
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| 143 | #define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000 |
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| 144 | #define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000 |
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| 145 | #define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000 |
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| 146 | #define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000 |
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| 147 | #define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000 |
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| 148 | #define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000 |
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| 149 | #define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000 |
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| 150 | #define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000 |
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| 151 | #define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000 |
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| 152 | |
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| 153 | #define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0 |
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| 154 | #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000 |
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| 155 | #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000 |
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| 156 | #define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000 |
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| 157 | #define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000 |
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| 158 | |
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| 159 | #define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5) |
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| 160 | |
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| 161 | /* |
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| 162 | * Integrator system registers |
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| 163 | */ |
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| 164 | |
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| 165 | /* |
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| 166 | * System Controller |
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| 167 | */ |
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| 168 | #define INTEGRATOR_SC_ID_OFFSET 0x00 |
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| 169 | #define INTEGRATOR_SC_OSC_OFFSET 0x04 |
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| 170 | #define INTEGRATOR_SC_CTRLS_OFFSET 0x08 |
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| 171 | #define INTEGRATOR_SC_CTRLC_OFFSET 0x0C |
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| 172 | #define INTEGRATOR_SC_DEC_OFFSET 0x10 |
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| 173 | #define INTEGRATOR_SC_ARB_OFFSET 0x14 |
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| 174 | #define INTEGRATOR_SC_LOCK_OFFSET 0x1C |
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| 175 | |
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| 176 | #define INTEGRATOR_SC_BASE 0x11000000 |
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| 177 | #define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET) |
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| 178 | #define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET) |
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| 179 | #define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET) |
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| 180 | #define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET) |
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| 181 | #define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET) |
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| 182 | #define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET) |
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| 183 | #define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) |
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| 184 | #define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET) |
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| 185 | |
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| 186 | #define INTEGRATOR_SC_OSC_SYS_10MHz 0x20 |
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| 187 | #define INTEGRATOR_SC_OSC_SYS_15MHz 0x34 |
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| 188 | #define INTEGRATOR_SC_OSC_SYS_20MHz 0x48 |
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| 189 | #define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C |
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| 190 | #define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C |
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| 191 | #define INTEGRATOR_SC_OSC_SYS_MASK 0xFF |
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| 192 | |
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| 193 | #define INTEGRATOR_SC_OSC_PCI_25MHz 0x100 |
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| 194 | #define INTEGRATOR_SC_OSC_PCI_33MHz 0x0 |
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| 195 | #define INTEGRATOR_SC_OSC_PCI_MASK 0x100 |
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| 196 | |
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| 197 | #define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0) |
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| 198 | #define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1) |
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| 199 | #define INTEGRATOR_SC_CTRL_nFLWP (1 << 2) |
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| 200 | #define INTEGRATOR_SC_CTRL_URTS0 (1 << 4) |
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| 201 | #define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5) |
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| 202 | #define INTEGRATOR_SC_CTRL_URTS1 (1 << 6) |
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| 203 | #define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7) |
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| 204 | |
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| 205 | /* |
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| 206 | * External Bus Interface |
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| 207 | */ |
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| 208 | #define INTEGRATOR_EBI_BASE 0x12000000 |
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| 209 | |
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| 210 | #define INTEGRATOR_EBI_CSR0_OFFSET 0x00 |
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| 211 | #define INTEGRATOR_EBI_CSR1_OFFSET 0x04 |
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| 212 | #define INTEGRATOR_EBI_CSR2_OFFSET 0x08 |
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| 213 | #define INTEGRATOR_EBI_CSR3_OFFSET 0x0C |
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| 214 | #define INTEGRATOR_EBI_LOCK_OFFSET 0x20 |
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| 215 | |
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| 216 | #define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET) |
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| 217 | #define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) |
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| 218 | #define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET) |
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| 219 | #define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET) |
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| 220 | #define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) |
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| 221 | |
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| 222 | #define INTEGRATOR_EBI_8_BIT 0x00 |
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| 223 | #define INTEGRATOR_EBI_16_BIT 0x01 |
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| 224 | #define INTEGRATOR_EBI_32_BIT 0x02 |
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| 225 | #define INTEGRATOR_EBI_WRITE_ENABLE 0x04 |
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| 226 | #define INTEGRATOR_EBI_SYNC 0x08 |
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| 227 | #define INTEGRATOR_EBI_WS_2 0x00 |
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| 228 | #define INTEGRATOR_EBI_WS_3 0x10 |
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| 229 | #define INTEGRATOR_EBI_WS_4 0x20 |
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| 230 | #define INTEGRATOR_EBI_WS_5 0x30 |
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| 231 | #define INTEGRATOR_EBI_WS_6 0x40 |
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| 232 | #define INTEGRATOR_EBI_WS_7 0x50 |
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| 233 | #define INTEGRATOR_EBI_WS_8 0x60 |
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| 234 | #define INTEGRATOR_EBI_WS_9 0x70 |
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| 235 | #define INTEGRATOR_EBI_WS_10 0x80 |
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| 236 | #define INTEGRATOR_EBI_WS_11 0x90 |
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| 237 | #define INTEGRATOR_EBI_WS_12 0xA0 |
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| 238 | #define INTEGRATOR_EBI_WS_13 0xB0 |
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| 239 | #define INTEGRATOR_EBI_WS_14 0xC0 |
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| 240 | #define INTEGRATOR_EBI_WS_15 0xD0 |
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| 241 | #define INTEGRATOR_EBI_WS_16 0xE0 |
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| 242 | #define INTEGRATOR_EBI_WS_17 0xF0 |
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| 243 | |
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| 244 | |
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| 245 | #define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */ |
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| 246 | #define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */ |
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| 247 | #define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */ |
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| 248 | #define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */ |
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| 249 | #define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */ |
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| 250 | #define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */ |
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| 251 | #define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */ |
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| 252 | |
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| 253 | /* |
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| 254 | * LED's & Switches |
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| 255 | */ |
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| 256 | #define INTEGRATOR_DBG_ALPHA_OFFSET 0x00 |
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| 257 | #define INTEGRATOR_DBG_LEDS_OFFSET 0x04 |
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| 258 | #define INTEGRATOR_DBG_SWITCH_OFFSET 0x08 |
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| 259 | |
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| 260 | #define INTEGRATOR_DBG_BASE 0x1A000000 |
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| 261 | #define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET) |
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| 262 | #define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET) |
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| 263 | #define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET) |
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| 264 | |
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| 265 | #define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */ |
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| 266 | |
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| 267 | #define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */ |
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| 268 | #define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */ |
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| 269 | #define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */ |
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| 270 | #define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */ |
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| 271 | #define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */ |
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| 272 | #define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */ |
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| 273 | |
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| 274 | /* PS2 Keyboard interface */ |
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| 275 | #define KMI0_BASE INTEGRATOR_KBD_BASE |
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| 276 | |
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| 277 | /* PS2 Mouse interface */ |
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| 278 | #define KMI1_BASE INTEGRATOR_MOUSE_BASE |
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| 279 | |
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| 280 | /* |
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| 281 | * Integrator Interrupt Controllers |
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| 282 | * |
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| 283 | * |
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| 284 | * Offsets from interrupt controller base |
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| 285 | * |
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| 286 | * System Controller interrupt controller base is |
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| 287 | * |
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| 288 | * INTEGRATOR_IC_BASE + (header_number << 6) |
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| 289 | * |
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| 290 | * Core Module interrupt controller base is |
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| 291 | * |
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| 292 | * INTEGRATOR_HDR_IC |
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| 293 | */ |
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| 294 | #define IRQ_STATUS 0 |
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| 295 | #define IRQ_RAW_STATUS 0x04 |
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| 296 | #define IRQ_ENABLE 0x08 |
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| 297 | #define IRQ_ENABLE_SET 0x08 |
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| 298 | #define IRQ_ENABLE_CLEAR 0x0C |
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| 299 | |
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| 300 | #define INT_SOFT_SET 0x10 |
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| 301 | #define INT_SOFT_CLEAR 0x14 |
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| 302 | |
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| 303 | #define FIQ_STATUS 0x20 |
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| 304 | #define FIQ_RAW_STATUS 0x24 |
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| 305 | #define FIQ_ENABLE 0x28 |
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| 306 | #define FIQ_ENABLE_SET 0x28 |
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| 307 | #define FIQ_ENABLE_CLEAR 0x2C |
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| 308 | |
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| 309 | |
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| 310 | /* |
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| 311 | * LED's |
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| 312 | */ |
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| 313 | #define GREEN_LED 0x01 |
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| 314 | #define YELLOW_LED 0x02 |
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| 315 | #define RED_LED 0x04 |
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| 316 | #define GREEN_LED_2 0x08 |
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| 317 | #define ALL_LEDS 0x0F |
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| 318 | |
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| 319 | #define LED_BANK INTEGRATOR_DBG_LEDS |
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| 320 | |
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| 321 | /* |
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| 322 | * Timer definitions |
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| 323 | * |
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| 324 | * Only use timer 1 & 2 |
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| 325 | * (both run at 24MHz and will need the clock divider set to 16). |
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| 326 | * |
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| 327 | * Timer 0 runs at bus frequency |
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| 328 | */ |
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| 329 | #define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE |
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| 330 | #define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) |
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| 331 | #define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) |
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| 332 | |
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| 333 | #define INTEGRATOR_CSR_BASE 0x10000000 |
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| 334 | #define INTEGRATOR_CSR_SIZE 0x10000000 |
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| 335 | |
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| 336 | #endif /* INTEGRATOR_HARDWARE_H */ |
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| 337 | |
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