1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * linux/arch/arm/mm/proc-arm920.S: MMU functions for ARM920 |
4 | * |
5 | * Copyright (C) 1999,2000 ARM Limited |
6 | * Copyright (C) 2000 Deep Blue Solutions Ltd. |
7 | * hacked for non-paged-MM by Hyok S. Choi, 2003. |
8 | * |
9 | * These are the low level assembler for performing cache and TLB |
10 | * functions on the arm920. |
11 | * |
12 | * CONFIG_CPU_ARM920_CPU_IDLE -> nohlt |
13 | */ |
14 | #include <linux/linkage.h> |
15 | #include <linux/init.h> |
16 | #include <linux/pgtable.h> |
17 | #include <asm/assembler.h> |
18 | #include <asm/hwcap.h> |
19 | #include <asm/pgtable-hwdef.h> |
20 | #include <asm/page.h> |
21 | #include <asm/ptrace.h> |
22 | #include "proc-macros.S" |
23 | |
24 | /* |
25 | * The size of one data cache line. |
26 | */ |
27 | #define CACHE_DLINESIZE 32 |
28 | |
29 | /* |
30 | * The number of data cache segments. |
31 | */ |
32 | #define CACHE_DSEGMENTS 8 |
33 | |
34 | /* |
35 | * The number of lines in a cache segment. |
36 | */ |
37 | #define CACHE_DENTRIES 64 |
38 | |
39 | /* |
40 | * This is the size at which it becomes more efficient to |
41 | * clean the whole cache, rather than using the individual |
42 | * cache line maintenance instructions. |
43 | */ |
44 | #define CACHE_DLIMIT 65536 |
45 | |
46 | |
47 | .text |
48 | /* |
49 | * cpu_arm920_proc_init() |
50 | */ |
51 | ENTRY(cpu_arm920_proc_init) |
52 | ret lr |
53 | |
54 | /* |
55 | * cpu_arm920_proc_fin() |
56 | */ |
57 | ENTRY(cpu_arm920_proc_fin) |
58 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
59 | bic r0, r0, #0x1000 @ ...i............ |
60 | bic r0, r0, #0x000e @ ............wca. |
61 | mcr p15, 0, r0, c1, c0, 0 @ disable caches |
62 | ret lr |
63 | |
64 | /* |
65 | * cpu_arm920_reset(loc) |
66 | * |
67 | * Perform a soft reset of the system. Put the CPU into the |
68 | * same state as it would be if it had been reset, and branch |
69 | * to what would be the reset vector. |
70 | * |
71 | * loc: location to jump to for soft reset |
72 | */ |
73 | .align 5 |
74 | .pushsection .idmap.text, "ax" |
75 | ENTRY(cpu_arm920_reset) |
76 | mov ip, #0 |
77 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches |
78 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
79 | #ifdef CONFIG_MMU |
80 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
81 | #endif |
82 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register |
83 | bic ip, ip, #0x000f @ ............wcam |
84 | bic ip, ip, #0x1100 @ ...i...s........ |
85 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
86 | ret r0 |
87 | ENDPROC(cpu_arm920_reset) |
88 | .popsection |
89 | |
90 | /* |
91 | * cpu_arm920_do_idle() |
92 | */ |
93 | .align 5 |
94 | ENTRY(cpu_arm920_do_idle) |
95 | mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt |
96 | ret lr |
97 | |
98 | |
99 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH |
100 | |
101 | /* |
102 | * flush_icache_all() |
103 | * |
104 | * Unconditionally clean and invalidate the entire icache. |
105 | */ |
106 | ENTRY(arm920_flush_icache_all) |
107 | mov r0, #0 |
108 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache |
109 | ret lr |
110 | ENDPROC(arm920_flush_icache_all) |
111 | |
112 | /* |
113 | * flush_user_cache_all() |
114 | * |
115 | * Invalidate all cache entries in a particular address |
116 | * space. |
117 | */ |
118 | ENTRY(arm920_flush_user_cache_all) |
119 | /* FALLTHROUGH */ |
120 | |
121 | /* |
122 | * flush_kern_cache_all() |
123 | * |
124 | * Clean and invalidate the entire cache. |
125 | */ |
126 | ENTRY(arm920_flush_kern_cache_all) |
127 | mov r2, #VM_EXEC |
128 | mov ip, #0 |
129 | __flush_whole_cache: |
130 | mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments |
131 | 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries |
132 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index |
133 | subs r3, r3, #1 << 26 |
134 | bcs 2b @ entries 63 to 0 |
135 | subs r1, r1, #1 << 5 |
136 | bcs 1b @ segments 7 to 0 |
137 | tst r2, #VM_EXEC |
138 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache |
139 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB |
140 | ret lr |
141 | |
142 | /* |
143 | * flush_user_cache_range(start, end, flags) |
144 | * |
145 | * Invalidate a range of cache entries in the specified |
146 | * address space. |
147 | * |
148 | * - start - start address (inclusive) |
149 | * - end - end address (exclusive) |
150 | * - flags - vm_flags for address space |
151 | */ |
152 | ENTRY(arm920_flush_user_cache_range) |
153 | mov ip, #0 |
154 | sub r3, r1, r0 @ calculate total size |
155 | cmp r3, #CACHE_DLIMIT |
156 | bhs __flush_whole_cache |
157 | |
158 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |
159 | tst r2, #VM_EXEC |
160 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry |
161 | add r0, r0, #CACHE_DLINESIZE |
162 | cmp r0, r1 |
163 | blo 1b |
164 | tst r2, #VM_EXEC |
165 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB |
166 | ret lr |
167 | |
168 | /* |
169 | * coherent_kern_range(start, end) |
170 | * |
171 | * Ensure coherency between the Icache and the Dcache in the |
172 | * region described by start, end. If you have non-snooping |
173 | * Harvard caches, you need to implement this function. |
174 | * |
175 | * - start - virtual start address |
176 | * - end - virtual end address |
177 | */ |
178 | ENTRY(arm920_coherent_kern_range) |
179 | /* FALLTHROUGH */ |
180 | |
181 | /* |
182 | * coherent_user_range(start, end) |
183 | * |
184 | * Ensure coherency between the Icache and the Dcache in the |
185 | * region described by start, end. If you have non-snooping |
186 | * Harvard caches, you need to implement this function. |
187 | * |
188 | * - start - virtual start address |
189 | * - end - virtual end address |
190 | */ |
191 | ENTRY(arm920_coherent_user_range) |
192 | bic r0, r0, #CACHE_DLINESIZE - 1 |
193 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
194 | mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry |
195 | add r0, r0, #CACHE_DLINESIZE |
196 | cmp r0, r1 |
197 | blo 1b |
198 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
199 | mov r0, #0 |
200 | ret lr |
201 | |
202 | /* |
203 | * flush_kern_dcache_area(void *addr, size_t size) |
204 | * |
205 | * Ensure no D cache aliasing occurs, either with itself or |
206 | * the I cache |
207 | * |
208 | * - addr - kernel address |
209 | * - size - region size |
210 | */ |
211 | ENTRY(arm920_flush_kern_dcache_area) |
212 | add r1, r0, r1 |
213 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |
214 | add r0, r0, #CACHE_DLINESIZE |
215 | cmp r0, r1 |
216 | blo 1b |
217 | mov r0, #0 |
218 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache |
219 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
220 | ret lr |
221 | |
222 | /* |
223 | * dma_inv_range(start, end) |
224 | * |
225 | * Invalidate (discard) the specified virtual address range. |
226 | * May not write back any entries. If 'start' or 'end' |
227 | * are not cache line aligned, those lines must be written |
228 | * back. |
229 | * |
230 | * - start - virtual start address |
231 | * - end - virtual end address |
232 | * |
233 | * (same as v4wb) |
234 | */ |
235 | arm920_dma_inv_range: |
236 | tst r0, #CACHE_DLINESIZE - 1 |
237 | bic r0, r0, #CACHE_DLINESIZE - 1 |
238 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
239 | tst r1, #CACHE_DLINESIZE - 1 |
240 | mcrne p15, 0, r1, c7, c10, 1 @ clean D entry |
241 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry |
242 | add r0, r0, #CACHE_DLINESIZE |
243 | cmp r0, r1 |
244 | blo 1b |
245 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
246 | ret lr |
247 | |
248 | /* |
249 | * dma_clean_range(start, end) |
250 | * |
251 | * Clean the specified virtual address range. |
252 | * |
253 | * - start - virtual start address |
254 | * - end - virtual end address |
255 | * |
256 | * (same as v4wb) |
257 | */ |
258 | arm920_dma_clean_range: |
259 | bic r0, r0, #CACHE_DLINESIZE - 1 |
260 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
261 | add r0, r0, #CACHE_DLINESIZE |
262 | cmp r0, r1 |
263 | blo 1b |
264 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
265 | ret lr |
266 | |
267 | /* |
268 | * dma_flush_range(start, end) |
269 | * |
270 | * Clean and invalidate the specified virtual address range. |
271 | * |
272 | * - start - virtual start address |
273 | * - end - virtual end address |
274 | */ |
275 | ENTRY(arm920_dma_flush_range) |
276 | bic r0, r0, #CACHE_DLINESIZE - 1 |
277 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |
278 | add r0, r0, #CACHE_DLINESIZE |
279 | cmp r0, r1 |
280 | blo 1b |
281 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
282 | ret lr |
283 | |
284 | /* |
285 | * dma_map_area(start, size, dir) |
286 | * - start - kernel virtual start address |
287 | * - size - size of region |
288 | * - dir - DMA direction |
289 | */ |
290 | ENTRY(arm920_dma_map_area) |
291 | add r1, r1, r0 |
292 | cmp r2, #DMA_TO_DEVICE |
293 | beq arm920_dma_clean_range |
294 | bcs arm920_dma_inv_range |
295 | b arm920_dma_flush_range |
296 | ENDPROC(arm920_dma_map_area) |
297 | |
298 | /* |
299 | * dma_unmap_area(start, size, dir) |
300 | * - start - kernel virtual start address |
301 | * - size - size of region |
302 | * - dir - DMA direction |
303 | */ |
304 | ENTRY(arm920_dma_unmap_area) |
305 | ret lr |
306 | ENDPROC(arm920_dma_unmap_area) |
307 | |
308 | .globl arm920_flush_kern_cache_louis |
309 | .equ arm920_flush_kern_cache_louis, arm920_flush_kern_cache_all |
310 | |
311 | @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) |
312 | define_cache_functions arm920 |
313 | #endif |
314 | |
315 | |
316 | ENTRY(cpu_arm920_dcache_clean_area) |
317 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
318 | add r0, r0, #CACHE_DLINESIZE |
319 | subs r1, r1, #CACHE_DLINESIZE |
320 | bhi 1b |
321 | ret lr |
322 | |
323 | /* =============================== PageTable ============================== */ |
324 | |
325 | /* |
326 | * cpu_arm920_switch_mm(pgd) |
327 | * |
328 | * Set the translation base pointer to be as described by pgd. |
329 | * |
330 | * pgd: new page tables |
331 | */ |
332 | .align 5 |
333 | ENTRY(cpu_arm920_switch_mm) |
334 | #ifdef CONFIG_MMU |
335 | mov ip, #0 |
336 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH |
337 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache |
338 | #else |
339 | @ && 'Clean & Invalidate whole DCache' |
340 | @ && Re-written to use Index Ops. |
341 | @ && Uses registers r1, r3 and ip |
342 | |
343 | mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments |
344 | 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries |
345 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index |
346 | subs r3, r3, #1 << 26 |
347 | bcs 2b @ entries 63 to 0 |
348 | subs r1, r1, #1 << 5 |
349 | bcs 1b @ segments 7 to 0 |
350 | #endif |
351 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache |
352 | mcr p15, 0, ip, c7, c10, 4 @ drain WB |
353 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer |
354 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
355 | #endif |
356 | ret lr |
357 | |
358 | /* |
359 | * cpu_arm920_set_pte(ptep, pte, ext) |
360 | * |
361 | * Set a PTE and flush it out |
362 | */ |
363 | .align 5 |
364 | ENTRY(cpu_arm920_set_pte_ext) |
365 | #ifdef CONFIG_MMU |
366 | armv3_set_pte_ext |
367 | mov r0, r0 |
368 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
369 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
370 | #endif |
371 | ret lr |
372 | |
373 | /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ |
374 | .globl cpu_arm920_suspend_size |
375 | .equ cpu_arm920_suspend_size, 4 * 3 |
376 | #ifdef CONFIG_ARM_CPU_SUSPEND |
377 | ENTRY(cpu_arm920_do_suspend) |
378 | stmfd sp!, {r4 - r6, lr} |
379 | mrc p15, 0, r4, c13, c0, 0 @ PID |
380 | mrc p15, 0, r5, c3, c0, 0 @ Domain ID |
381 | mrc p15, 0, r6, c1, c0, 0 @ Control register |
382 | stmia r0, {r4 - r6} |
383 | ldmfd sp!, {r4 - r6, pc} |
384 | ENDPROC(cpu_arm920_do_suspend) |
385 | |
386 | ENTRY(cpu_arm920_do_resume) |
387 | mov ip, #0 |
388 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs |
389 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches |
390 | ldmia r0, {r4 - r6} |
391 | mcr p15, 0, r4, c13, c0, 0 @ PID |
392 | mcr p15, 0, r5, c3, c0, 0 @ Domain ID |
393 | mcr p15, 0, r1, c2, c0, 0 @ TTB address |
394 | mov r0, r6 @ control register |
395 | b cpu_resume_mmu |
396 | ENDPROC(cpu_arm920_do_resume) |
397 | #endif |
398 | |
399 | .type __arm920_setup, #function |
400 | __arm920_setup: |
401 | mov r0, #0 |
402 | mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 |
403 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 |
404 | #ifdef CONFIG_MMU |
405 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 |
406 | #endif |
407 | adr r5, arm920_crval |
408 | ldmia r5, {r5, r6} |
409 | mrc p15, 0, r0, c1, c0 @ get control register v4 |
410 | bic r0, r0, r5 |
411 | orr r0, r0, r6 |
412 | ret lr |
413 | .size __arm920_setup, . - __arm920_setup |
414 | |
415 | /* |
416 | * R |
417 | * .RVI ZFRS BLDP WCAM |
418 | * ..11 0001 ..11 0101 |
419 | * |
420 | */ |
421 | .type arm920_crval, #object |
422 | arm920_crval: |
423 | crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130 |
424 | |
425 | __INITDATA |
426 | @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) |
427 | define_processor_functions arm920, dabort=v4t_early_abort, pabort=legacy_pabort, suspend=1 |
428 | |
429 | .section ".rodata" |
430 | |
431 | string cpu_arch_name, "armv4t" |
432 | string cpu_elf_name, "v4" |
433 | string cpu_arm920_name, "ARM920T" |
434 | |
435 | .align |
436 | |
437 | .section ".proc.info.init" , "a" |
438 | |
439 | .type __arm920_proc_info,#object |
440 | __arm920_proc_info: |
441 | .long 0x41009200 |
442 | .long 0xff00fff0 |
443 | .long PMD_TYPE_SECT | \ |
444 | PMD_SECT_BUFFERABLE | \ |
445 | PMD_SECT_CACHEABLE | \ |
446 | PMD_BIT4 | \ |
447 | PMD_SECT_AP_WRITE | \ |
448 | PMD_SECT_AP_READ |
449 | .long PMD_TYPE_SECT | \ |
450 | PMD_BIT4 | \ |
451 | PMD_SECT_AP_WRITE | \ |
452 | PMD_SECT_AP_READ |
453 | initfn __arm920_setup, __arm920_proc_info |
454 | .long cpu_arch_name |
455 | .long cpu_elf_name |
456 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB |
457 | .long cpu_arm920_name |
458 | .long arm920_processor_functions |
459 | .long v4wbi_tlb_fns |
460 | .long v4wb_user_fns |
461 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH |
462 | .long arm920_cache_fns |
463 | #else |
464 | .long v4wt_cache_fns |
465 | #endif |
466 | .size __arm920_proc_info, . - __arm920_proc_info |
467 | |