1 | /* |
2 | * Support for MicroBlaze PVR (processor version register) |
3 | * |
4 | * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> |
5 | * Copyright (C) 2007-2009 PetaLogix |
6 | * Copyright (C) 2007 John Williams <john.williams@petalogix.com> |
7 | * |
8 | * This file is subject to the terms and conditions of the GNU General Public |
9 | * License. See the file "COPYING" in the main directory of this archive |
10 | * for more details. |
11 | */ |
12 | |
13 | #include <linux/init.h> |
14 | #include <linux/string.h> |
15 | #include <asm/pvr.h> |
16 | #include <asm/cpuinfo.h> |
17 | |
18 | /* |
19 | * Helper macro to map between fields in our struct cpuinfo, and |
20 | * the PVR macros in pvr.h. |
21 | */ |
22 | |
23 | #define CI(c, p) { ci->c = PVR_##p(pvr); } |
24 | |
25 | #define err_printk(x) \ |
26 | pr_err("ERROR: Microblaze " x "-different for PVR and DTS\n"); |
27 | |
28 | void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu) |
29 | { |
30 | struct pvr_s pvr; |
31 | u32 temp; /* for saving temp value */ |
32 | get_pvr(&pvr); |
33 | |
34 | CI(ver_code, VERSION); |
35 | if (!ci->ver_code) { |
36 | pr_err("ERROR: MB has broken PVR regs -> use DTS setting\n" ); |
37 | return; |
38 | } |
39 | |
40 | temp = PVR_USE_BARREL(pvr) | PVR_USE_MSR_INSTR(pvr) | |
41 | PVR_USE_PCMP_INSTR(pvr) | PVR_USE_DIV(pvr); |
42 | if (ci->use_instr != temp) |
43 | err_printk("BARREL, MSR, PCMP or DIV" ); |
44 | ci->use_instr = temp; |
45 | |
46 | temp = PVR_USE_HW_MUL(pvr) | PVR_USE_MUL64(pvr); |
47 | if (ci->use_mult != temp) |
48 | err_printk("HW_MUL" ); |
49 | ci->use_mult = temp; |
50 | |
51 | temp = PVR_USE_FPU(pvr) | PVR_USE_FPU2(pvr); |
52 | if (ci->use_fpu != temp) |
53 | err_printk("HW_FPU" ); |
54 | ci->use_fpu = temp; |
55 | |
56 | ci->use_exc = PVR_OPCODE_0x0_ILLEGAL(pvr) | |
57 | PVR_UNALIGNED_EXCEPTION(pvr) | |
58 | PVR_ILL_OPCODE_EXCEPTION(pvr) | |
59 | PVR_IOPB_BUS_EXCEPTION(pvr) | |
60 | PVR_DOPB_BUS_EXCEPTION(pvr) | |
61 | PVR_DIV_ZERO_EXCEPTION(pvr) | |
62 | PVR_FPU_EXCEPTION(pvr) | |
63 | PVR_FSL_EXCEPTION(pvr); |
64 | |
65 | CI(pvr_user1, USER1); |
66 | CI(pvr_user2, USER2); |
67 | |
68 | CI(mmu, USE_MMU); |
69 | CI(mmu_privins, MMU_PRIVINS); |
70 | CI(endian, ENDIAN); |
71 | |
72 | CI(use_icache, USE_ICACHE); |
73 | CI(icache_tagbits, ICACHE_ADDR_TAG_BITS); |
74 | CI(icache_write, ICACHE_ALLOW_WR); |
75 | ci->icache_line_length = PVR_ICACHE_LINE_LEN(pvr) << 2; |
76 | CI(icache_size, ICACHE_BYTE_SIZE); |
77 | CI(icache_base, ICACHE_BASEADDR); |
78 | CI(icache_high, ICACHE_HIGHADDR); |
79 | |
80 | CI(use_dcache, USE_DCACHE); |
81 | CI(dcache_tagbits, DCACHE_ADDR_TAG_BITS); |
82 | CI(dcache_write, DCACHE_ALLOW_WR); |
83 | ci->dcache_line_length = PVR_DCACHE_LINE_LEN(pvr) << 2; |
84 | CI(dcache_size, DCACHE_BYTE_SIZE); |
85 | CI(dcache_base, DCACHE_BASEADDR); |
86 | CI(dcache_high, DCACHE_HIGHADDR); |
87 | |
88 | temp = PVR_DCACHE_USE_WRITEBACK(pvr); |
89 | if (ci->dcache_wb != temp) |
90 | err_printk("DCACHE WB" ); |
91 | ci->dcache_wb = temp; |
92 | |
93 | CI(use_dopb, D_OPB); |
94 | CI(use_iopb, I_OPB); |
95 | CI(use_dlmb, D_LMB); |
96 | CI(use_ilmb, I_LMB); |
97 | CI(num_fsl, FSL_LINKS); |
98 | |
99 | CI(irq_edge, INTERRUPT_IS_EDGE); |
100 | CI(irq_positive, EDGE_IS_POSITIVE); |
101 | |
102 | CI(area_optimised, AREA_OPTIMISED); |
103 | |
104 | CI(hw_debug, DEBUG_ENABLED); |
105 | CI(num_pc_brk, NUMBER_OF_PC_BRK); |
106 | CI(num_rd_brk, NUMBER_OF_RD_ADDR_BRK); |
107 | CI(num_wr_brk, NUMBER_OF_WR_ADDR_BRK); |
108 | |
109 | CI(fpga_family_code, TARGET_FAMILY); |
110 | } |
111 | |