| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #include <linux/linkage.h> |
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| 3 | |
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| 4 | /* |
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| 5 | * Unsigned divide operation. |
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| 6 | * Input : Divisor in Reg r5 |
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| 7 | * Dividend in Reg r6 |
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| 8 | * Output: Result in Reg r3 |
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| 9 | */ |
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| 10 | |
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| 11 | .text |
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| 12 | .globl __udivsi3 |
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| 13 | .type __udivsi3, @function |
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| 14 | .ent __udivsi3 |
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| 15 | |
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| 16 | __udivsi3: |
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| 17 | |
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| 18 | .frame r1, 0, r15 |
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| 19 | |
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| 20 | addik r1, r1, -12 |
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| 21 | swi r29, r1, 0 |
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| 22 | swi r30, r1, 4 |
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| 23 | swi r31, r1, 8 |
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| 24 | |
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| 25 | beqi r6, div_by_zero /* div_by_zero /* division error */ |
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| 26 | beqid r5, result_is_zero /* result is zero */ |
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| 27 | addik r30, r0, 0 /* clear mod */ |
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| 28 | addik r29, r0, 32 /* initialize the loop count */ |
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| 29 | |
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| 30 | /* check if r6 and r5 are equal - if yes, return 1 */ |
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| 31 | rsub r18, r5, r6 |
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| 32 | beqid r18, return_here |
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| 33 | addik r3, r0, 1 |
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| 34 | |
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| 35 | /* check if (uns)r6 is greater than (uns)r5. in that case, just return 0 */ |
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| 36 | xor r18, r5, r6 |
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| 37 | bgeid r18, 16 |
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| 38 | add r3, r0, r0 /* we would anyways clear r3 */ |
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| 39 | blti r6, return_here /* r6[bit 31 = 1] hence is greater */ |
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| 40 | bri checkr6 |
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| 41 | rsub r18, r6, r5 /* microblazecmp */ |
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| 42 | blti r18, return_here |
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| 43 | |
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| 44 | /* if r6 [bit 31] is set, then return result as 1 */ |
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| 45 | checkr6: |
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| 46 | bgti r6, div0 |
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| 47 | brid return_here |
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| 48 | addik r3, r0, 1 |
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| 49 | |
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| 50 | /* first part try to find the first '1' in the r5 */ |
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| 51 | div0: |
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| 52 | blti r5, div2 |
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| 53 | div1: |
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| 54 | add r5, r5, r5 /* left shift logical r5 */ |
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| 55 | bgtid r5, div1 |
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| 56 | addik r29, r29, -1 |
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| 57 | div2: |
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| 58 | /* left shift logical r5 get the '1' into the carry */ |
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| 59 | add r5, r5, r5 |
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| 60 | addc r30, r30, r30 /* move that bit into the mod register */ |
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| 61 | rsub r31, r6, r30 /* try to subtract (r30 a r6) */ |
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| 62 | blti r31, mod_too_small |
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| 63 | /* move the r31 to mod since the result was positive */ |
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| 64 | or r30, r0, r31 |
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| 65 | addik r3, r3, 1 |
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| 66 | mod_too_small: |
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| 67 | addik r29, r29, -1 |
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| 68 | beqi r29, loop_end |
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| 69 | add r3, r3, r3 /* shift in the '1' into div */ |
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| 70 | bri div2 /* div2 */ |
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| 71 | loop_end: |
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| 72 | bri return_here |
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| 73 | div_by_zero: |
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| 74 | result_is_zero: |
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| 75 | or r3, r0, r0 /* set result to 0 */ |
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| 76 | return_here: |
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| 77 | /* restore values of csrs and that of r3 and the divisor and the dividend */ |
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| 78 | lwi r29, r1, 0 |
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| 79 | lwi r30, r1, 4 |
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| 80 | lwi r31, r1, 8 |
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| 81 | rtsd r15, 8 |
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| 82 | addik r1, r1, 12 |
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| 83 | |
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| 84 | .size __udivsi3, . - __udivsi3 |
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| 85 | .end __udivsi3 |
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| 86 | |
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