1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. |
5 | * |
6 | * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> |
7 | * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com> |
8 | */ |
9 | |
10 | #include <linux/init.h> |
11 | #include <linux/bitops.h> |
12 | #include <linux/memblock.h> |
13 | #include <linux/ioport.h> |
14 | #include <linux/kernel.h> |
15 | #include <linux/io.h> |
16 | #include <linux/of.h> |
17 | #include <linux/of_clk.h> |
18 | #include <linux/of_fdt.h> |
19 | #include <linux/libfdt.h> |
20 | #include <linux/smp.h> |
21 | #include <asm/addrspace.h> |
22 | #include <asm/bmips.h> |
23 | #include <asm/bootinfo.h> |
24 | #include <asm/cpu-type.h> |
25 | #include <asm/mipsregs.h> |
26 | #include <asm/prom.h> |
27 | #include <asm/smp-ops.h> |
28 | #include <asm/time.h> |
29 | #include <asm/traps.h> |
30 | #include <asm/fw/cfe/cfe_api.h> |
31 | |
32 | #define RELO_NORMAL_VEC BIT(18) |
33 | |
34 | #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) |
35 | #define BCM6328_TP1_DISABLED BIT(9) |
36 | |
37 | extern bool bmips_rac_flush_disable; |
38 | |
39 | static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000; |
40 | |
41 | struct bmips_quirk { |
42 | const char *compatible; |
43 | void (*quirk_fn)(void); |
44 | }; |
45 | |
46 | static void kbase_setup(void) |
47 | { |
48 | __raw_writel(val: kbase | RELO_NORMAL_VEC, |
49 | addr: BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1); |
50 | ebase = kbase; |
51 | } |
52 | |
53 | static void bcm3384_viper_quirks(void) |
54 | { |
55 | /* |
56 | * Some experimental CM boxes are set up to let CM own the Viper TP0 |
57 | * and let Linux own TP1. This requires moving the kernel |
58 | * load address to a non-conflicting region (e.g. via |
59 | * CONFIG_PHYSICAL_START) and supplying an alternate DTB. |
60 | * If we detect this condition, we need to move the MIPS exception |
61 | * vectors up to an area that we own. |
62 | * |
63 | * This is distinct from the OTHER special case mentioned in |
64 | * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our |
65 | * logical CPU#1). For the Viper TP1 case, SMP is off limits. |
66 | * |
67 | * Also note that many BMIPS435x CPUs do not have a |
68 | * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just |
69 | * write VMLINUX_LOAD_ADDRESS into that register on every SoC. |
70 | */ |
71 | board_ebase_setup = &kbase_setup; |
72 | bmips_smp_enabled = 0; |
73 | } |
74 | |
75 | static void bcm63xx_fixup_cpu1(void) |
76 | { |
77 | /* |
78 | * The bootloader has set up the CPU1 reset vector at |
79 | * 0xa000_0200. |
80 | * This conflicts with the special interrupt vector (IV). |
81 | * The bootloader has also set up CPU1 to respond to the wrong |
82 | * IPI interrupt. |
83 | * Here we will start up CPU1 in the background and ask it to |
84 | * reconfigure itself then go back to sleep. |
85 | */ |
86 | memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20); |
87 | __sync(); |
88 | set_c0_cause(C_SW0); |
89 | cpumask_set_cpu(cpu: 1, dstp: &bmips_booted_mask); |
90 | } |
91 | |
92 | static void bcm6328_quirks(void) |
93 | { |
94 | /* Check CPU1 status in OTP (it is usually disabled) */ |
95 | if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED) |
96 | bmips_smp_enabled = 0; |
97 | else |
98 | bcm63xx_fixup_cpu1(); |
99 | } |
100 | |
101 | static void bcm6358_quirks(void) |
102 | { |
103 | /* |
104 | * BCM3368/BCM6358 need special handling for their shared TLB, so |
105 | * disable SMP for now |
106 | */ |
107 | bmips_smp_enabled = 0; |
108 | |
109 | /* |
110 | * RAC flush causes kernel panics on BCM6358 when booting from TP1 |
111 | * because the bootloader is not initializing it properly. |
112 | */ |
113 | bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)); |
114 | } |
115 | |
116 | static void bcm6368_quirks(void) |
117 | { |
118 | bcm63xx_fixup_cpu1(); |
119 | } |
120 | |
121 | static const struct bmips_quirk bmips_quirk_list[] = { |
122 | { "brcm,bcm3368" , &bcm6358_quirks }, |
123 | { "brcm,bcm3384-viper" , &bcm3384_viper_quirks }, |
124 | { "brcm,bcm33843-viper" , &bcm3384_viper_quirks }, |
125 | { "brcm,bcm6328" , &bcm6328_quirks }, |
126 | { "brcm,bcm6358" , &bcm6358_quirks }, |
127 | { "brcm,bcm6362" , &bcm6368_quirks }, |
128 | { "brcm,bcm6368" , &bcm6368_quirks }, |
129 | { "brcm,bcm63168" , &bcm6368_quirks }, |
130 | { "brcm,bcm63268" , &bcm6368_quirks }, |
131 | { }, |
132 | }; |
133 | |
134 | static void __init bmips_init_cfe(void) |
135 | { |
136 | cfe_seal = fw_arg3; |
137 | |
138 | if (cfe_seal != CFE_EPTSEAL) |
139 | return; |
140 | |
141 | cfe_init(fw_arg0, fw_arg2); |
142 | } |
143 | |
144 | void __init prom_init(void) |
145 | { |
146 | bmips_init_cfe(); |
147 | bmips_cpu_setup(); |
148 | register_bmips_smp_ops(); |
149 | } |
150 | |
151 | const char *get_system_type(void) |
152 | { |
153 | return "Generic BMIPS kernel" ; |
154 | } |
155 | |
156 | void __init plat_time_init(void) |
157 | { |
158 | struct device_node *np; |
159 | u32 freq; |
160 | |
161 | np = of_find_node_by_name(NULL, name: "cpus" ); |
162 | if (!np) |
163 | panic(fmt: "missing 'cpus' DT node" ); |
164 | if (of_property_read_u32(np, propname: "mips-hpt-frequency" , out_value: &freq) < 0) |
165 | panic(fmt: "missing 'mips-hpt-frequency' property" ); |
166 | of_node_put(node: np); |
167 | |
168 | mips_hpt_frequency = freq; |
169 | } |
170 | |
171 | void __init plat_mem_setup(void) |
172 | { |
173 | void *dtb; |
174 | const struct bmips_quirk *q; |
175 | |
176 | set_io_port_base(0); |
177 | ioport_resource.start = 0; |
178 | ioport_resource.end = ~0; |
179 | |
180 | /* |
181 | * intended to somewhat resemble ARM; see |
182 | * Documentation/arch/arm/booting.rst |
183 | */ |
184 | if (fw_arg0 == 0 && fw_arg1 == 0xffffffff) |
185 | dtb = phys_to_virt(address: fw_arg2); |
186 | else |
187 | dtb = get_fdt(); |
188 | |
189 | if (!dtb) |
190 | cfe_die("no dtb found" ); |
191 | |
192 | __dt_setup_arch(dtb); |
193 | |
194 | for (q = bmips_quirk_list; q->quirk_fn; q++) { |
195 | if (of_flat_dt_is_compatible(node: of_get_flat_dt_root(), |
196 | name: q->compatible)) { |
197 | q->quirk_fn(); |
198 | } |
199 | } |
200 | } |
201 | |
202 | void __init device_tree_init(void) |
203 | { |
204 | struct device_node *np; |
205 | |
206 | unflatten_and_copy_device_tree(); |
207 | |
208 | /* Disable SMP boot unless both CPUs are listed in DT and !disabled */ |
209 | np = of_find_node_by_name(NULL, name: "cpus" ); |
210 | if (np && of_get_available_child_count(np) <= 1) |
211 | bmips_smp_enabled = 0; |
212 | of_node_put(node: np); |
213 | } |
214 | |
215 | static int __init plat_dev_init(void) |
216 | { |
217 | of_clk_init(NULL); |
218 | return 0; |
219 | } |
220 | |
221 | arch_initcall(plat_dev_init); |
222 | |