1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. |
5 | * |
6 | * Copyright (C) 2004-2017 Cavium, Inc. |
7 | * Copyright (C) 2008 Wind River Systems |
8 | */ |
9 | |
10 | #include <linux/etherdevice.h> |
11 | #include <linux/of.h> |
12 | #include <linux/of_platform.h> |
13 | #include <linux/of_fdt.h> |
14 | #include <linux/platform_device.h> |
15 | #include <linux/libfdt.h> |
16 | |
17 | #include <asm/octeon/octeon.h> |
18 | #include <asm/octeon/cvmx-helper-board.h> |
19 | |
20 | #ifdef CONFIG_USB |
21 | #include <linux/usb/ehci_def.h> |
22 | #include <linux/usb/ehci_pdriver.h> |
23 | #include <linux/usb/ohci_pdriver.h> |
24 | #include <asm/octeon/cvmx-uctlx-defs.h> |
25 | |
26 | #define CVMX_UAHCX_EHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000010ull)) |
27 | #define CVMX_UAHCX_OHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000408ull)) |
28 | |
29 | static DEFINE_MUTEX(octeon2_usb_clocks_mutex); |
30 | |
31 | static int octeon2_usb_clock_start_cnt; |
32 | |
33 | static int __init octeon2_usb_reset(void) |
34 | { |
35 | union cvmx_uctlx_clk_rst_ctl clk_rst_ctl; |
36 | u32 ucmd; |
37 | |
38 | if (!OCTEON_IS_OCTEON2()) |
39 | return 0; |
40 | |
41 | clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); |
42 | if (clk_rst_ctl.s.hrst) { |
43 | ucmd = cvmx_read64_uint32(CVMX_UAHCX_EHCI_USBCMD); |
44 | ucmd &= ~CMD_RUN; |
45 | cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd); |
46 | mdelay(2); |
47 | ucmd |= CMD_RESET; |
48 | cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd); |
49 | ucmd = cvmx_read64_uint32(CVMX_UAHCX_OHCI_USBCMD); |
50 | ucmd |= CMD_RUN; |
51 | cvmx_write64_uint32(CVMX_UAHCX_OHCI_USBCMD, ucmd); |
52 | } |
53 | |
54 | return 0; |
55 | } |
56 | arch_initcall(octeon2_usb_reset); |
57 | |
58 | static void octeon2_usb_clocks_start(struct device *dev) |
59 | { |
60 | u64 div; |
61 | union cvmx_uctlx_if_ena if_ena; |
62 | union cvmx_uctlx_clk_rst_ctl clk_rst_ctl; |
63 | union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status; |
64 | int i; |
65 | unsigned long io_clk_64_to_ns; |
66 | u32 clock_rate = 12000000; |
67 | bool is_crystal_clock = false; |
68 | |
69 | |
70 | mutex_lock(&octeon2_usb_clocks_mutex); |
71 | |
72 | octeon2_usb_clock_start_cnt++; |
73 | if (octeon2_usb_clock_start_cnt != 1) |
74 | goto exit; |
75 | |
76 | io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate(); |
77 | |
78 | if (dev->of_node) { |
79 | struct device_node *uctl_node; |
80 | const char *clock_type; |
81 | |
82 | uctl_node = of_get_parent(node: dev->of_node); |
83 | if (!uctl_node) { |
84 | dev_err(dev, "No UCTL device node\n" ); |
85 | goto exit; |
86 | } |
87 | i = of_property_read_u32(np: uctl_node, |
88 | propname: "refclk-frequency" , out_value: &clock_rate); |
89 | if (i) { |
90 | dev_err(dev, "No UCTL \"refclk-frequency\"\n" ); |
91 | of_node_put(node: uctl_node); |
92 | goto exit; |
93 | } |
94 | i = of_property_read_string(np: uctl_node, |
95 | propname: "refclk-type" , out_string: &clock_type); |
96 | of_node_put(node: uctl_node); |
97 | if (!i && strcmp("crystal" , clock_type) == 0) |
98 | is_crystal_clock = true; |
99 | } |
100 | |
101 | /* |
102 | * Step 1: Wait for voltages stable. That surely happened |
103 | * before starting the kernel. |
104 | * |
105 | * Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1 |
106 | */ |
107 | if_ena.u64 = 0; |
108 | if_ena.s.en = 1; |
109 | cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64); |
110 | |
111 | for (i = 0; i <= 1; i++) { |
112 | port_ctl_status.u64 = |
113 | cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0)); |
114 | /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */ |
115 | port_ctl_status.s.txvreftune = 15; |
116 | port_ctl_status.s.txrisetune = 1; |
117 | port_ctl_status.s.txpreemphasistune = 1; |
118 | cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0), |
119 | port_ctl_status.u64); |
120 | } |
121 | |
122 | /* Step 3: Configure the reference clock, PHY, and HCLK */ |
123 | clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); |
124 | |
125 | /* |
126 | * If the UCTL looks like it has already been started, skip |
127 | * the initialization, otherwise bus errors are obtained. |
128 | */ |
129 | if (clk_rst_ctl.s.hrst) |
130 | goto end_clock; |
131 | /* 3a */ |
132 | clk_rst_ctl.s.p_por = 1; |
133 | clk_rst_ctl.s.hrst = 0; |
134 | clk_rst_ctl.s.p_prst = 0; |
135 | clk_rst_ctl.s.h_clkdiv_rst = 0; |
136 | clk_rst_ctl.s.o_clkdiv_rst = 0; |
137 | clk_rst_ctl.s.h_clkdiv_en = 0; |
138 | clk_rst_ctl.s.o_clkdiv_en = 0; |
139 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
140 | |
141 | /* 3b */ |
142 | clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1; |
143 | switch (clock_rate) { |
144 | default: |
145 | pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n" , |
146 | clock_rate); |
147 | fallthrough; |
148 | case 12000000: |
149 | clk_rst_ctl.s.p_refclk_div = 0; |
150 | break; |
151 | case 24000000: |
152 | clk_rst_ctl.s.p_refclk_div = 1; |
153 | break; |
154 | case 48000000: |
155 | clk_rst_ctl.s.p_refclk_div = 2; |
156 | break; |
157 | } |
158 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
159 | |
160 | /* 3c */ |
161 | div = octeon_get_io_clock_rate() / 130000000ull; |
162 | |
163 | switch (div) { |
164 | case 0: |
165 | div = 1; |
166 | break; |
167 | case 1: |
168 | case 2: |
169 | case 3: |
170 | case 4: |
171 | break; |
172 | case 5: |
173 | div = 4; |
174 | break; |
175 | case 6: |
176 | case 7: |
177 | div = 6; |
178 | break; |
179 | case 8: |
180 | case 9: |
181 | case 10: |
182 | case 11: |
183 | div = 8; |
184 | break; |
185 | default: |
186 | div = 12; |
187 | break; |
188 | } |
189 | clk_rst_ctl.s.h_div = div; |
190 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
191 | /* Read it back, */ |
192 | clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0)); |
193 | clk_rst_ctl.s.h_clkdiv_en = 1; |
194 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
195 | /* 3d */ |
196 | clk_rst_ctl.s.h_clkdiv_rst = 1; |
197 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
198 | |
199 | /* 3e: delay 64 io clocks */ |
200 | ndelay(io_clk_64_to_ns); |
201 | |
202 | /* |
203 | * Step 4: Program the power-on reset field in the UCTL |
204 | * clock-reset-control register. |
205 | */ |
206 | clk_rst_ctl.s.p_por = 0; |
207 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
208 | |
209 | /* Step 5: Wait 3 ms for the PHY clock to start. */ |
210 | mdelay(3); |
211 | |
212 | /* Steps 6..9 for ATE only, are skipped. */ |
213 | |
214 | /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */ |
215 | /* 10a */ |
216 | clk_rst_ctl.s.o_clkdiv_rst = 1; |
217 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
218 | |
219 | /* 10b */ |
220 | clk_rst_ctl.s.o_clkdiv_en = 1; |
221 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
222 | |
223 | /* 10c */ |
224 | ndelay(io_clk_64_to_ns); |
225 | |
226 | /* |
227 | * Step 11: Program the PHY reset field: |
228 | * UCTL0_CLK_RST_CTL[P_PRST] = 1 |
229 | */ |
230 | clk_rst_ctl.s.p_prst = 1; |
231 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
232 | |
233 | /* Step 11b */ |
234 | udelay(1); |
235 | |
236 | /* Step 11c */ |
237 | clk_rst_ctl.s.p_prst = 0; |
238 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
239 | |
240 | /* Step 11d */ |
241 | mdelay(1); |
242 | |
243 | /* Step 11e */ |
244 | clk_rst_ctl.s.p_prst = 1; |
245 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
246 | |
247 | /* Step 12: Wait 1 uS. */ |
248 | udelay(1); |
249 | |
250 | /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */ |
251 | clk_rst_ctl.s.hrst = 1; |
252 | cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64); |
253 | |
254 | end_clock: |
255 | /* Set uSOF cycle period to 60,000 bits. */ |
256 | cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull); |
257 | |
258 | exit: |
259 | mutex_unlock(lock: &octeon2_usb_clocks_mutex); |
260 | } |
261 | |
262 | static void octeon2_usb_clocks_stop(void) |
263 | { |
264 | mutex_lock(&octeon2_usb_clocks_mutex); |
265 | octeon2_usb_clock_start_cnt--; |
266 | mutex_unlock(lock: &octeon2_usb_clocks_mutex); |
267 | } |
268 | |
269 | static int octeon_ehci_power_on(struct platform_device *pdev) |
270 | { |
271 | octeon2_usb_clocks_start(dev: &pdev->dev); |
272 | return 0; |
273 | } |
274 | |
275 | static void octeon_ehci_power_off(struct platform_device *pdev) |
276 | { |
277 | octeon2_usb_clocks_stop(); |
278 | } |
279 | |
280 | static struct usb_ehci_pdata octeon_ehci_pdata = { |
281 | /* Octeon EHCI matches CPU endianness. */ |
282 | #ifdef __BIG_ENDIAN |
283 | .big_endian_mmio = 1, |
284 | #endif |
285 | /* |
286 | * We can DMA from anywhere. But the descriptors must be in |
287 | * the lower 4GB. |
288 | */ |
289 | .dma_mask_64 = 0, |
290 | .power_on = octeon_ehci_power_on, |
291 | .power_off = octeon_ehci_power_off, |
292 | }; |
293 | |
294 | static void __init octeon_ehci_hw_start(struct device *dev) |
295 | { |
296 | union cvmx_uctlx_ehci_ctl ehci_ctl; |
297 | |
298 | octeon2_usb_clocks_start(dev); |
299 | |
300 | ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0)); |
301 | /* Use 64-bit addressing. */ |
302 | ehci_ctl.s.ehci_64b_addr_en = 1; |
303 | ehci_ctl.s.l2c_addr_msb = 0; |
304 | #ifdef __BIG_ENDIAN |
305 | ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ |
306 | ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ |
307 | #else |
308 | ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */ |
309 | ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */ |
310 | ehci_ctl.s.inv_reg_a2 = 1; |
311 | #endif |
312 | cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64); |
313 | |
314 | octeon2_usb_clocks_stop(); |
315 | } |
316 | |
317 | static int __init octeon_ehci_device_init(void) |
318 | { |
319 | struct platform_device *pd; |
320 | struct device_node *ehci_node; |
321 | int ret = 0; |
322 | |
323 | ehci_node = of_find_node_by_name(NULL, name: "ehci" ); |
324 | if (!ehci_node) |
325 | return 0; |
326 | |
327 | pd = of_find_device_by_node(np: ehci_node); |
328 | of_node_put(node: ehci_node); |
329 | if (!pd) |
330 | return 0; |
331 | |
332 | pd->dev.platform_data = &octeon_ehci_pdata; |
333 | octeon_ehci_hw_start(dev: &pd->dev); |
334 | put_device(dev: &pd->dev); |
335 | |
336 | return ret; |
337 | } |
338 | device_initcall(octeon_ehci_device_init); |
339 | |
340 | static int octeon_ohci_power_on(struct platform_device *pdev) |
341 | { |
342 | octeon2_usb_clocks_start(dev: &pdev->dev); |
343 | return 0; |
344 | } |
345 | |
346 | static void octeon_ohci_power_off(struct platform_device *pdev) |
347 | { |
348 | octeon2_usb_clocks_stop(); |
349 | } |
350 | |
351 | static struct usb_ohci_pdata octeon_ohci_pdata = { |
352 | /* Octeon OHCI matches CPU endianness. */ |
353 | #ifdef __BIG_ENDIAN |
354 | .big_endian_mmio = 1, |
355 | #endif |
356 | .power_on = octeon_ohci_power_on, |
357 | .power_off = octeon_ohci_power_off, |
358 | }; |
359 | |
360 | static void __init octeon_ohci_hw_start(struct device *dev) |
361 | { |
362 | union cvmx_uctlx_ohci_ctl ohci_ctl; |
363 | |
364 | octeon2_usb_clocks_start(dev); |
365 | |
366 | ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0)); |
367 | ohci_ctl.s.l2c_addr_msb = 0; |
368 | #ifdef __BIG_ENDIAN |
369 | ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ |
370 | ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ |
371 | #else |
372 | ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */ |
373 | ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */ |
374 | ohci_ctl.s.inv_reg_a2 = 1; |
375 | #endif |
376 | cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64); |
377 | |
378 | octeon2_usb_clocks_stop(); |
379 | } |
380 | |
381 | static int __init octeon_ohci_device_init(void) |
382 | { |
383 | struct platform_device *pd; |
384 | struct device_node *ohci_node; |
385 | int ret = 0; |
386 | |
387 | ohci_node = of_find_node_by_name(NULL, name: "ohci" ); |
388 | if (!ohci_node) |
389 | return 0; |
390 | |
391 | pd = of_find_device_by_node(np: ohci_node); |
392 | of_node_put(node: ohci_node); |
393 | if (!pd) |
394 | return 0; |
395 | |
396 | pd->dev.platform_data = &octeon_ohci_pdata; |
397 | octeon_ohci_hw_start(dev: &pd->dev); |
398 | put_device(dev: &pd->dev); |
399 | |
400 | return ret; |
401 | } |
402 | device_initcall(octeon_ohci_device_init); |
403 | |
404 | #endif /* CONFIG_USB */ |
405 | |
406 | /* Octeon Random Number Generator. */ |
407 | static int __init octeon_rng_device_init(void) |
408 | { |
409 | struct platform_device *pd; |
410 | int ret = 0; |
411 | |
412 | struct resource rng_resources[] = { |
413 | { |
414 | .flags = IORESOURCE_MEM, |
415 | .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS), |
416 | .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf |
417 | }, { |
418 | .flags = IORESOURCE_MEM, |
419 | .start = cvmx_build_io_address(8, 0), |
420 | .end = cvmx_build_io_address(8, 0) + 0x7 |
421 | } |
422 | }; |
423 | |
424 | pd = platform_device_alloc(name: "octeon_rng" , id: -1); |
425 | if (!pd) { |
426 | ret = -ENOMEM; |
427 | goto out; |
428 | } |
429 | |
430 | ret = platform_device_add_resources(pd, rng_resources, |
431 | ARRAY_SIZE(rng_resources)); |
432 | if (ret) |
433 | goto fail; |
434 | |
435 | ret = platform_device_add(pdev: pd); |
436 | if (ret) |
437 | goto fail; |
438 | |
439 | return ret; |
440 | fail: |
441 | platform_device_put(pdev: pd); |
442 | |
443 | out: |
444 | return ret; |
445 | } |
446 | device_initcall(octeon_rng_device_init); |
447 | |
448 | static const struct of_device_id octeon_ids[] __initconst = { |
449 | { .compatible = "simple-bus" , }, |
450 | { .compatible = "cavium,octeon-6335-uctl" , }, |
451 | { .compatible = "cavium,octeon-5750-usbn" , }, |
452 | { .compatible = "cavium,octeon-3860-bootbus" , }, |
453 | { .compatible = "cavium,mdio-mux" , }, |
454 | { .compatible = "gpio-leds" , }, |
455 | {}, |
456 | }; |
457 | |
458 | static bool __init octeon_has_88e1145(void) |
459 | { |
460 | return !OCTEON_IS_MODEL(OCTEON_CN52XX) && |
461 | !OCTEON_IS_MODEL(OCTEON_CN6XXX) && |
462 | !OCTEON_IS_MODEL(OCTEON_CN56XX); |
463 | } |
464 | |
465 | static bool __init octeon_has_fixed_link(int ipd_port) |
466 | { |
467 | switch (cvmx_sysinfo_get()->board_type) { |
468 | case CVMX_BOARD_TYPE_CN3005_EVB_HS5: |
469 | case CVMX_BOARD_TYPE_CN3010_EVB_HS5: |
470 | case CVMX_BOARD_TYPE_CN3020_EVB_HS5: |
471 | case CVMX_BOARD_TYPE_CUST_NB5: |
472 | case CVMX_BOARD_TYPE_EBH3100: |
473 | /* Port 1 on these boards is always gigabit. */ |
474 | return ipd_port == 1; |
475 | case CVMX_BOARD_TYPE_BBGW_REF: |
476 | /* Ports 0 and 1 connect to the switch. */ |
477 | return ipd_port == 0 || ipd_port == 1; |
478 | } |
479 | return false; |
480 | } |
481 | |
482 | static void __init octeon_fdt_set_phy(int eth, int phy_addr) |
483 | { |
484 | const __be32 *phy_handle; |
485 | const __be32 *alt_phy_handle; |
486 | const __be32 *reg; |
487 | u32 phandle; |
488 | int phy; |
489 | int alt_phy; |
490 | const char *p; |
491 | int current_len; |
492 | char new_name[20]; |
493 | |
494 | phy_handle = fdt_getprop(fdt: initial_boot_params, nodeoffset: eth, name: "phy-handle" , NULL); |
495 | if (!phy_handle) |
496 | return; |
497 | |
498 | phandle = be32_to_cpup(p: phy_handle); |
499 | phy = fdt_node_offset_by_phandle(fdt: initial_boot_params, phandle); |
500 | |
501 | alt_phy_handle = fdt_getprop(fdt: initial_boot_params, nodeoffset: eth, name: "cavium,alt-phy-handle" , NULL); |
502 | if (alt_phy_handle) { |
503 | u32 alt_phandle = be32_to_cpup(p: alt_phy_handle); |
504 | |
505 | alt_phy = fdt_node_offset_by_phandle(fdt: initial_boot_params, phandle: alt_phandle); |
506 | } else { |
507 | alt_phy = -1; |
508 | } |
509 | |
510 | if (phy_addr < 0 || phy < 0) { |
511 | /* Delete the PHY things */ |
512 | fdt_nop_property(fdt: initial_boot_params, nodeoffset: eth, name: "phy-handle" ); |
513 | /* This one may fail */ |
514 | fdt_nop_property(fdt: initial_boot_params, nodeoffset: eth, name: "cavium,alt-phy-handle" ); |
515 | if (phy >= 0) |
516 | fdt_nop_node(fdt: initial_boot_params, nodeoffset: phy); |
517 | if (alt_phy >= 0) |
518 | fdt_nop_node(fdt: initial_boot_params, nodeoffset: alt_phy); |
519 | return; |
520 | } |
521 | |
522 | if (phy_addr >= 256 && alt_phy > 0) { |
523 | const struct fdt_property *phy_prop; |
524 | struct fdt_property *alt_prop; |
525 | fdt32_t phy_handle_name; |
526 | |
527 | /* Use the alt phy node instead.*/ |
528 | phy_prop = fdt_get_property(fdt: initial_boot_params, nodeoffset: eth, name: "phy-handle" , NULL); |
529 | phy_handle_name = phy_prop->nameoff; |
530 | fdt_nop_node(fdt: initial_boot_params, nodeoffset: phy); |
531 | fdt_nop_property(fdt: initial_boot_params, nodeoffset: eth, name: "phy-handle" ); |
532 | alt_prop = fdt_get_property_w(fdt: initial_boot_params, nodeoffset: eth, name: "cavium,alt-phy-handle" , NULL); |
533 | alt_prop->nameoff = phy_handle_name; |
534 | phy = alt_phy; |
535 | } |
536 | |
537 | phy_addr &= 0xff; |
538 | |
539 | if (octeon_has_88e1145()) { |
540 | fdt_nop_property(fdt: initial_boot_params, nodeoffset: phy, name: "marvell,reg-init" ); |
541 | memset(new_name, 0, sizeof(new_name)); |
542 | strcpy(p: new_name, q: "marvell,88e1145" ); |
543 | p = fdt_getprop(fdt: initial_boot_params, nodeoffset: phy, name: "compatible" , |
544 | lenp: ¤t_len); |
545 | if (p && current_len >= strlen(new_name)) |
546 | fdt_setprop_inplace(fdt: initial_boot_params, nodeoffset: phy, |
547 | name: "compatible" , val: new_name, len: current_len); |
548 | } |
549 | |
550 | reg = fdt_getprop(fdt: initial_boot_params, nodeoffset: phy, name: "reg" , NULL); |
551 | if (phy_addr == be32_to_cpup(p: reg)) |
552 | return; |
553 | |
554 | fdt_setprop_inplace_cell(fdt: initial_boot_params, nodeoffset: phy, name: "reg" , val: phy_addr); |
555 | |
556 | snprintf(buf: new_name, size: sizeof(new_name), fmt: "ethernet-phy@%x" , phy_addr); |
557 | |
558 | p = fdt_get_name(fdt: initial_boot_params, nodeoffset: phy, lenp: ¤t_len); |
559 | if (p && current_len == strlen(new_name)) |
560 | fdt_set_name(fdt: initial_boot_params, nodeoffset: phy, name: new_name); |
561 | else |
562 | pr_err("Error: could not rename ethernet phy: <%s>" , p); |
563 | } |
564 | |
565 | static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac) |
566 | { |
567 | const u8 *old_mac; |
568 | int old_len; |
569 | u8 new_mac[6]; |
570 | u64 mac = *pmac; |
571 | int r; |
572 | |
573 | old_mac = fdt_getprop(fdt: initial_boot_params, nodeoffset: n, name: "local-mac-address" , |
574 | lenp: &old_len); |
575 | if (!old_mac || old_len != 6 || is_valid_ether_addr(addr: old_mac)) |
576 | return; |
577 | |
578 | new_mac[0] = (mac >> 40) & 0xff; |
579 | new_mac[1] = (mac >> 32) & 0xff; |
580 | new_mac[2] = (mac >> 24) & 0xff; |
581 | new_mac[3] = (mac >> 16) & 0xff; |
582 | new_mac[4] = (mac >> 8) & 0xff; |
583 | new_mac[5] = mac & 0xff; |
584 | |
585 | r = fdt_setprop_inplace(fdt: initial_boot_params, nodeoffset: n, name: "local-mac-address" , |
586 | val: new_mac, len: sizeof(new_mac)); |
587 | |
588 | if (r) { |
589 | pr_err("Setting \"local-mac-address\" failed %d" , r); |
590 | return; |
591 | } |
592 | *pmac = mac + 1; |
593 | } |
594 | |
595 | static void __init octeon_fdt_rm_ethernet(int node) |
596 | { |
597 | const __be32 *phy_handle; |
598 | |
599 | phy_handle = fdt_getprop(fdt: initial_boot_params, nodeoffset: node, name: "phy-handle" , NULL); |
600 | if (phy_handle) { |
601 | u32 ph = be32_to_cpup(p: phy_handle); |
602 | int p = fdt_node_offset_by_phandle(fdt: initial_boot_params, phandle: ph); |
603 | |
604 | if (p >= 0) |
605 | fdt_nop_node(fdt: initial_boot_params, nodeoffset: p); |
606 | } |
607 | fdt_nop_node(fdt: initial_boot_params, nodeoffset: node); |
608 | } |
609 | |
610 | static void __init _octeon_rx_tx_delay(int eth, int rx_delay, int tx_delay) |
611 | { |
612 | fdt_setprop_inplace_cell(fdt: initial_boot_params, nodeoffset: eth, name: "rx-delay" , |
613 | val: rx_delay); |
614 | fdt_setprop_inplace_cell(fdt: initial_boot_params, nodeoffset: eth, name: "tx-delay" , |
615 | val: tx_delay); |
616 | } |
617 | |
618 | static void __init octeon_rx_tx_delay(int eth, int iface, int port) |
619 | { |
620 | switch (cvmx_sysinfo_get()->board_type) { |
621 | case CVMX_BOARD_TYPE_CN3005_EVB_HS5: |
622 | if (iface == 0) { |
623 | if (port == 0) { |
624 | /* |
625 | * Boards with gigabit WAN ports need a |
626 | * different setting that is compatible with |
627 | * 100 Mbit settings |
628 | */ |
629 | _octeon_rx_tx_delay(eth, rx_delay: 0xc, tx_delay: 0x0c); |
630 | return; |
631 | } else if (port == 1) { |
632 | /* Different config for switch port. */ |
633 | _octeon_rx_tx_delay(eth, rx_delay: 0x0, tx_delay: 0x0); |
634 | return; |
635 | } |
636 | } |
637 | break; |
638 | case CVMX_BOARD_TYPE_UBNT_E100: |
639 | if (iface == 0 && port <= 2) { |
640 | _octeon_rx_tx_delay(eth, rx_delay: 0x0, tx_delay: 0x10); |
641 | return; |
642 | } |
643 | break; |
644 | } |
645 | fdt_nop_property(fdt: initial_boot_params, nodeoffset: eth, name: "rx-delay" ); |
646 | fdt_nop_property(fdt: initial_boot_params, nodeoffset: eth, name: "tx-delay" ); |
647 | } |
648 | |
649 | static void __init octeon_fdt_pip_port(int iface, int i, int p, int max) |
650 | { |
651 | char name_buffer[20]; |
652 | int eth; |
653 | int phy_addr; |
654 | int ipd_port; |
655 | int fixed_link; |
656 | |
657 | snprintf(buf: name_buffer, size: sizeof(name_buffer), fmt: "ethernet@%x" , p); |
658 | eth = fdt_subnode_offset(fdt: initial_boot_params, parentoffset: iface, name: name_buffer); |
659 | if (eth < 0) |
660 | return; |
661 | if (p > max) { |
662 | pr_debug("Deleting port %x:%x\n" , i, p); |
663 | octeon_fdt_rm_ethernet(node: eth); |
664 | return; |
665 | } |
666 | if (OCTEON_IS_MODEL(OCTEON_CN68XX)) |
667 | ipd_port = (0x100 * i) + (0x10 * p) + 0x800; |
668 | else |
669 | ipd_port = 16 * i + p; |
670 | |
671 | phy_addr = cvmx_helper_board_get_mii_address(ipd_port); |
672 | octeon_fdt_set_phy(eth, phy_addr); |
673 | |
674 | fixed_link = fdt_subnode_offset(fdt: initial_boot_params, parentoffset: eth, name: "fixed-link" ); |
675 | if (fixed_link < 0) |
676 | WARN_ON(octeon_has_fixed_link(ipd_port)); |
677 | else if (!octeon_has_fixed_link(ipd_port)) |
678 | fdt_nop_node(fdt: initial_boot_params, nodeoffset: fixed_link); |
679 | octeon_rx_tx_delay(eth, iface: i, port: p); |
680 | } |
681 | |
682 | static void __init octeon_fdt_pip_iface(int pip, int idx) |
683 | { |
684 | char name_buffer[20]; |
685 | int iface; |
686 | int p; |
687 | int count = 0; |
688 | |
689 | snprintf(buf: name_buffer, size: sizeof(name_buffer), fmt: "interface@%d" , idx); |
690 | iface = fdt_subnode_offset(fdt: initial_boot_params, parentoffset: pip, name: name_buffer); |
691 | if (iface < 0) |
692 | return; |
693 | |
694 | if (cvmx_helper_interface_enumerate(idx) == 0) |
695 | count = cvmx_helper_ports_on_interface(idx); |
696 | |
697 | for (p = 0; p < 16; p++) |
698 | octeon_fdt_pip_port(iface, i: idx, p, max: count - 1); |
699 | } |
700 | |
701 | void __init octeon_fill_mac_addresses(void) |
702 | { |
703 | const char *alias_prop; |
704 | char name_buffer[20]; |
705 | u64 mac_addr_base; |
706 | int aliases; |
707 | int pip; |
708 | int i; |
709 | |
710 | aliases = fdt_path_offset(fdt: initial_boot_params, path: "/aliases" ); |
711 | if (aliases < 0) |
712 | return; |
713 | |
714 | mac_addr_base = |
715 | ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 | |
716 | ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 | |
717 | ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 | |
718 | ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 | |
719 | ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 | |
720 | (octeon_bootinfo->mac_addr_base[5] & 0xffull); |
721 | |
722 | for (i = 0; i < 2; i++) { |
723 | int mgmt; |
724 | |
725 | snprintf(buf: name_buffer, size: sizeof(name_buffer), fmt: "mix%d" , i); |
726 | alias_prop = fdt_getprop(fdt: initial_boot_params, nodeoffset: aliases, |
727 | name: name_buffer, NULL); |
728 | if (!alias_prop) |
729 | continue; |
730 | mgmt = fdt_path_offset(fdt: initial_boot_params, path: alias_prop); |
731 | if (mgmt < 0) |
732 | continue; |
733 | octeon_fdt_set_mac_addr(n: mgmt, pmac: &mac_addr_base); |
734 | } |
735 | |
736 | alias_prop = fdt_getprop(fdt: initial_boot_params, nodeoffset: aliases, name: "pip" , NULL); |
737 | if (!alias_prop) |
738 | return; |
739 | |
740 | pip = fdt_path_offset(fdt: initial_boot_params, path: alias_prop); |
741 | if (pip < 0) |
742 | return; |
743 | |
744 | for (i = 0; i <= 4; i++) { |
745 | int iface; |
746 | int p; |
747 | |
748 | snprintf(buf: name_buffer, size: sizeof(name_buffer), fmt: "interface@%d" , i); |
749 | iface = fdt_subnode_offset(fdt: initial_boot_params, parentoffset: pip, |
750 | name: name_buffer); |
751 | if (iface < 0) |
752 | continue; |
753 | for (p = 0; p < 16; p++) { |
754 | int eth; |
755 | |
756 | snprintf(buf: name_buffer, size: sizeof(name_buffer), |
757 | fmt: "ethernet@%x" , p); |
758 | eth = fdt_subnode_offset(fdt: initial_boot_params, parentoffset: iface, |
759 | name: name_buffer); |
760 | if (eth < 0) |
761 | continue; |
762 | octeon_fdt_set_mac_addr(n: eth, pmac: &mac_addr_base); |
763 | } |
764 | } |
765 | } |
766 | |
767 | int __init octeon_prune_device_tree(void) |
768 | { |
769 | int i, max_port, uart_mask; |
770 | const char *pip_path; |
771 | const char *alias_prop; |
772 | char name_buffer[20]; |
773 | int aliases; |
774 | |
775 | if (fdt_check_header(fdt: initial_boot_params)) |
776 | panic(fmt: "Corrupt Device Tree." ); |
777 | |
778 | WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N, |
779 | "Built-in DTB booting is deprecated on %s. Please switch to use appended DTB." , |
780 | cvmx_board_type_to_string(octeon_bootinfo->board_type)); |
781 | |
782 | aliases = fdt_path_offset(fdt: initial_boot_params, path: "/aliases" ); |
783 | if (aliases < 0) { |
784 | pr_err("Error: No /aliases node in device tree." ); |
785 | return -EINVAL; |
786 | } |
787 | |
788 | if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) |
789 | max_port = 2; |
790 | else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)) |
791 | max_port = 1; |
792 | else |
793 | max_port = 0; |
794 | |
795 | if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E) |
796 | max_port = 0; |
797 | |
798 | for (i = 0; i < 2; i++) { |
799 | int mgmt; |
800 | |
801 | snprintf(buf: name_buffer, size: sizeof(name_buffer), |
802 | fmt: "mix%d" , i); |
803 | alias_prop = fdt_getprop(fdt: initial_boot_params, nodeoffset: aliases, |
804 | name: name_buffer, NULL); |
805 | if (alias_prop) { |
806 | mgmt = fdt_path_offset(fdt: initial_boot_params, path: alias_prop); |
807 | if (mgmt < 0) |
808 | continue; |
809 | if (i >= max_port) { |
810 | pr_debug("Deleting mix%d\n" , i); |
811 | octeon_fdt_rm_ethernet(node: mgmt); |
812 | fdt_nop_property(fdt: initial_boot_params, nodeoffset: aliases, |
813 | name: name_buffer); |
814 | } else { |
815 | int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i); |
816 | |
817 | octeon_fdt_set_phy(eth: mgmt, phy_addr); |
818 | } |
819 | } |
820 | } |
821 | |
822 | pip_path = fdt_getprop(fdt: initial_boot_params, nodeoffset: aliases, name: "pip" , NULL); |
823 | if (pip_path) { |
824 | int pip = fdt_path_offset(fdt: initial_boot_params, path: pip_path); |
825 | |
826 | if (pip >= 0) |
827 | for (i = 0; i <= 4; i++) |
828 | octeon_fdt_pip_iface(pip, idx: i); |
829 | } |
830 | |
831 | /* I2C */ |
832 | if (OCTEON_IS_MODEL(OCTEON_CN52XX) || |
833 | OCTEON_IS_MODEL(OCTEON_CN63XX) || |
834 | OCTEON_IS_MODEL(OCTEON_CN68XX) || |
835 | OCTEON_IS_MODEL(OCTEON_CN56XX)) |
836 | max_port = 2; |
837 | else |
838 | max_port = 1; |
839 | |
840 | for (i = 0; i < 2; i++) { |
841 | int i2c; |
842 | |
843 | snprintf(buf: name_buffer, size: sizeof(name_buffer), |
844 | fmt: "twsi%d" , i); |
845 | alias_prop = fdt_getprop(fdt: initial_boot_params, nodeoffset: aliases, |
846 | name: name_buffer, NULL); |
847 | |
848 | if (alias_prop) { |
849 | i2c = fdt_path_offset(fdt: initial_boot_params, path: alias_prop); |
850 | if (i2c < 0) |
851 | continue; |
852 | if (i >= max_port) { |
853 | pr_debug("Deleting twsi%d\n" , i); |
854 | fdt_nop_node(fdt: initial_boot_params, nodeoffset: i2c); |
855 | fdt_nop_property(fdt: initial_boot_params, nodeoffset: aliases, |
856 | name: name_buffer); |
857 | } |
858 | } |
859 | } |
860 | |
861 | /* SMI/MDIO */ |
862 | if (OCTEON_IS_MODEL(OCTEON_CN68XX)) |
863 | max_port = 4; |
864 | else if (OCTEON_IS_MODEL(OCTEON_CN52XX) || |
865 | OCTEON_IS_MODEL(OCTEON_CN63XX) || |
866 | OCTEON_IS_MODEL(OCTEON_CN56XX)) |
867 | max_port = 2; |
868 | else |
869 | max_port = 1; |
870 | |
871 | for (i = 0; i < 2; i++) { |
872 | int i2c; |
873 | |
874 | snprintf(buf: name_buffer, size: sizeof(name_buffer), |
875 | fmt: "smi%d" , i); |
876 | alias_prop = fdt_getprop(fdt: initial_boot_params, nodeoffset: aliases, |
877 | name: name_buffer, NULL); |
878 | if (alias_prop) { |
879 | i2c = fdt_path_offset(fdt: initial_boot_params, path: alias_prop); |
880 | if (i2c < 0) |
881 | continue; |
882 | if (i >= max_port) { |
883 | pr_debug("Deleting smi%d\n" , i); |
884 | fdt_nop_node(fdt: initial_boot_params, nodeoffset: i2c); |
885 | fdt_nop_property(fdt: initial_boot_params, nodeoffset: aliases, |
886 | name: name_buffer); |
887 | } |
888 | } |
889 | } |
890 | |
891 | /* Serial */ |
892 | uart_mask = 3; |
893 | |
894 | /* Right now CN52XX is the only chip with a third uart */ |
895 | if (OCTEON_IS_MODEL(OCTEON_CN52XX)) |
896 | uart_mask |= 4; /* uart2 */ |
897 | |
898 | for (i = 0; i < 3; i++) { |
899 | int uart; |
900 | |
901 | snprintf(buf: name_buffer, size: sizeof(name_buffer), |
902 | fmt: "uart%d" , i); |
903 | alias_prop = fdt_getprop(fdt: initial_boot_params, nodeoffset: aliases, |
904 | name: name_buffer, NULL); |
905 | |
906 | if (alias_prop) { |
907 | uart = fdt_path_offset(fdt: initial_boot_params, path: alias_prop); |
908 | if (uart_mask & (1 << i)) { |
909 | __be32 f; |
910 | |
911 | f = cpu_to_be32(octeon_get_io_clock_rate()); |
912 | fdt_setprop_inplace(fdt: initial_boot_params, |
913 | nodeoffset: uart, name: "clock-frequency" , |
914 | val: &f, len: sizeof(f)); |
915 | continue; |
916 | } |
917 | pr_debug("Deleting uart%d\n" , i); |
918 | fdt_nop_node(fdt: initial_boot_params, nodeoffset: uart); |
919 | fdt_nop_property(fdt: initial_boot_params, nodeoffset: aliases, |
920 | name: name_buffer); |
921 | } |
922 | } |
923 | |
924 | /* Compact Flash */ |
925 | alias_prop = fdt_getprop(fdt: initial_boot_params, nodeoffset: aliases, |
926 | name: "cf0" , NULL); |
927 | if (alias_prop) { |
928 | union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; |
929 | unsigned long base_ptr, region_base, region_size; |
930 | unsigned long region1_base = 0; |
931 | unsigned long region1_size = 0; |
932 | int cs, bootbus; |
933 | bool is_16bit = false; |
934 | bool is_true_ide = false; |
935 | __be32 new_reg[6]; |
936 | __be32 *ranges; |
937 | int len; |
938 | |
939 | int cf = fdt_path_offset(fdt: initial_boot_params, path: alias_prop); |
940 | |
941 | base_ptr = 0; |
942 | if (octeon_bootinfo->major_version == 1 |
943 | && octeon_bootinfo->minor_version >= 1) { |
944 | if (octeon_bootinfo->compact_flash_common_base_addr) |
945 | base_ptr = octeon_bootinfo->compact_flash_common_base_addr; |
946 | } else { |
947 | base_ptr = 0x1d000800; |
948 | } |
949 | |
950 | if (!base_ptr) |
951 | goto no_cf; |
952 | |
953 | /* Find CS0 region. */ |
954 | for (cs = 0; cs < 8; cs++) { |
955 | mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); |
956 | region_base = mio_boot_reg_cfg.s.base << 16; |
957 | region_size = (mio_boot_reg_cfg.s.size + 1) << 16; |
958 | if (mio_boot_reg_cfg.s.en && base_ptr >= region_base |
959 | && base_ptr < region_base + region_size) { |
960 | is_16bit = mio_boot_reg_cfg.s.width; |
961 | break; |
962 | } |
963 | } |
964 | if (cs >= 7) { |
965 | /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */ |
966 | goto no_cf; |
967 | } |
968 | |
969 | if (!(base_ptr & 0xfffful)) { |
970 | /* |
971 | * Boot loader signals availability of DMA (true_ide |
972 | * mode) by setting low order bits of base_ptr to |
973 | * zero. |
974 | */ |
975 | |
976 | /* Assume that CS1 immediately follows. */ |
977 | mio_boot_reg_cfg.u64 = |
978 | cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1)); |
979 | region1_base = mio_boot_reg_cfg.s.base << 16; |
980 | region1_size = (mio_boot_reg_cfg.s.size + 1) << 16; |
981 | if (!mio_boot_reg_cfg.s.en) |
982 | goto no_cf; |
983 | is_true_ide = true; |
984 | |
985 | } else { |
986 | fdt_nop_property(fdt: initial_boot_params, nodeoffset: cf, name: "cavium,true-ide" ); |
987 | fdt_nop_property(fdt: initial_boot_params, nodeoffset: cf, name: "cavium,dma-engine-handle" ); |
988 | if (!is_16bit) { |
989 | __be32 width = cpu_to_be32(8); |
990 | |
991 | fdt_setprop_inplace(fdt: initial_boot_params, nodeoffset: cf, |
992 | name: "cavium,bus-width" , val: &width, len: sizeof(width)); |
993 | } |
994 | } |
995 | new_reg[0] = cpu_to_be32(cs); |
996 | new_reg[1] = cpu_to_be32(0); |
997 | new_reg[2] = cpu_to_be32(0x10000); |
998 | new_reg[3] = cpu_to_be32(cs + 1); |
999 | new_reg[4] = cpu_to_be32(0); |
1000 | new_reg[5] = cpu_to_be32(0x10000); |
1001 | fdt_setprop_inplace(fdt: initial_boot_params, nodeoffset: cf, |
1002 | name: "reg" , val: new_reg, len: sizeof(new_reg)); |
1003 | |
1004 | bootbus = fdt_parent_offset(fdt: initial_boot_params, nodeoffset: cf); |
1005 | if (bootbus < 0) |
1006 | goto no_cf; |
1007 | ranges = fdt_getprop_w(fdt: initial_boot_params, nodeoffset: bootbus, name: "ranges" , lenp: &len); |
1008 | if (!ranges || len < (5 * 8 * sizeof(__be32))) |
1009 | goto no_cf; |
1010 | |
1011 | ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); |
1012 | ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); |
1013 | ranges[(cs * 5) + 4] = cpu_to_be32(region_size); |
1014 | if (is_true_ide) { |
1015 | cs++; |
1016 | ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32); |
1017 | ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff); |
1018 | ranges[(cs * 5) + 4] = cpu_to_be32(region1_size); |
1019 | } |
1020 | goto end_cf; |
1021 | no_cf: |
1022 | fdt_nop_node(fdt: initial_boot_params, nodeoffset: cf); |
1023 | |
1024 | end_cf: |
1025 | ; |
1026 | } |
1027 | |
1028 | /* 8 char LED */ |
1029 | alias_prop = fdt_getprop(fdt: initial_boot_params, nodeoffset: aliases, |
1030 | name: "led0" , NULL); |
1031 | if (alias_prop) { |
1032 | union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; |
1033 | unsigned long base_ptr, region_base, region_size; |
1034 | int cs, bootbus; |
1035 | __be32 new_reg[6]; |
1036 | __be32 *ranges; |
1037 | int len; |
1038 | int led = fdt_path_offset(fdt: initial_boot_params, path: alias_prop); |
1039 | |
1040 | base_ptr = octeon_bootinfo->led_display_base_addr; |
1041 | if (base_ptr == 0) |
1042 | goto no_led; |
1043 | /* Find CS0 region. */ |
1044 | for (cs = 0; cs < 8; cs++) { |
1045 | mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); |
1046 | region_base = mio_boot_reg_cfg.s.base << 16; |
1047 | region_size = (mio_boot_reg_cfg.s.size + 1) << 16; |
1048 | if (mio_boot_reg_cfg.s.en && base_ptr >= region_base |
1049 | && base_ptr < region_base + region_size) |
1050 | break; |
1051 | } |
1052 | |
1053 | if (cs > 7) |
1054 | goto no_led; |
1055 | |
1056 | new_reg[0] = cpu_to_be32(cs); |
1057 | new_reg[1] = cpu_to_be32(0x20); |
1058 | new_reg[2] = cpu_to_be32(0x20); |
1059 | new_reg[3] = cpu_to_be32(cs); |
1060 | new_reg[4] = cpu_to_be32(0); |
1061 | new_reg[5] = cpu_to_be32(0x20); |
1062 | fdt_setprop_inplace(fdt: initial_boot_params, nodeoffset: led, |
1063 | name: "reg" , val: new_reg, len: sizeof(new_reg)); |
1064 | |
1065 | bootbus = fdt_parent_offset(fdt: initial_boot_params, nodeoffset: led); |
1066 | if (bootbus < 0) |
1067 | goto no_led; |
1068 | ranges = fdt_getprop_w(fdt: initial_boot_params, nodeoffset: bootbus, name: "ranges" , lenp: &len); |
1069 | if (!ranges || len < (5 * 8 * sizeof(__be32))) |
1070 | goto no_led; |
1071 | |
1072 | ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); |
1073 | ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); |
1074 | ranges[(cs * 5) + 4] = cpu_to_be32(region_size); |
1075 | goto end_led; |
1076 | |
1077 | no_led: |
1078 | fdt_nop_node(fdt: initial_boot_params, nodeoffset: led); |
1079 | end_led: |
1080 | ; |
1081 | } |
1082 | |
1083 | #ifdef CONFIG_USB |
1084 | /* OHCI/UHCI USB */ |
1085 | alias_prop = fdt_getprop(fdt: initial_boot_params, nodeoffset: aliases, |
1086 | name: "uctl" , NULL); |
1087 | if (alias_prop) { |
1088 | int uctl = fdt_path_offset(fdt: initial_boot_params, path: alias_prop); |
1089 | |
1090 | if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) || |
1091 | octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) { |
1092 | pr_debug("Deleting uctl\n" ); |
1093 | fdt_nop_node(fdt: initial_boot_params, nodeoffset: uctl); |
1094 | fdt_nop_property(fdt: initial_boot_params, nodeoffset: aliases, name: "uctl" ); |
1095 | } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E || |
1096 | octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) { |
1097 | /* Missing "refclk-type" defaults to crystal. */ |
1098 | fdt_nop_property(fdt: initial_boot_params, nodeoffset: uctl, name: "refclk-type" ); |
1099 | } |
1100 | } |
1101 | |
1102 | /* DWC2 USB */ |
1103 | alias_prop = fdt_getprop(fdt: initial_boot_params, nodeoffset: aliases, |
1104 | name: "usbn" , NULL); |
1105 | if (alias_prop) { |
1106 | int usbn = fdt_path_offset(fdt: initial_boot_params, path: alias_prop); |
1107 | |
1108 | if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 || |
1109 | !octeon_has_feature(OCTEON_FEATURE_USB))) { |
1110 | pr_debug("Deleting usbn\n" ); |
1111 | fdt_nop_node(fdt: initial_boot_params, nodeoffset: usbn); |
1112 | fdt_nop_property(fdt: initial_boot_params, nodeoffset: aliases, name: "usbn" ); |
1113 | } else { |
1114 | __be32 new_f[1]; |
1115 | enum cvmx_helper_board_usb_clock_types c; |
1116 | |
1117 | c = __cvmx_helper_board_usb_get_clock_type(); |
1118 | switch (c) { |
1119 | case USB_CLOCK_TYPE_REF_48: |
1120 | new_f[0] = cpu_to_be32(48000000); |
1121 | fdt_setprop_inplace(fdt: initial_boot_params, nodeoffset: usbn, |
1122 | name: "refclk-frequency" , val: new_f, len: sizeof(new_f)); |
1123 | fallthrough; |
1124 | case USB_CLOCK_TYPE_REF_12: |
1125 | /* Missing "refclk-type" defaults to external. */ |
1126 | fdt_nop_property(fdt: initial_boot_params, nodeoffset: usbn, name: "refclk-type" ); |
1127 | break; |
1128 | default: |
1129 | break; |
1130 | } |
1131 | } |
1132 | } |
1133 | #endif |
1134 | |
1135 | return 0; |
1136 | } |
1137 | |
1138 | static int __init octeon_publish_devices(void) |
1139 | { |
1140 | return of_platform_populate(NULL, matches: octeon_ids, NULL, NULL); |
1141 | } |
1142 | arch_initcall(octeon_publish_devices); |
1143 | |