| 1 | /* |
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| 2 | * This file is subject to the terms and conditions of the GNU General Public |
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| 3 | * License. See the file "COPYING" in the main directory of this archive |
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| 4 | * for more details. |
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| 5 | * |
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| 6 | * FPU context handling code for KVM. |
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| 7 | * |
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| 8 | * Copyright (C) 2015 Imagination Technologies Ltd. |
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| 9 | */ |
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| 10 | |
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| 11 | #include <asm/asm.h> |
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| 12 | #include <asm/asm-offsets.h> |
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| 13 | #include <asm/fpregdef.h> |
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| 14 | #include <asm/mipsregs.h> |
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| 15 | #include <asm/regdef.h> |
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| 16 | |
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| 17 | /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */ |
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| 18 | #undef fp |
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| 19 | |
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| 20 | .set noreorder |
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| 21 | .set noat |
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| 22 | |
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| 23 | LEAF(__kvm_save_fpu) |
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| 24 | .set push |
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| 25 | .set hardfloat |
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| 26 | .set fp=64 |
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| 27 | mfc0 t0, CP0_STATUS |
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| 28 | sll t0, t0, 5 # is Status.FR set? |
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| 29 | bgez t0, 1f # no: skip odd doubles |
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| 30 | nop |
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| 31 | sdc1 $f1, VCPU_FPR1(a0) |
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| 32 | sdc1 $f3, VCPU_FPR3(a0) |
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| 33 | sdc1 $f5, VCPU_FPR5(a0) |
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| 34 | sdc1 $f7, VCPU_FPR7(a0) |
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| 35 | sdc1 $f9, VCPU_FPR9(a0) |
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| 36 | sdc1 $f11, VCPU_FPR11(a0) |
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| 37 | sdc1 $f13, VCPU_FPR13(a0) |
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| 38 | sdc1 $f15, VCPU_FPR15(a0) |
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| 39 | sdc1 $f17, VCPU_FPR17(a0) |
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| 40 | sdc1 $f19, VCPU_FPR19(a0) |
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| 41 | sdc1 $f21, VCPU_FPR21(a0) |
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| 42 | sdc1 $f23, VCPU_FPR23(a0) |
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| 43 | sdc1 $f25, VCPU_FPR25(a0) |
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| 44 | sdc1 $f27, VCPU_FPR27(a0) |
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| 45 | sdc1 $f29, VCPU_FPR29(a0) |
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| 46 | sdc1 $f31, VCPU_FPR31(a0) |
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| 47 | 1: sdc1 $f0, VCPU_FPR0(a0) |
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| 48 | sdc1 $f2, VCPU_FPR2(a0) |
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| 49 | sdc1 $f4, VCPU_FPR4(a0) |
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| 50 | sdc1 $f6, VCPU_FPR6(a0) |
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| 51 | sdc1 $f8, VCPU_FPR8(a0) |
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| 52 | sdc1 $f10, VCPU_FPR10(a0) |
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| 53 | sdc1 $f12, VCPU_FPR12(a0) |
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| 54 | sdc1 $f14, VCPU_FPR14(a0) |
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| 55 | sdc1 $f16, VCPU_FPR16(a0) |
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| 56 | sdc1 $f18, VCPU_FPR18(a0) |
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| 57 | sdc1 $f20, VCPU_FPR20(a0) |
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| 58 | sdc1 $f22, VCPU_FPR22(a0) |
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| 59 | sdc1 $f24, VCPU_FPR24(a0) |
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| 60 | sdc1 $f26, VCPU_FPR26(a0) |
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| 61 | sdc1 $f28, VCPU_FPR28(a0) |
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| 62 | jr ra |
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| 63 | sdc1 $f30, VCPU_FPR30(a0) |
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| 64 | .set pop |
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| 65 | END(__kvm_save_fpu) |
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| 66 | |
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| 67 | LEAF(__kvm_restore_fpu) |
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| 68 | .set push |
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| 69 | .set hardfloat |
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| 70 | .set fp=64 |
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| 71 | mfc0 t0, CP0_STATUS |
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| 72 | sll t0, t0, 5 # is Status.FR set? |
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| 73 | bgez t0, 1f # no: skip odd doubles |
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| 74 | nop |
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| 75 | ldc1 $f1, VCPU_FPR1(a0) |
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| 76 | ldc1 $f3, VCPU_FPR3(a0) |
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| 77 | ldc1 $f5, VCPU_FPR5(a0) |
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| 78 | ldc1 $f7, VCPU_FPR7(a0) |
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| 79 | ldc1 $f9, VCPU_FPR9(a0) |
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| 80 | ldc1 $f11, VCPU_FPR11(a0) |
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| 81 | ldc1 $f13, VCPU_FPR13(a0) |
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| 82 | ldc1 $f15, VCPU_FPR15(a0) |
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| 83 | ldc1 $f17, VCPU_FPR17(a0) |
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| 84 | ldc1 $f19, VCPU_FPR19(a0) |
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| 85 | ldc1 $f21, VCPU_FPR21(a0) |
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| 86 | ldc1 $f23, VCPU_FPR23(a0) |
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| 87 | ldc1 $f25, VCPU_FPR25(a0) |
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| 88 | ldc1 $f27, VCPU_FPR27(a0) |
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| 89 | ldc1 $f29, VCPU_FPR29(a0) |
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| 90 | ldc1 $f31, VCPU_FPR31(a0) |
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| 91 | 1: ldc1 $f0, VCPU_FPR0(a0) |
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| 92 | ldc1 $f2, VCPU_FPR2(a0) |
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| 93 | ldc1 $f4, VCPU_FPR4(a0) |
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| 94 | ldc1 $f6, VCPU_FPR6(a0) |
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| 95 | ldc1 $f8, VCPU_FPR8(a0) |
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| 96 | ldc1 $f10, VCPU_FPR10(a0) |
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| 97 | ldc1 $f12, VCPU_FPR12(a0) |
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| 98 | ldc1 $f14, VCPU_FPR14(a0) |
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| 99 | ldc1 $f16, VCPU_FPR16(a0) |
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| 100 | ldc1 $f18, VCPU_FPR18(a0) |
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| 101 | ldc1 $f20, VCPU_FPR20(a0) |
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| 102 | ldc1 $f22, VCPU_FPR22(a0) |
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| 103 | ldc1 $f24, VCPU_FPR24(a0) |
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| 104 | ldc1 $f26, VCPU_FPR26(a0) |
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| 105 | ldc1 $f28, VCPU_FPR28(a0) |
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| 106 | jr ra |
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| 107 | ldc1 $f30, VCPU_FPR30(a0) |
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| 108 | .set pop |
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| 109 | END(__kvm_restore_fpu) |
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| 110 | |
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| 111 | LEAF(__kvm_restore_fcsr) |
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| 112 | .set push |
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| 113 | .set hardfloat |
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| 114 | lw t0, VCPU_FCR31(a0) |
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| 115 | /* |
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| 116 | * The ctc1 must stay at this offset in __kvm_restore_fcsr. |
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| 117 | * See kvm_mips_csr_die_notify() which handles t0 containing a value |
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| 118 | * which triggers an FP Exception, which must be stepped over and |
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| 119 | * ignored since the set cause bits must remain there for the guest. |
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| 120 | */ |
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| 121 | ctc1 t0, fcr31 |
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| 122 | jr ra |
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| 123 | nop |
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| 124 | .set pop |
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| 125 | END(__kvm_restore_fcsr) |
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| 126 | |
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