1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. |
5 | * |
6 | * A small micro-assembler. It is intentionally kept simple, does only |
7 | * support a subset of instructions, and does not try to hide pipeline |
8 | * effects like branch delay slots. |
9 | * |
10 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
11 | * Copyright (C) 2005, 2007 Maciej W. Rozycki |
12 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
13 | * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. |
14 | */ |
15 | |
16 | enum fields { |
17 | RS = 0x001, |
18 | RT = 0x002, |
19 | RD = 0x004, |
20 | RE = 0x008, |
21 | SIMM = 0x010, |
22 | UIMM = 0x020, |
23 | BIMM = 0x040, |
24 | JIMM = 0x080, |
25 | FUNC = 0x100, |
26 | SET = 0x200, |
27 | SCIMM = 0x400, |
28 | SIMM9 = 0x800, |
29 | }; |
30 | |
31 | #define OP_MASK 0x3f |
32 | #define OP_SH 26 |
33 | #define RD_MASK 0x1f |
34 | #define RD_SH 11 |
35 | #define RE_MASK 0x1f |
36 | #define RE_SH 6 |
37 | #define IMM_MASK 0xffff |
38 | #define IMM_SH 0 |
39 | #define JIMM_MASK 0x3ffffff |
40 | #define JIMM_SH 0 |
41 | #define FUNC_MASK 0x3f |
42 | #define FUNC_SH 0 |
43 | #define SET_MASK 0x7 |
44 | #define SET_SH 0 |
45 | #define SIMM9_SH 7 |
46 | #define SIMM9_MASK 0x1ff |
47 | |
48 | enum opcode { |
49 | insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1, |
50 | insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bgtz, insn_blez, |
51 | insn_bltz, insn_bltzl, insn_bne, insn_break, insn_cache, insn_cfc1, |
52 | insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddivu, |
53 | insn_ddivu_r6, insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu, |
54 | insn_divu_r6, insn_dmfc0, insn_dmodu, insn_dmtc0, insn_dmultu, |
55 | insn_dmulu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd, insn_dsll, |
56 | insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav, insn_dsrl, |
57 | insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext, insn_ins, |
58 | insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu, insn_ld, |
59 | insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld, |
60 | insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, |
61 | insn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0, |
62 | insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_muhu, insn_nor, |
63 | insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc, |
64 | insn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll, |
65 | insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, |
66 | insn_srav, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, |
67 | insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, |
68 | insn_wsbh, insn_xor, insn_xori, insn_yield, |
69 | insn_invalid /* insn_invalid must be last */ |
70 | }; |
71 | |
72 | struct insn { |
73 | u32 match; |
74 | enum fields fields; |
75 | }; |
76 | |
77 | static inline u32 build_rs(u32 arg) |
78 | { |
79 | WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n" ); |
80 | |
81 | return (arg & RS_MASK) << RS_SH; |
82 | } |
83 | |
84 | static inline u32 build_rt(u32 arg) |
85 | { |
86 | WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n" ); |
87 | |
88 | return (arg & RT_MASK) << RT_SH; |
89 | } |
90 | |
91 | static inline u32 build_rd(u32 arg) |
92 | { |
93 | WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n" ); |
94 | |
95 | return (arg & RD_MASK) << RD_SH; |
96 | } |
97 | |
98 | static inline u32 build_re(u32 arg) |
99 | { |
100 | WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n" ); |
101 | |
102 | return (arg & RE_MASK) << RE_SH; |
103 | } |
104 | |
105 | static inline u32 build_simm(s32 arg) |
106 | { |
107 | WARN(arg > 0x7fff || arg < -0x8000, |
108 | KERN_WARNING "Micro-assembler field overflow\n" ); |
109 | |
110 | return arg & 0xffff; |
111 | } |
112 | |
113 | static inline u32 build_uimm(u32 arg) |
114 | { |
115 | WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n" ); |
116 | |
117 | return arg & IMM_MASK; |
118 | } |
119 | |
120 | static inline u32 build_scimm(u32 arg) |
121 | { |
122 | WARN(arg & ~SCIMM_MASK, |
123 | KERN_WARNING "Micro-assembler field overflow\n" ); |
124 | |
125 | return (arg & SCIMM_MASK) << SCIMM_SH; |
126 | } |
127 | |
128 | static inline u32 build_scimm9(s32 arg) |
129 | { |
130 | WARN((arg > 0xff || arg < -0x100), |
131 | KERN_WARNING "Micro-assembler field overflow\n" ); |
132 | |
133 | return (arg & SIMM9_MASK) << SIMM9_SH; |
134 | } |
135 | |
136 | static inline u32 build_func(u32 arg) |
137 | { |
138 | WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n" ); |
139 | |
140 | return arg & FUNC_MASK; |
141 | } |
142 | |
143 | static inline u32 build_set(u32 arg) |
144 | { |
145 | WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n" ); |
146 | |
147 | return arg & SET_MASK; |
148 | } |
149 | |
150 | static void build_insn(u32 **buf, enum opcode opc, ...); |
151 | |
152 | #define I_u1u2u3(op) \ |
153 | Ip_u1u2u3(op) \ |
154 | { \ |
155 | build_insn(buf, insn##op, a, b, c); \ |
156 | } \ |
157 | UASM_EXPORT_SYMBOL(uasm_i##op); |
158 | |
159 | #define I_s3s1s2(op) \ |
160 | Ip_s3s1s2(op) \ |
161 | { \ |
162 | build_insn(buf, insn##op, b, c, a); \ |
163 | } \ |
164 | UASM_EXPORT_SYMBOL(uasm_i##op); |
165 | |
166 | #define I_u2u1u3(op) \ |
167 | Ip_u2u1u3(op) \ |
168 | { \ |
169 | build_insn(buf, insn##op, b, a, c); \ |
170 | } \ |
171 | UASM_EXPORT_SYMBOL(uasm_i##op); |
172 | |
173 | #define I_u3u2u1(op) \ |
174 | Ip_u3u2u1(op) \ |
175 | { \ |
176 | build_insn(buf, insn##op, c, b, a); \ |
177 | } \ |
178 | UASM_EXPORT_SYMBOL(uasm_i##op); |
179 | |
180 | #define I_u3u1u2(op) \ |
181 | Ip_u3u1u2(op) \ |
182 | { \ |
183 | build_insn(buf, insn##op, b, c, a); \ |
184 | } \ |
185 | UASM_EXPORT_SYMBOL(uasm_i##op); |
186 | |
187 | #define I_u1u2s3(op) \ |
188 | Ip_u1u2s3(op) \ |
189 | { \ |
190 | build_insn(buf, insn##op, a, b, c); \ |
191 | } \ |
192 | UASM_EXPORT_SYMBOL(uasm_i##op); |
193 | |
194 | #define I_u2s3u1(op) \ |
195 | Ip_u2s3u1(op) \ |
196 | { \ |
197 | build_insn(buf, insn##op, c, a, b); \ |
198 | } \ |
199 | UASM_EXPORT_SYMBOL(uasm_i##op); |
200 | |
201 | #define I_u2u1s3(op) \ |
202 | Ip_u2u1s3(op) \ |
203 | { \ |
204 | build_insn(buf, insn##op, b, a, c); \ |
205 | } \ |
206 | UASM_EXPORT_SYMBOL(uasm_i##op); |
207 | |
208 | #define I_u2u1msbu3(op) \ |
209 | Ip_u2u1msbu3(op) \ |
210 | { \ |
211 | build_insn(buf, insn##op, b, a, c+d-1, c); \ |
212 | } \ |
213 | UASM_EXPORT_SYMBOL(uasm_i##op); |
214 | |
215 | #define I_u2u1msb32u3(op) \ |
216 | Ip_u2u1msbu3(op) \ |
217 | { \ |
218 | build_insn(buf, insn##op, b, a, c+d-33, c); \ |
219 | } \ |
220 | UASM_EXPORT_SYMBOL(uasm_i##op); |
221 | |
222 | #define I_u2u1msb32msb3(op) \ |
223 | Ip_u2u1msbu3(op) \ |
224 | { \ |
225 | build_insn(buf, insn##op, b, a, c+d-33, c-32); \ |
226 | } \ |
227 | UASM_EXPORT_SYMBOL(uasm_i##op); |
228 | |
229 | #define I_u2u1msbdu3(op) \ |
230 | Ip_u2u1msbu3(op) \ |
231 | { \ |
232 | build_insn(buf, insn##op, b, a, d-1, c); \ |
233 | } \ |
234 | UASM_EXPORT_SYMBOL(uasm_i##op); |
235 | |
236 | #define I_u1u2(op) \ |
237 | Ip_u1u2(op) \ |
238 | { \ |
239 | build_insn(buf, insn##op, a, b); \ |
240 | } \ |
241 | UASM_EXPORT_SYMBOL(uasm_i##op); |
242 | |
243 | #define I_u2u1(op) \ |
244 | Ip_u1u2(op) \ |
245 | { \ |
246 | build_insn(buf, insn##op, b, a); \ |
247 | } \ |
248 | UASM_EXPORT_SYMBOL(uasm_i##op); |
249 | |
250 | #define I_u1s2(op) \ |
251 | Ip_u1s2(op) \ |
252 | { \ |
253 | build_insn(buf, insn##op, a, b); \ |
254 | } \ |
255 | UASM_EXPORT_SYMBOL(uasm_i##op); |
256 | |
257 | #define I_u1(op) \ |
258 | Ip_u1(op) \ |
259 | { \ |
260 | build_insn(buf, insn##op, a); \ |
261 | } \ |
262 | UASM_EXPORT_SYMBOL(uasm_i##op); |
263 | |
264 | #define I_0(op) \ |
265 | Ip_0(op) \ |
266 | { \ |
267 | build_insn(buf, insn##op); \ |
268 | } \ |
269 | UASM_EXPORT_SYMBOL(uasm_i##op); |
270 | |
271 | I_u2u1s3(_addiu) |
272 | I_u3u1u2(_addu) |
273 | I_u2u1u3(_andi) |
274 | I_u3u1u2(_and) |
275 | I_u1u2s3(_beq) |
276 | I_u1u2s3(_beql) |
277 | I_u1s2(_bgez) |
278 | I_u1s2(_bgezl) |
279 | I_u1s2(_bgtz) |
280 | I_u1s2(_blez) |
281 | I_u1s2(_bltz) |
282 | I_u1s2(_bltzl) |
283 | I_u1u2s3(_bne) |
284 | I_u1(_break) |
285 | I_u2s3u1(_cache) |
286 | I_u1u2(_cfc1) |
287 | I_u2u1(_cfcmsa) |
288 | I_u1u2(_ctc1) |
289 | I_u2u1(_ctcmsa) |
290 | I_u1u2(_ddivu) |
291 | I_u3u1u2(_ddivu_r6) |
292 | I_u1u2u3(_dmfc0) |
293 | I_u3u1u2(_dmodu) |
294 | I_u1u2u3(_dmtc0) |
295 | I_u1u2(_dmultu) |
296 | I_u3u1u2(_dmulu) |
297 | I_u2u1s3(_daddiu) |
298 | I_u3u1u2(_daddu) |
299 | I_u1(_di); |
300 | I_u1u2(_divu) |
301 | I_u3u1u2(_divu_r6) |
302 | I_u2u1(_dsbh); |
303 | I_u2u1(_dshd); |
304 | I_u2u1u3(_dsll) |
305 | I_u2u1u3(_dsll32) |
306 | I_u3u2u1(_dsllv) |
307 | I_u2u1u3(_dsra) |
308 | I_u2u1u3(_dsra32) |
309 | I_u3u2u1(_dsrav) |
310 | I_u2u1u3(_dsrl) |
311 | I_u2u1u3(_dsrl32) |
312 | I_u3u2u1(_dsrlv) |
313 | I_u2u1u3(_drotr) |
314 | I_u2u1u3(_drotr32) |
315 | I_u3u1u2(_dsubu) |
316 | I_0(_eret) |
317 | I_u2u1msbdu3(_ext) |
318 | I_u2u1msbu3(_ins) |
319 | I_u1(_j) |
320 | I_u1(_jal) |
321 | I_u2u1(_jalr) |
322 | I_u1(_jr) |
323 | I_u2s3u1(_lb) |
324 | I_u2s3u1(_lbu) |
325 | I_u2s3u1(_ld) |
326 | I_u2s3u1(_lh) |
327 | I_u2s3u1(_lhu) |
328 | I_u2s3u1(_ll) |
329 | I_u2s3u1(_lld) |
330 | I_u1s2(_lui) |
331 | I_u2s3u1(_lw) |
332 | I_u2s3u1(_lwu) |
333 | I_u1u2u3(_mfc0) |
334 | I_u1u2u3(_mfhc0) |
335 | I_u3u1u2(_modu) |
336 | I_u3u1u2(_movn) |
337 | I_u3u1u2(_movz) |
338 | I_u1(_mfhi) |
339 | I_u1(_mflo) |
340 | I_u1u2u3(_mtc0) |
341 | I_u1u2u3(_mthc0) |
342 | I_u1(_mthi) |
343 | I_u1(_mtlo) |
344 | I_u3u1u2(_mul) |
345 | I_u1u2(_multu) |
346 | I_u3u1u2(_mulu) |
347 | I_u3u1u2(_muhu) |
348 | I_u3u1u2(_nor) |
349 | I_u3u1u2(_or) |
350 | I_u2u1u3(_ori) |
351 | I_0(_rfe) |
352 | I_u2s3u1(_sb) |
353 | I_u2s3u1(_sc) |
354 | I_u2s3u1(_scd) |
355 | I_u2s3u1(_sd) |
356 | I_u3u1u2(_seleqz) |
357 | I_u3u1u2(_selnez) |
358 | I_u2s3u1(_sh) |
359 | I_u2u1u3(_sll) |
360 | I_u3u2u1(_sllv) |
361 | I_s3s1s2(_slt) |
362 | I_u2u1s3(_slti) |
363 | I_u2u1s3(_sltiu) |
364 | I_u3u1u2(_sltu) |
365 | I_u2u1u3(_sra) |
366 | I_u3u2u1(_srav) |
367 | I_u2u1u3(_srl) |
368 | I_u3u2u1(_srlv) |
369 | I_u2u1u3(_rotr) |
370 | I_u3u1u2(_subu) |
371 | I_u2s3u1(_sw) |
372 | I_u1(_sync) |
373 | I_0(_tlbp) |
374 | I_0(_tlbr) |
375 | I_0(_tlbwi) |
376 | I_0(_tlbwr) |
377 | I_u1(_wait); |
378 | I_u2u1(_wsbh) |
379 | I_u3u1u2(_xor) |
380 | I_u2u1u3(_xori) |
381 | I_u2u1(_yield) |
382 | I_u2u1msbu3(_dins); |
383 | I_u2u1msb32u3(_dinsm); |
384 | I_u2u1msb32msb3(_dinsu); |
385 | I_u1(_syscall); |
386 | I_u1u2s3(_bbit0); |
387 | I_u1u2s3(_bbit1); |
388 | I_u3u1u2(_lwx) |
389 | I_u3u1u2(_ldx) |
390 | I_u1u2(_ldpte) |
391 | I_u2u1u3(_lddir) |
392 | |
393 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
394 | #include <asm/octeon/octeon.h> |
395 | void uasm_i_pref(u32 **buf, unsigned int a, signed int b, |
396 | unsigned int c) |
397 | { |
398 | if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && a <= 24 && a != 5) |
399 | /* |
400 | * As per erratum Core-14449, replace prefetches 0-4, |
401 | * 6-24 with 'pref 28'. |
402 | */ |
403 | build_insn(buf, insn_pref, c, 28, b); |
404 | else |
405 | build_insn(buf, insn_pref, c, a, b); |
406 | } |
407 | UASM_EXPORT_SYMBOL(uasm_i_pref); |
408 | #else |
409 | I_u2s3u1(_pref) |
410 | #endif |
411 | |
412 | /* Handle labels. */ |
413 | void uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) |
414 | { |
415 | (*lab)->addr = addr; |
416 | (*lab)->lab = lid; |
417 | (*lab)++; |
418 | } |
419 | UASM_EXPORT_SYMBOL(uasm_build_label); |
420 | |
421 | int uasm_in_compat_space_p(long addr) |
422 | { |
423 | /* Is this address in 32bit compat space? */ |
424 | return addr == (int)addr; |
425 | } |
426 | UASM_EXPORT_SYMBOL(uasm_in_compat_space_p); |
427 | |
428 | static int uasm_rel_highest(long val) |
429 | { |
430 | #ifdef CONFIG_64BIT |
431 | return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; |
432 | #else |
433 | return 0; |
434 | #endif |
435 | } |
436 | |
437 | static int uasm_rel_higher(long val) |
438 | { |
439 | #ifdef CONFIG_64BIT |
440 | return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; |
441 | #else |
442 | return 0; |
443 | #endif |
444 | } |
445 | |
446 | int uasm_rel_hi(long val) |
447 | { |
448 | return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; |
449 | } |
450 | UASM_EXPORT_SYMBOL(uasm_rel_hi); |
451 | |
452 | int uasm_rel_lo(long val) |
453 | { |
454 | return ((val & 0xffff) ^ 0x8000) - 0x8000; |
455 | } |
456 | UASM_EXPORT_SYMBOL(uasm_rel_lo); |
457 | |
458 | void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr) |
459 | { |
460 | if (!uasm_in_compat_space_p(addr)) { |
461 | uasm_i_lui(buf, rs, uasm_rel_highest(val: addr)); |
462 | if (uasm_rel_higher(val: addr)) |
463 | uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(val: addr)); |
464 | if (uasm_rel_hi(val: addr)) { |
465 | uasm_i_dsll(buf, rs, rs, 16); |
466 | uasm_i_daddiu(buf, rs, rs, |
467 | uasm_rel_hi(val: addr)); |
468 | uasm_i_dsll(buf, rs, rs, 16); |
469 | } else |
470 | uasm_i_dsll32(buf, rs, rs, 0); |
471 | } else |
472 | uasm_i_lui(buf, rs, uasm_rel_hi(val: addr)); |
473 | } |
474 | UASM_EXPORT_SYMBOL(UASM_i_LA_mostly); |
475 | |
476 | void UASM_i_LA(u32 **buf, unsigned int rs, long addr) |
477 | { |
478 | UASM_i_LA_mostly(buf, rs, addr); |
479 | if (uasm_rel_lo(val: addr)) { |
480 | if (!uasm_in_compat_space_p(addr)) |
481 | uasm_i_daddiu(buf, rs, rs, |
482 | uasm_rel_lo(val: addr)); |
483 | else |
484 | uasm_i_addiu(buf, rs, rs, |
485 | uasm_rel_lo(val: addr)); |
486 | } |
487 | } |
488 | UASM_EXPORT_SYMBOL(UASM_i_LA); |
489 | |
490 | /* Handle relocations. */ |
491 | void uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid) |
492 | { |
493 | (*rel)->addr = addr; |
494 | (*rel)->type = R_MIPS_PC16; |
495 | (*rel)->lab = lid; |
496 | (*rel)++; |
497 | } |
498 | UASM_EXPORT_SYMBOL(uasm_r_mips_pc16); |
499 | |
500 | static inline void __resolve_relocs(struct uasm_reloc *rel, |
501 | struct uasm_label *lab); |
502 | |
503 | void uasm_resolve_relocs(struct uasm_reloc *rel, |
504 | struct uasm_label *lab) |
505 | { |
506 | struct uasm_label *l; |
507 | |
508 | for (; rel->lab != UASM_LABEL_INVALID; rel++) |
509 | for (l = lab; l->lab != UASM_LABEL_INVALID; l++) |
510 | if (rel->lab == l->lab) |
511 | __resolve_relocs(rel, l); |
512 | } |
513 | UASM_EXPORT_SYMBOL(uasm_resolve_relocs); |
514 | |
515 | void uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, |
516 | long off) |
517 | { |
518 | for (; rel->lab != UASM_LABEL_INVALID; rel++) |
519 | if (rel->addr >= first && rel->addr < end) |
520 | rel->addr += off; |
521 | } |
522 | UASM_EXPORT_SYMBOL(uasm_move_relocs); |
523 | |
524 | void uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, |
525 | long off) |
526 | { |
527 | for (; lab->lab != UASM_LABEL_INVALID; lab++) |
528 | if (lab->addr >= first && lab->addr < end) |
529 | lab->addr += off; |
530 | } |
531 | UASM_EXPORT_SYMBOL(uasm_move_labels); |
532 | |
533 | void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, |
534 | u32 *first, u32 *end, u32 *target) |
535 | { |
536 | long off = (long)(target - first); |
537 | |
538 | memcpy(target, first, (end - first) * sizeof(u32)); |
539 | |
540 | uasm_move_relocs(rel, first, end, off); |
541 | uasm_move_labels(lab, first, end, off); |
542 | } |
543 | UASM_EXPORT_SYMBOL(uasm_copy_handler); |
544 | |
545 | int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr) |
546 | { |
547 | for (; rel->lab != UASM_LABEL_INVALID; rel++) { |
548 | if (rel->addr == addr |
549 | && (rel->type == R_MIPS_PC16 |
550 | || rel->type == R_MIPS_26)) |
551 | return 1; |
552 | } |
553 | |
554 | return 0; |
555 | } |
556 | UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay); |
557 | |
558 | /* Convenience functions for labeled branches. */ |
559 | void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, |
560 | int lid) |
561 | { |
562 | uasm_r_mips_pc16(rel: r, addr: *p, lid); |
563 | uasm_i_bltz(p, reg, 0); |
564 | } |
565 | UASM_EXPORT_SYMBOL(uasm_il_bltz); |
566 | |
567 | void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid) |
568 | { |
569 | uasm_r_mips_pc16(rel: r, addr: *p, lid); |
570 | uasm_i_b(p, 0); |
571 | } |
572 | UASM_EXPORT_SYMBOL(uasm_il_b); |
573 | |
574 | void uasm_il_beq(u32 **p, struct uasm_reloc **r, unsigned int r1, |
575 | unsigned int r2, int lid) |
576 | { |
577 | uasm_r_mips_pc16(rel: r, addr: *p, lid); |
578 | uasm_i_beq(p, r1, r2, 0); |
579 | } |
580 | UASM_EXPORT_SYMBOL(uasm_il_beq); |
581 | |
582 | void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, |
583 | int lid) |
584 | { |
585 | uasm_r_mips_pc16(rel: r, addr: *p, lid); |
586 | uasm_i_beqz(p, reg, 0); |
587 | } |
588 | UASM_EXPORT_SYMBOL(uasm_il_beqz); |
589 | |
590 | void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, |
591 | int lid) |
592 | { |
593 | uasm_r_mips_pc16(rel: r, addr: *p, lid); |
594 | uasm_i_beqzl(p, reg, 0); |
595 | } |
596 | UASM_EXPORT_SYMBOL(uasm_il_beqzl); |
597 | |
598 | void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1, |
599 | unsigned int reg2, int lid) |
600 | { |
601 | uasm_r_mips_pc16(rel: r, addr: *p, lid); |
602 | uasm_i_bne(p, reg1, reg2, 0); |
603 | } |
604 | UASM_EXPORT_SYMBOL(uasm_il_bne); |
605 | |
606 | void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, |
607 | int lid) |
608 | { |
609 | uasm_r_mips_pc16(rel: r, addr: *p, lid); |
610 | uasm_i_bnez(p, reg, 0); |
611 | } |
612 | UASM_EXPORT_SYMBOL(uasm_il_bnez); |
613 | |
614 | void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, |
615 | int lid) |
616 | { |
617 | uasm_r_mips_pc16(rel: r, addr: *p, lid); |
618 | uasm_i_bgezl(p, reg, 0); |
619 | } |
620 | UASM_EXPORT_SYMBOL(uasm_il_bgezl); |
621 | |
622 | void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, |
623 | int lid) |
624 | { |
625 | uasm_r_mips_pc16(rel: r, addr: *p, lid); |
626 | uasm_i_bgez(p, reg, 0); |
627 | } |
628 | UASM_EXPORT_SYMBOL(uasm_il_bgez); |
629 | |
630 | void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg, |
631 | unsigned int bit, int lid) |
632 | { |
633 | uasm_r_mips_pc16(rel: r, addr: *p, lid); |
634 | uasm_i_bbit0(p, reg, bit, 0); |
635 | } |
636 | UASM_EXPORT_SYMBOL(uasm_il_bbit0); |
637 | |
638 | void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg, |
639 | unsigned int bit, int lid) |
640 | { |
641 | uasm_r_mips_pc16(rel: r, addr: *p, lid); |
642 | uasm_i_bbit1(p, reg, bit, 0); |
643 | } |
644 | UASM_EXPORT_SYMBOL(uasm_il_bbit1); |
645 | |