1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * |
4 | * Parts of this file are based on Ralink's 2.6.21 BSP |
5 | * |
6 | * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> |
7 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
8 | * Copyright (C) 2013 John Crispin <john@phrozen.org> |
9 | */ |
10 | |
11 | #include <linux/kernel.h> |
12 | #include <linux/init.h> |
13 | #include <linux/bug.h> |
14 | #include <linux/slab.h> |
15 | #include <linux/sys_soc.h> |
16 | |
17 | #include <asm/mipsregs.h> |
18 | #include <asm/mach-ralink/ralink_regs.h> |
19 | #include <asm/mach-ralink/mt7620.h> |
20 | |
21 | #include "common.h" |
22 | |
23 | /* analog */ |
24 | #define PMU0_CFG 0x88 |
25 | #define PMU_SW_SET BIT(28) |
26 | #define A_DCDC_EN BIT(24) |
27 | #define A_SSC_PERI BIT(19) |
28 | #define A_SSC_GEN BIT(18) |
29 | #define A_SSC_M 0x3 |
30 | #define A_SSC_S 16 |
31 | #define A_DLY_M 0x7 |
32 | #define A_DLY_S 8 |
33 | #define A_VTUNE_M 0xff |
34 | |
35 | /* digital */ |
36 | #define PMU1_CFG 0x8C |
37 | #define DIG_SW_SEL BIT(25) |
38 | |
39 | /* EFUSE bits */ |
40 | #define EFUSE_MT7688 0x100000 |
41 | |
42 | /* DRAM type bit */ |
43 | #define DRAM_TYPE_MT7628_MASK 0x1 |
44 | |
45 | /* does the board have sdram or ddram */ |
46 | static int dram_type; |
47 | |
48 | static struct ralink_soc_info *soc_info_ptr; |
49 | |
50 | static __init void |
51 | mt7620_dram_init(struct ralink_soc_info *soc_info) |
52 | { |
53 | switch (dram_type) { |
54 | case SYSCFG0_DRAM_TYPE_SDRAM: |
55 | pr_info("Board has SDRAM\n" ); |
56 | soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN; |
57 | soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX; |
58 | break; |
59 | |
60 | case SYSCFG0_DRAM_TYPE_DDR1: |
61 | pr_info("Board has DDR1\n" ); |
62 | soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; |
63 | soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; |
64 | break; |
65 | |
66 | case SYSCFG0_DRAM_TYPE_DDR2: |
67 | pr_info("Board has DDR2\n" ); |
68 | soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; |
69 | soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; |
70 | break; |
71 | default: |
72 | BUG(); |
73 | } |
74 | } |
75 | |
76 | static __init void |
77 | mt7628_dram_init(struct ralink_soc_info *soc_info) |
78 | { |
79 | switch (dram_type) { |
80 | case SYSCFG0_DRAM_TYPE_DDR1_MT7628: |
81 | pr_info("Board has DDR1\n" ); |
82 | soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN; |
83 | soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX; |
84 | break; |
85 | |
86 | case SYSCFG0_DRAM_TYPE_DDR2_MT7628: |
87 | pr_info("Board has DDR2\n" ); |
88 | soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN; |
89 | soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX; |
90 | break; |
91 | default: |
92 | BUG(); |
93 | } |
94 | } |
95 | |
96 | static unsigned int __init mt7620_get_soc_name0(void) |
97 | { |
98 | return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME0); |
99 | } |
100 | |
101 | static unsigned int __init mt7620_get_soc_name1(void) |
102 | { |
103 | return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME1); |
104 | } |
105 | |
106 | static bool __init mt7620_soc_valid(void) |
107 | { |
108 | if (mt7620_get_soc_name0() == MT7620_CHIP_NAME0 && |
109 | mt7620_get_soc_name1() == MT7620_CHIP_NAME1) |
110 | return true; |
111 | else |
112 | return false; |
113 | } |
114 | |
115 | static bool __init mt7628_soc_valid(void) |
116 | { |
117 | if (mt7620_get_soc_name0() == MT7620_CHIP_NAME0 && |
118 | mt7620_get_soc_name1() == MT7628_CHIP_NAME1) |
119 | return true; |
120 | else |
121 | return false; |
122 | } |
123 | |
124 | static unsigned int __init mt7620_get_rev(void) |
125 | { |
126 | return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_REV); |
127 | } |
128 | |
129 | static unsigned int __init mt7620_get_bga(void) |
130 | { |
131 | return (mt7620_get_rev() >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK; |
132 | } |
133 | |
134 | static unsigned int __init mt7620_get_efuse(void) |
135 | { |
136 | return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_EFUSE_CFG); |
137 | } |
138 | |
139 | static unsigned int __init mt7620_get_soc_ver(void) |
140 | { |
141 | return (mt7620_get_rev() >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK; |
142 | } |
143 | |
144 | static unsigned int __init mt7620_get_soc_eco(void) |
145 | { |
146 | return (mt7620_get_rev() & CHIP_REV_ECO_MASK); |
147 | } |
148 | |
149 | static const char __init *mt7620_get_soc_name(struct ralink_soc_info *soc_info) |
150 | { |
151 | if (mt7620_soc_valid()) { |
152 | u32 bga = mt7620_get_bga(); |
153 | |
154 | if (bga) { |
155 | ralink_soc = MT762X_SOC_MT7620A; |
156 | soc_info->compatible = "ralink,mt7620a-soc" ; |
157 | return "MT7620A" ; |
158 | } else { |
159 | ralink_soc = MT762X_SOC_MT7620N; |
160 | soc_info->compatible = "ralink,mt7620n-soc" ; |
161 | return "MT7620N" ; |
162 | } |
163 | } else if (mt7628_soc_valid()) { |
164 | u32 efuse = mt7620_get_efuse(); |
165 | unsigned char *name = NULL; |
166 | |
167 | if (efuse & EFUSE_MT7688) { |
168 | ralink_soc = MT762X_SOC_MT7688; |
169 | name = "MT7688" ; |
170 | } else { |
171 | ralink_soc = MT762X_SOC_MT7628AN; |
172 | name = "MT7628AN" ; |
173 | } |
174 | soc_info->compatible = "ralink,mt7628an-soc" ; |
175 | return name; |
176 | } else { |
177 | panic(fmt: "mt762x: unknown SoC, n0:%08x n1:%08x\n" , |
178 | mt7620_get_soc_name0(), mt7620_get_soc_name1()); |
179 | } |
180 | } |
181 | |
182 | static const char __init *mt7620_get_soc_id_name(void) |
183 | { |
184 | if (ralink_soc == MT762X_SOC_MT7620A) |
185 | return "mt7620a" ; |
186 | else if (ralink_soc == MT762X_SOC_MT7620N) |
187 | return "mt7620n" ; |
188 | else if (ralink_soc == MT762X_SOC_MT7688) |
189 | return "mt7688" ; |
190 | else if (ralink_soc == MT762X_SOC_MT7628AN) |
191 | return "mt7628n" ; |
192 | else |
193 | return "invalid" ; |
194 | } |
195 | |
196 | static int __init mt7620_soc_dev_init(void) |
197 | { |
198 | struct soc_device *soc_dev; |
199 | struct soc_device_attribute *soc_dev_attr; |
200 | |
201 | soc_dev_attr = kzalloc(size: sizeof(*soc_dev_attr), GFP_KERNEL); |
202 | if (!soc_dev_attr) |
203 | return -ENOMEM; |
204 | |
205 | soc_dev_attr->family = "Ralink" ; |
206 | soc_dev_attr->soc_id = mt7620_get_soc_id_name(); |
207 | |
208 | soc_dev_attr->data = soc_info_ptr; |
209 | |
210 | soc_dev = soc_device_register(soc_plat_dev_attr: soc_dev_attr); |
211 | if (IS_ERR(ptr: soc_dev)) { |
212 | kfree(objp: soc_dev_attr); |
213 | return PTR_ERR(ptr: soc_dev); |
214 | } |
215 | |
216 | return 0; |
217 | } |
218 | device_initcall(mt7620_soc_dev_init); |
219 | |
220 | void __init prom_soc_init(struct ralink_soc_info *soc_info) |
221 | { |
222 | const char *name = mt7620_get_soc_name(soc_info); |
223 | u32 cfg0; |
224 | u32 pmu0; |
225 | u32 pmu1; |
226 | |
227 | snprintf(buf: soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, |
228 | fmt: "MediaTek %s ver:%u eco:%u" , |
229 | name, mt7620_get_soc_ver(), mt7620_get_soc_eco()); |
230 | |
231 | cfg0 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG0); |
232 | if (is_mt76x8()) { |
233 | dram_type = cfg0 & DRAM_TYPE_MT7628_MASK; |
234 | } else { |
235 | dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & |
236 | SYSCFG0_DRAM_TYPE_MASK; |
237 | if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN) |
238 | dram_type = SYSCFG0_DRAM_TYPE_SDRAM; |
239 | } |
240 | |
241 | soc_info->mem_base = MT7620_DRAM_BASE; |
242 | if (is_mt76x8()) |
243 | mt7628_dram_init(soc_info); |
244 | else |
245 | mt7620_dram_init(soc_info); |
246 | |
247 | pmu0 = __raw_readl(MT7620_SYSC_BASE + PMU0_CFG); |
248 | pmu1 = __raw_readl(MT7620_SYSC_BASE + PMU1_CFG); |
249 | |
250 | pr_info("Analog PMU set to %s control\n" , |
251 | (pmu0 & PMU_SW_SET) ? ("sw" ) : ("hw" )); |
252 | pr_info("Digital PMU set to %s control\n" , |
253 | (pmu1 & DIG_SW_SEL) ? ("sw" ) : ("hw" )); |
254 | |
255 | soc_info_ptr = soc_info; |
256 | } |
257 | |