1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | #ifndef _PPC64_PPC_ASM_H |
3 | #define _PPC64_PPC_ASM_H |
4 | /* |
5 | * |
6 | * Definitions used by various bits of low-level assembly code on PowerPC. |
7 | * |
8 | * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. |
9 | */ |
10 | |
11 | /* Condition Register Bit Fields */ |
12 | |
13 | #define cr0 0 |
14 | #define cr1 1 |
15 | #define cr2 2 |
16 | #define cr3 3 |
17 | #define cr4 4 |
18 | #define cr5 5 |
19 | #define cr6 6 |
20 | #define cr7 7 |
21 | |
22 | |
23 | /* General Purpose Registers (GPRs) */ |
24 | |
25 | #define r0 0 |
26 | #define r1 1 |
27 | #define r2 2 |
28 | #define r3 3 |
29 | #define r4 4 |
30 | #define r5 5 |
31 | #define r6 6 |
32 | #define r7 7 |
33 | #define r8 8 |
34 | #define r9 9 |
35 | #define r10 10 |
36 | #define r11 11 |
37 | #define r12 12 |
38 | #define r13 13 |
39 | #define r14 14 |
40 | #define r15 15 |
41 | #define r16 16 |
42 | #define r17 17 |
43 | #define r18 18 |
44 | #define r19 19 |
45 | #define r20 20 |
46 | #define r21 21 |
47 | #define r22 22 |
48 | #define r23 23 |
49 | #define r24 24 |
50 | #define r25 25 |
51 | #define r26 26 |
52 | #define r27 27 |
53 | #define r28 28 |
54 | #define r29 29 |
55 | #define r30 30 |
56 | #define r31 31 |
57 | |
58 | #define SPRN_TBRL 268 |
59 | #define SPRN_TBRU 269 |
60 | #define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */ |
61 | #define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ |
62 | |
63 | #define MSR_LE 0x0000000000000001 |
64 | |
65 | #define FIXUP_ENDIAN \ |
66 | tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ |
67 | b $+44; /* Skip trampoline if endian is good */ \ |
68 | .long 0xa600607d; /* mfmsr r11 */ \ |
69 | .long 0x01006b69; /* xori r11,r11,1 */ \ |
70 | .long 0x00004039; /* li r10,0 */ \ |
71 | .long 0x6401417d; /* mtmsrd r10,1 */ \ |
72 | .long 0x05009f42; /* bcl 20,31,$+4 */ \ |
73 | .long 0xa602487d; /* mflr r10 */ \ |
74 | .long 0x14004a39; /* addi r10,r10,20 */ \ |
75 | .long 0xa6035a7d; /* mtsrr0 r10 */ \ |
76 | .long 0xa6037b7d; /* mtsrr1 r11 */ \ |
77 | .long 0x2400004c /* rfid */ |
78 | |
79 | #ifdef CONFIG_PPC_8xx |
80 | #define MFTBL(dest) mftb dest |
81 | #define MFTBU(dest) mftbu dest |
82 | #else |
83 | #define MFTBL(dest) mfspr dest, SPRN_TBRL |
84 | #define MFTBU(dest) mfspr dest, SPRN_TBRU |
85 | #endif |
86 | |
87 | #ifdef CONFIG_PPC64_BOOT_WRAPPER |
88 | #define LOAD_REG_ADDR(reg,name) \ |
89 | addis reg,r2,name@toc@ha; \ |
90 | addi reg,reg,name@toc@l |
91 | #else |
92 | #define LOAD_REG_ADDR(reg,name) \ |
93 | lis reg,name@ha; \ |
94 | addi reg,reg,name@l |
95 | #endif |
96 | |
97 | #endif /* _PPC64_PPC_ASM_H */ |
98 | |