1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
4 | */ |
5 | |
6 | #ifndef _POWERPC_SYSDEV_DART_H |
7 | #define _POWERPC_SYSDEV_DART_H |
8 | |
9 | |
10 | /* Offset from base to control register */ |
11 | #define DART_CNTL 0 |
12 | |
13 | /* Offset from base to exception register */ |
14 | #define DART_EXCP_U3 0x10 |
15 | /* Offset from base to TLB tag registers */ |
16 | #define DART_TAGS_U3 0x1000 |
17 | |
18 | /* U4 registers */ |
19 | #define DART_BASE_U4 0x10 |
20 | #define DART_SIZE_U4 0x20 |
21 | #define DART_EXCP_U4 0x30 |
22 | #define DART_TAGS_U4 0x1000 |
23 | |
24 | /* Control Register fields */ |
25 | |
26 | /* U3 registers */ |
27 | #define DART_CNTL_U3_BASE_MASK 0xfffff |
28 | #define DART_CNTL_U3_BASE_SHIFT 12 |
29 | #define DART_CNTL_U3_FLUSHTLB 0x400 |
30 | #define DART_CNTL_U3_ENABLE 0x200 |
31 | #define DART_CNTL_U3_SIZE_MASK 0x1ff |
32 | #define DART_CNTL_U3_SIZE_SHIFT 0 |
33 | |
34 | /* U4 registers */ |
35 | #define DART_BASE_U4_BASE_MASK 0xffffff |
36 | #define DART_BASE_U4_BASE_SHIFT 0 |
37 | #define DART_CNTL_U4_ENABLE 0x80000000 |
38 | #define DART_CNTL_U4_IONE 0x40000000 |
39 | #define DART_CNTL_U4_FLUSHTLB 0x20000000 |
40 | #define DART_CNTL_U4_IDLE 0x10000000 |
41 | #define DART_CNTL_U4_PAR_EN 0x08000000 |
42 | #define DART_CNTL_U4_IONE_MASK 0x07ffffff |
43 | #define DART_SIZE_U4_SIZE_MASK 0x1fff |
44 | #define DART_SIZE_U4_SIZE_SHIFT 0 |
45 | |
46 | #define DART_REG(r) (dart + ((r) >> 2)) |
47 | #define DART_IN(r) (in_be32(DART_REG(r))) |
48 | #define DART_OUT(r,v) (out_be32(DART_REG(r), (v))) |
49 | |
50 | |
51 | /* size of table in pages */ |
52 | |
53 | |
54 | /* DART table fields */ |
55 | |
56 | #define DARTMAP_VALID 0x80000000 |
57 | #define DARTMAP_RPNMASK 0x00ffffff |
58 | |
59 | |
60 | #define DART_PAGE_SHIFT 12 |
61 | #define DART_PAGE_SIZE (1 << DART_PAGE_SHIFT) |
62 | |
63 | |
64 | #endif /* _POWERPC_SYSDEV_DART_H */ |
65 | |