1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* ppc-opc.c -- PowerPC opcode list |
3 | Copyright (C) 1994-2016 Free Software Foundation, Inc. |
4 | Written by Ian Lance Taylor, Cygnus Support |
5 | |
6 | This file is part of GDB, GAS, and the GNU binutils. |
7 | |
8 | */ |
9 | |
10 | #include <linux/stddef.h> |
11 | #include <linux/kernel.h> |
12 | #include <linux/bug.h> |
13 | #include "nonstdio.h" |
14 | #include "ppc.h" |
15 | |
16 | #define ATTRIBUTE_UNUSED |
17 | #define _(x) x |
18 | |
19 | /* This file holds the PowerPC opcode table. The opcode table |
20 | includes almost all of the extended instruction mnemonics. This |
21 | permits the disassembler to use them, and simplifies the assembler |
22 | logic, at the cost of increasing the table size. The table is |
23 | strictly constant data, so the compiler should be able to put it in |
24 | the .text section. |
25 | |
26 | This file also holds the operand table. All knowledge about |
27 | inserting operands into instructions and vice-versa is kept in this |
28 | file. */ |
29 | |
30 | /* Local insertion and extraction functions. */ |
31 | |
32 | static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **); |
33 | static long extract_arx (unsigned long, ppc_cpu_t, int *); |
34 | static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **); |
35 | static long extract_ary (unsigned long, ppc_cpu_t, int *); |
36 | static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **); |
37 | static long extract_bat (unsigned long, ppc_cpu_t, int *); |
38 | static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **); |
39 | static long extract_bba (unsigned long, ppc_cpu_t, int *); |
40 | static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **); |
41 | static long extract_bdm (unsigned long, ppc_cpu_t, int *); |
42 | static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **); |
43 | static long extract_bdp (unsigned long, ppc_cpu_t, int *); |
44 | static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **); |
45 | static long extract_bo (unsigned long, ppc_cpu_t, int *); |
46 | static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **); |
47 | static long extract_boe (unsigned long, ppc_cpu_t, int *); |
48 | static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **); |
49 | static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **); |
50 | static long extract_dcmxs (unsigned long, ppc_cpu_t, int *); |
51 | static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **); |
52 | static long extract_dxd (unsigned long, ppc_cpu_t, int *); |
53 | static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **); |
54 | static long extract_dxdn (unsigned long, ppc_cpu_t, int *); |
55 | static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **); |
56 | static long extract_fxm (unsigned long, ppc_cpu_t, int *); |
57 | static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **); |
58 | static long extract_li20 (unsigned long, ppc_cpu_t, int *); |
59 | static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **); |
60 | static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **); |
61 | static long extract_mbe (unsigned long, ppc_cpu_t, int *); |
62 | static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **); |
63 | static long extract_mb6 (unsigned long, ppc_cpu_t, int *); |
64 | static long extract_nb (unsigned long, ppc_cpu_t, int *); |
65 | static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **); |
66 | static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **); |
67 | static long extract_nsi (unsigned long, ppc_cpu_t, int *); |
68 | static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **); |
69 | static long extract_oimm (unsigned long, ppc_cpu_t, int *); |
70 | static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **); |
71 | static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **); |
72 | static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **); |
73 | static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **); |
74 | static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **); |
75 | static long extract_rbs (unsigned long, ppc_cpu_t, int *); |
76 | static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **); |
77 | static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **); |
78 | static long extract_rx (unsigned long, ppc_cpu_t, int *); |
79 | static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **); |
80 | static long extract_ry (unsigned long, ppc_cpu_t, int *); |
81 | static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **); |
82 | static long extract_sh6 (unsigned long, ppc_cpu_t, int *); |
83 | static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **); |
84 | static long extract_sci8 (unsigned long, ppc_cpu_t, int *); |
85 | static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **); |
86 | static long extract_sci8n (unsigned long, ppc_cpu_t, int *); |
87 | static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **); |
88 | static long extract_sd4h (unsigned long, ppc_cpu_t, int *); |
89 | static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **); |
90 | static long extract_sd4w (unsigned long, ppc_cpu_t, int *); |
91 | static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **); |
92 | static long extract_spr (unsigned long, ppc_cpu_t, int *); |
93 | static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **); |
94 | static long extract_sprg (unsigned long, ppc_cpu_t, int *); |
95 | static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **); |
96 | static long extract_tbr (unsigned long, ppc_cpu_t, int *); |
97 | static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **); |
98 | static long extract_xt6 (unsigned long, ppc_cpu_t, int *); |
99 | static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **); |
100 | static long extract_xtq6 (unsigned long, ppc_cpu_t, int *); |
101 | static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **); |
102 | static long extract_xa6 (unsigned long, ppc_cpu_t, int *); |
103 | static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **); |
104 | static long extract_xb6 (unsigned long, ppc_cpu_t, int *); |
105 | static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **); |
106 | static long extract_xb6s (unsigned long, ppc_cpu_t, int *); |
107 | static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **); |
108 | static long extract_xc6 (unsigned long, ppc_cpu_t, int *); |
109 | static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **); |
110 | static long extract_dm (unsigned long, ppc_cpu_t, int *); |
111 | static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **); |
112 | static long extract_vlesi (unsigned long, ppc_cpu_t, int *); |
113 | static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **); |
114 | static long extract_vlensi (unsigned long, ppc_cpu_t, int *); |
115 | static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **); |
116 | static long extract_vleui (unsigned long, ppc_cpu_t, int *); |
117 | static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **); |
118 | static long extract_vleil (unsigned long, ppc_cpu_t, int *); |
119 | |
120 | /* The operands table. |
121 | |
122 | The fields are bitm, shift, insert, extract, flags. |
123 | |
124 | We used to put parens around the various additions, like the one |
125 | for BA just below. However, that caused trouble with feeble |
126 | compilers with a limit on depth of a parenthesized expression, like |
127 | (reportedly) the compiler in Microsoft Developer Studio 5. So we |
128 | omit the parens, since the macros are never used in a context where |
129 | the addition will be ambiguous. */ |
130 | |
131 | const struct powerpc_operand powerpc_operands[] = |
132 | { |
133 | /* The zero index is used to indicate the end of the list of |
134 | operands. */ |
135 | #define UNUSED 0 |
136 | { 0, 0, NULL, NULL, 0 }, |
137 | |
138 | /* The BA field in an XL form instruction. */ |
139 | #define BA UNUSED + 1 |
140 | /* The BI field in a B form or XL form instruction. */ |
141 | #define BI BA |
142 | #define BI_MASK (0x1f << 16) |
143 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, |
144 | |
145 | /* The BA field in an XL form instruction when it must be the same |
146 | as the BT field in the same instruction. */ |
147 | #define BAT BA + 1 |
148 | { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, |
149 | |
150 | /* The BB field in an XL form instruction. */ |
151 | #define BB BAT + 1 |
152 | #define BB_MASK (0x1f << 11) |
153 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT }, |
154 | |
155 | /* The BB field in an XL form instruction when it must be the same |
156 | as the BA field in the same instruction. */ |
157 | #define BBA BB + 1 |
158 | /* The VB field in a VX form instruction when it must be the same |
159 | as the VA field in the same instruction. */ |
160 | #define VBA BBA |
161 | { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, |
162 | |
163 | /* The BD field in a B form instruction. The lower two bits are |
164 | forced to zero. */ |
165 | #define BD BBA + 1 |
166 | { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
167 | |
168 | /* The BD field in a B form instruction when absolute addressing is |
169 | used. */ |
170 | #define BDA BD + 1 |
171 | { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
172 | |
173 | /* The BD field in a B form instruction when the - modifier is used. |
174 | This sets the y bit of the BO field appropriately. */ |
175 | #define BDM BDA + 1 |
176 | { 0xfffc, 0, insert_bdm, extract_bdm, |
177 | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
178 | |
179 | /* The BD field in a B form instruction when the - modifier is used |
180 | and absolute address is used. */ |
181 | #define BDMA BDM + 1 |
182 | { 0xfffc, 0, insert_bdm, extract_bdm, |
183 | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
184 | |
185 | /* The BD field in a B form instruction when the + modifier is used. |
186 | This sets the y bit of the BO field appropriately. */ |
187 | #define BDP BDMA + 1 |
188 | { 0xfffc, 0, insert_bdp, extract_bdp, |
189 | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
190 | |
191 | /* The BD field in a B form instruction when the + modifier is used |
192 | and absolute addressing is used. */ |
193 | #define BDPA BDP + 1 |
194 | { 0xfffc, 0, insert_bdp, extract_bdp, |
195 | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
196 | |
197 | /* The BF field in an X or XL form instruction. */ |
198 | #define BF BDPA + 1 |
199 | /* The CRFD field in an X form instruction. */ |
200 | #define CRFD BF |
201 | /* The CRD field in an XL form instruction. */ |
202 | #define CRD BF |
203 | { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG }, |
204 | |
205 | /* The BF field in an X or XL form instruction. */ |
206 | #define BFF BF + 1 |
207 | { 0x7, 23, NULL, NULL, 0 }, |
208 | |
209 | /* An optional BF field. This is used for comparison instructions, |
210 | in which an omitted BF field is taken as zero. */ |
211 | #define OBF BFF + 1 |
212 | { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, |
213 | |
214 | /* The BFA field in an X or XL form instruction. */ |
215 | #define BFA OBF + 1 |
216 | { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG }, |
217 | |
218 | /* The BO field in a B form instruction. Certain values are |
219 | illegal. */ |
220 | #define BO BFA + 1 |
221 | #define BO_MASK (0x1f << 21) |
222 | { 0x1f, 21, insert_bo, extract_bo, 0 }, |
223 | |
224 | /* The BO field in a B form instruction when the + or - modifier is |
225 | used. This is like the BO field, but it must be even. */ |
226 | #define BOE BO + 1 |
227 | { 0x1e, 21, insert_boe, extract_boe, 0 }, |
228 | |
229 | /* The RM field in an X form instruction. */ |
230 | #define RM BOE + 1 |
231 | { 0x3, 11, NULL, NULL, 0 }, |
232 | |
233 | #define BH RM + 1 |
234 | { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
235 | |
236 | /* The BT field in an X or XL form instruction. */ |
237 | #define BT BH + 1 |
238 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT }, |
239 | |
240 | /* The BI16 field in a BD8 form instruction. */ |
241 | #define BI16 BT + 1 |
242 | { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT }, |
243 | |
244 | /* The BI32 field in a BD15 form instruction. */ |
245 | #define BI32 BI16 + 1 |
246 | { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, |
247 | |
248 | /* The BO32 field in a BD15 form instruction. */ |
249 | #define BO32 BI32 + 1 |
250 | { 0x3, 20, NULL, NULL, 0 }, |
251 | |
252 | /* The B8 field in a BD8 form instruction. */ |
253 | #define B8 BO32 + 1 |
254 | { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
255 | |
256 | /* The B15 field in a BD15 form instruction. The lowest bit is |
257 | forced to zero. */ |
258 | #define B15 B8 + 1 |
259 | { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
260 | |
261 | /* The B24 field in a BD24 form instruction. The lowest bit is |
262 | forced to zero. */ |
263 | #define B24 B15 + 1 |
264 | { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
265 | |
266 | /* The condition register number portion of the BI field in a B form |
267 | or XL form instruction. This is used for the extended |
268 | conditional branch mnemonics, which set the lower two bits of the |
269 | BI field. This field is optional. */ |
270 | #define CR B24 + 1 |
271 | { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, |
272 | |
273 | /* The CRB field in an X form instruction. */ |
274 | #define CRB CR + 1 |
275 | /* The MB field in an M form instruction. */ |
276 | #define MB CRB |
277 | #define MB_MASK (0x1f << 6) |
278 | { 0x1f, 6, NULL, NULL, 0 }, |
279 | |
280 | /* The CRD32 field in an XL form instruction. */ |
281 | #define CRD32 CRB + 1 |
282 | { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG }, |
283 | |
284 | /* The CRFS field in an X form instruction. */ |
285 | #define CRFS CRD32 + 1 |
286 | { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG }, |
287 | |
288 | #define CRS CRFS + 1 |
289 | { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, |
290 | |
291 | /* The CT field in an X form instruction. */ |
292 | #define CT CRS + 1 |
293 | /* The MO field in an mbar instruction. */ |
294 | #define MO CT |
295 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
296 | |
297 | /* The D field in a D form instruction. This is a displacement off |
298 | a register, and implies that the next operand is a register in |
299 | parentheses. */ |
300 | #define D CT + 1 |
301 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
302 | |
303 | /* The D8 field in a D form instruction. This is a displacement off |
304 | a register, and implies that the next operand is a register in |
305 | parentheses. */ |
306 | #define D8 D + 1 |
307 | { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
308 | |
309 | /* The DCMX field in an X form instruction. */ |
310 | #define DCMX D8 + 1 |
311 | { 0x7f, 16, NULL, NULL, 0 }, |
312 | |
313 | /* The split DCMX field in an X form instruction. */ |
314 | #define DCMXS DCMX + 1 |
315 | { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 }, |
316 | |
317 | /* The DQ field in a DQ form instruction. This is like D, but the |
318 | lower four bits are forced to zero. */ |
319 | #define DQ DCMXS + 1 |
320 | { 0xfff0, 0, NULL, NULL, |
321 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, |
322 | |
323 | /* The DS field in a DS form instruction. This is like D, but the |
324 | lower two bits are forced to zero. */ |
325 | #define DS DQ + 1 |
326 | { 0xfffc, 0, NULL, NULL, |
327 | PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, |
328 | |
329 | /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits |
330 | unsigned imediate */ |
331 | #define DUIS DS + 1 |
332 | #define BHRBE DUIS |
333 | { 0x3ff, 11, NULL, NULL, 0 }, |
334 | |
335 | /* The split D field in a DX form instruction. */ |
336 | #define DXD DUIS + 1 |
337 | { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd, |
338 | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, |
339 | |
340 | /* The split ND field in a DX form instruction. |
341 | This is the same as the DX field, only negated. */ |
342 | #define NDXD DXD + 1 |
343 | { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn, |
344 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, |
345 | |
346 | /* The E field in a wrteei instruction. */ |
347 | /* And the W bit in the pair singles instructions. */ |
348 | /* And the ST field in a VX form instruction. */ |
349 | #define E NDXD + 1 |
350 | #define PSW E |
351 | #define ST E |
352 | { 0x1, 15, NULL, NULL, 0 }, |
353 | |
354 | /* The FL1 field in a POWER SC form instruction. */ |
355 | #define FL1 E + 1 |
356 | /* The U field in an X form instruction. */ |
357 | #define U FL1 |
358 | { 0xf, 12, NULL, NULL, 0 }, |
359 | |
360 | /* The FL2 field in a POWER SC form instruction. */ |
361 | #define FL2 FL1 + 1 |
362 | { 0x7, 2, NULL, NULL, 0 }, |
363 | |
364 | /* The FLM field in an XFL form instruction. */ |
365 | #define FLM FL2 + 1 |
366 | { 0xff, 17, NULL, NULL, 0 }, |
367 | |
368 | /* The FRA field in an X or A form instruction. */ |
369 | #define FRA FLM + 1 |
370 | #define FRA_MASK (0x1f << 16) |
371 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, |
372 | |
373 | /* The FRAp field of DFP instructions. */ |
374 | #define FRAp FRA + 1 |
375 | { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR }, |
376 | |
377 | /* The FRB field in an X or A form instruction. */ |
378 | #define FRB FRAp + 1 |
379 | #define FRB_MASK (0x1f << 11) |
380 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, |
381 | |
382 | /* The FRBp field of DFP instructions. */ |
383 | #define FRBp FRB + 1 |
384 | { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR }, |
385 | |
386 | /* The FRC field in an A form instruction. */ |
387 | #define FRC FRBp + 1 |
388 | #define FRC_MASK (0x1f << 6) |
389 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, |
390 | |
391 | /* The FRS field in an X form instruction or the FRT field in a D, X |
392 | or A form instruction. */ |
393 | #define FRS FRC + 1 |
394 | #define FRT FRS |
395 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, |
396 | |
397 | /* The FRSp field of stfdp or the FRTp field of lfdp and DFP |
398 | instructions. */ |
399 | #define FRSp FRS + 1 |
400 | #define FRTp FRSp |
401 | { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR }, |
402 | |
403 | /* The FXM field in an XFX instruction. */ |
404 | #define FXM FRSp + 1 |
405 | { 0xff, 12, insert_fxm, extract_fxm, 0 }, |
406 | |
407 | /* Power4 version for mfcr. */ |
408 | #define FXM4 FXM + 1 |
409 | { 0xff, 12, insert_fxm, extract_fxm, |
410 | PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, |
411 | /* If the FXM4 operand is omitted, use the sentinel value -1. */ |
412 | { -1, -1, NULL, NULL, 0}, |
413 | |
414 | /* The IMM20 field in an LI instruction. */ |
415 | #define IMM20 FXM4 + 2 |
416 | { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED}, |
417 | |
418 | /* The L field in a D or X form instruction. */ |
419 | #define L IMM20 + 1 |
420 | { 0x1, 21, NULL, NULL, 0 }, |
421 | |
422 | /* The optional L field in tlbie and tlbiel instructions. */ |
423 | #define LOPT L + 1 |
424 | /* The R field in a HTM X form instruction. */ |
425 | #define HTM_R LOPT |
426 | { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
427 | |
428 | /* The optional (for 32-bit) L field in cmp[l][i] instructions. */ |
429 | #define L32OPT LOPT + 1 |
430 | { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 }, |
431 | |
432 | /* The L field in dcbf instruction. */ |
433 | #define L2OPT L32OPT + 1 |
434 | { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
435 | |
436 | /* The LEV field in a POWER SVC form instruction. */ |
437 | #define SVC_LEV L2OPT + 1 |
438 | { 0x7f, 5, NULL, NULL, 0 }, |
439 | |
440 | /* The LEV field in an SC form instruction. */ |
441 | #define LEV SVC_LEV + 1 |
442 | { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
443 | |
444 | /* The LI field in an I form instruction. The lower two bits are |
445 | forced to zero. */ |
446 | #define LI LEV + 1 |
447 | { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
448 | |
449 | /* The LI field in an I form instruction when used as an absolute |
450 | address. */ |
451 | #define LIA LI + 1 |
452 | { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
453 | |
454 | /* The LS or WC field in an X (sync or wait) form instruction. */ |
455 | #define LS LIA + 1 |
456 | #define WC LS |
457 | { 0x3, 21, insert_ls, NULL, PPC_OPERAND_OPTIONAL }, |
458 | |
459 | /* The ME field in an M form instruction. */ |
460 | #define ME LS + 1 |
461 | #define ME_MASK (0x1f << 1) |
462 | { 0x1f, 1, NULL, NULL, 0 }, |
463 | |
464 | /* The MB and ME fields in an M form instruction expressed a single |
465 | operand which is a bitmask indicating which bits to select. This |
466 | is a two operand form using PPC_OPERAND_NEXT. See the |
467 | description in opcode/ppc.h for what this means. */ |
468 | #define MBE ME + 1 |
469 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, |
470 | { -1, 0, insert_mbe, extract_mbe, 0 }, |
471 | |
472 | /* The MB or ME field in an MD or MDS form instruction. The high |
473 | bit is wrapped to the low end. */ |
474 | #define MB6 MBE + 2 |
475 | #define ME6 MB6 |
476 | #define MB6_MASK (0x3f << 5) |
477 | { 0x3f, 5, insert_mb6, extract_mb6, 0 }, |
478 | |
479 | /* The NB field in an X form instruction. The value 32 is stored as |
480 | 0. */ |
481 | #define NB MB6 + 1 |
482 | { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, |
483 | |
484 | /* The NBI field in an lswi instruction, which has special value |
485 | restrictions. The value 32 is stored as 0. */ |
486 | #define NBI NB + 1 |
487 | { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 }, |
488 | |
489 | /* The NSI field in a D form instruction. This is the same as the |
490 | SI field, only negated. */ |
491 | #define NSI NBI + 1 |
492 | { 0xffff, 0, insert_nsi, extract_nsi, |
493 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
494 | |
495 | /* The NSI field in a D form instruction when we accept a wide range |
496 | of positive values. */ |
497 | #define NSISIGNOPT NSI + 1 |
498 | { 0xffff, 0, insert_nsi, extract_nsi, |
499 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
500 | |
501 | /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ |
502 | #define RA NSISIGNOPT + 1 |
503 | #define RA_MASK (0x1f << 16) |
504 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, |
505 | |
506 | /* As above, but 0 in the RA field means zero, not r0. */ |
507 | #define RA0 RA + 1 |
508 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, |
509 | |
510 | /* The RA field in the DQ form lq or an lswx instruction, which have special |
511 | value restrictions. */ |
512 | #define RAQ RA0 + 1 |
513 | #define RAX RAQ |
514 | { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 }, |
515 | |
516 | /* The RA field in a D or X form instruction which is an updating |
517 | load, which means that the RA field may not be zero and may not |
518 | equal the RT field. */ |
519 | #define RAL RAQ + 1 |
520 | { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 }, |
521 | |
522 | /* The RA field in an lmw instruction, which has special value |
523 | restrictions. */ |
524 | #define RAM RAL + 1 |
525 | { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 }, |
526 | |
527 | /* The RA field in a D or X form instruction which is an updating |
528 | store or an updating floating point load, which means that the RA |
529 | field may not be zero. */ |
530 | #define RAS RAM + 1 |
531 | { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 }, |
532 | |
533 | /* The RA field of the tlbwe, dccci and iccci instructions, |
534 | which are optional. */ |
535 | #define RAOPT RAS + 1 |
536 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, |
537 | |
538 | /* The RB field in an X, XO, M, or MDS form instruction. */ |
539 | #define RB RAOPT + 1 |
540 | #define RB_MASK (0x1f << 11) |
541 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, |
542 | |
543 | /* The RB field in an X form instruction when it must be the same as |
544 | the RS field in the instruction. This is used for extended |
545 | mnemonics like mr. */ |
546 | #define RBS RB + 1 |
547 | { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, |
548 | |
549 | /* The RB field in an lswx instruction, which has special value |
550 | restrictions. */ |
551 | #define RBX RBS + 1 |
552 | { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR }, |
553 | |
554 | /* The RB field of the dccci and iccci instructions, which are optional. */ |
555 | #define RBOPT RBX + 1 |
556 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, |
557 | |
558 | /* The RC register field in an maddld, maddhd or maddhdu instruction. */ |
559 | #define RC RBOPT + 1 |
560 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR }, |
561 | |
562 | /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form |
563 | instruction or the RT field in a D, DS, X, XFX or XO form |
564 | instruction. */ |
565 | #define RS RC + 1 |
566 | #define RT RS |
567 | #define RT_MASK (0x1f << 21) |
568 | #define RD RS |
569 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, |
570 | |
571 | /* The RS and RT fields of the DS form stq and DQ form lq instructions, |
572 | which have special value restrictions. */ |
573 | #define RSQ RS + 1 |
574 | #define RTQ RSQ |
575 | { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR }, |
576 | |
577 | /* The RS field of the tlbwe instruction, which is optional. */ |
578 | #define RSO RSQ + 1 |
579 | #define RTO RSO |
580 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, |
581 | |
582 | /* The RX field of the SE_RR form instruction. */ |
583 | #define RX RSO + 1 |
584 | { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR }, |
585 | |
586 | /* The ARX field of the SE_RR form instruction. */ |
587 | #define ARX RX + 1 |
588 | { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR }, |
589 | |
590 | /* The RY field of the SE_RR form instruction. */ |
591 | #define RY ARX + 1 |
592 | #define RZ RY |
593 | { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR }, |
594 | |
595 | /* The ARY field of the SE_RR form instruction. */ |
596 | #define ARY RY + 1 |
597 | { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR }, |
598 | |
599 | /* The SCLSCI8 field in a D form instruction. */ |
600 | #define SCLSCI8 ARY + 1 |
601 | { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 }, |
602 | |
603 | /* The SCLSCI8N field in a D form instruction. This is the same as the |
604 | SCLSCI8 field, only negated. */ |
605 | #define SCLSCI8N SCLSCI8 + 1 |
606 | { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n, |
607 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
608 | |
609 | /* The SD field of the SD4 form instruction. */ |
610 | #define SE_SD SCLSCI8N + 1 |
611 | { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS }, |
612 | |
613 | /* The SD field of the SD4 form instruction, for halfword. */ |
614 | #define SE_SDH SE_SD + 1 |
615 | { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS }, |
616 | |
617 | /* The SD field of the SD4 form instruction, for word. */ |
618 | #define SE_SDW SE_SDH + 1 |
619 | { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS }, |
620 | |
621 | /* The SH field in an X or M form instruction. */ |
622 | #define SH SE_SDW + 1 |
623 | #define SH_MASK (0x1f << 11) |
624 | /* The other UIMM field in a EVX form instruction. */ |
625 | #define EVUIMM SH |
626 | /* The FC field in an atomic X form instruction. */ |
627 | #define FC SH |
628 | { 0x1f, 11, NULL, NULL, 0 }, |
629 | |
630 | /* The SI field in a HTM X form instruction. */ |
631 | #define HTM_SI SH + 1 |
632 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED }, |
633 | |
634 | /* The SH field in an MD form instruction. This is split. */ |
635 | #define SH6 HTM_SI + 1 |
636 | #define SH6_MASK ((0x1f << 11) | (1 << 1)) |
637 | { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 }, |
638 | |
639 | /* The SH field of the tlbwe instruction, which is optional. */ |
640 | #define SHO SH6 + 1 |
641 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
642 | |
643 | /* The SI field in a D form instruction. */ |
644 | #define SI SHO + 1 |
645 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, |
646 | |
647 | /* The SI field in a D form instruction when we accept a wide range |
648 | of positive values. */ |
649 | #define SISIGNOPT SI + 1 |
650 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
651 | |
652 | /* The SI8 field in a D form instruction. */ |
653 | #define SI8 SISIGNOPT + 1 |
654 | { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, |
655 | |
656 | /* The SPR field in an XFX form instruction. This is flipped--the |
657 | lower 5 bits are stored in the upper 5 and vice- versa. */ |
658 | #define SPR SI8 + 1 |
659 | #define PMR SPR |
660 | #define TMR SPR |
661 | #define SPR_MASK (0x3ff << 11) |
662 | { 0x3ff, 11, insert_spr, extract_spr, 0 }, |
663 | |
664 | /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ |
665 | #define SPRBAT SPR + 1 |
666 | #define SPRBAT_MASK (0x3 << 17) |
667 | { 0x3, 17, NULL, NULL, 0 }, |
668 | |
669 | /* The SPRG register number in an XFX form m[ft]sprg instruction. */ |
670 | #define SPRG SPRBAT + 1 |
671 | { 0x1f, 16, insert_sprg, extract_sprg, 0 }, |
672 | |
673 | /* The SR field in an X form instruction. */ |
674 | #define SR SPRG + 1 |
675 | /* The 4-bit UIMM field in a VX form instruction. */ |
676 | #define UIMM4 SR |
677 | { 0xf, 16, NULL, NULL, 0 }, |
678 | |
679 | /* The STRM field in an X AltiVec form instruction. */ |
680 | #define STRM SR + 1 |
681 | /* The T field in a tlbilx form instruction. */ |
682 | #define T STRM |
683 | /* The L field in wclr instructions. */ |
684 | #define L2 STRM |
685 | { 0x3, 21, NULL, NULL, 0 }, |
686 | |
687 | /* The ESYNC field in an X (sync) form instruction. */ |
688 | #define ESYNC STRM + 1 |
689 | { 0xf, 16, insert_esync, NULL, PPC_OPERAND_OPTIONAL }, |
690 | |
691 | /* The SV field in a POWER SC form instruction. */ |
692 | #define SV ESYNC + 1 |
693 | { 0x3fff, 2, NULL, NULL, 0 }, |
694 | |
695 | /* The TBR field in an XFX form instruction. This is like the SPR |
696 | field, but it is optional. */ |
697 | #define TBR SV + 1 |
698 | { 0x3ff, 11, insert_tbr, extract_tbr, |
699 | PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, |
700 | /* If the TBR operand is ommitted, use the value 268. */ |
701 | { -1, 268, NULL, NULL, 0}, |
702 | |
703 | /* The TO field in a D or X form instruction. */ |
704 | #define TO TBR + 2 |
705 | #define DUI TO |
706 | #define TO_MASK (0x1f << 21) |
707 | { 0x1f, 21, NULL, NULL, 0 }, |
708 | |
709 | /* The UI field in a D form instruction. */ |
710 | #define UI TO + 1 |
711 | { 0xffff, 0, NULL, NULL, 0 }, |
712 | |
713 | #define UISIGNOPT UI + 1 |
714 | { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT }, |
715 | |
716 | /* The IMM field in an SE_IM5 instruction. */ |
717 | #define UI5 UISIGNOPT + 1 |
718 | { 0x1f, 4, NULL, NULL, 0 }, |
719 | |
720 | /* The OIMM field in an SE_OIM5 instruction. */ |
721 | #define OIMM5 UI5 + 1 |
722 | { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 }, |
723 | |
724 | /* The UI7 field in an SE_LI instruction. */ |
725 | #define UI7 OIMM5 + 1 |
726 | { 0x7f, 4, NULL, NULL, 0 }, |
727 | |
728 | /* The VA field in a VA, VX or VXR form instruction. */ |
729 | #define VA UI7 + 1 |
730 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, |
731 | |
732 | /* The VB field in a VA, VX or VXR form instruction. */ |
733 | #define VB VA + 1 |
734 | { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, |
735 | |
736 | /* The VC field in a VA form instruction. */ |
737 | #define VC VB + 1 |
738 | { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, |
739 | |
740 | /* The VD or VS field in a VA, VX, VXR or X form instruction. */ |
741 | #define VD VC + 1 |
742 | #define VS VD |
743 | { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, |
744 | |
745 | /* The SIMM field in a VX form instruction, and TE in Z form. */ |
746 | #define SIMM VD + 1 |
747 | #define TE SIMM |
748 | { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, |
749 | |
750 | /* The UIMM field in a VX form instruction. */ |
751 | #define UIMM SIMM + 1 |
752 | #define DCTL UIMM |
753 | { 0x1f, 16, NULL, NULL, 0 }, |
754 | |
755 | /* The 3-bit UIMM field in a VX form instruction. */ |
756 | #define UIMM3 UIMM + 1 |
757 | { 0x7, 16, NULL, NULL, 0 }, |
758 | |
759 | /* The 6-bit UIM field in a X form instruction. */ |
760 | #define UIM6 UIMM3 + 1 |
761 | { 0x3f, 16, NULL, NULL, 0 }, |
762 | |
763 | /* The SIX field in a VX form instruction. */ |
764 | #define SIX UIM6 + 1 |
765 | { 0xf, 11, NULL, NULL, 0 }, |
766 | |
767 | /* The PS field in a VX form instruction. */ |
768 | #define PS SIX + 1 |
769 | { 0x1, 9, NULL, NULL, 0 }, |
770 | |
771 | /* The SHB field in a VA form instruction. */ |
772 | #define SHB PS + 1 |
773 | { 0xf, 6, NULL, NULL, 0 }, |
774 | |
775 | /* The other UIMM field in a half word EVX form instruction. */ |
776 | #define EVUIMM_2 SHB + 1 |
777 | { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, |
778 | |
779 | /* The other UIMM field in a word EVX form instruction. */ |
780 | #define EVUIMM_4 EVUIMM_2 + 1 |
781 | { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, |
782 | |
783 | /* The other UIMM field in a double EVX form instruction. */ |
784 | #define EVUIMM_8 EVUIMM_4 + 1 |
785 | { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, |
786 | |
787 | /* The WS or DRM field in an X form instruction. */ |
788 | #define WS EVUIMM_8 + 1 |
789 | #define DRM WS |
790 | { 0x7, 11, NULL, NULL, 0 }, |
791 | |
792 | /* PowerPC paired singles extensions. */ |
793 | /* W bit in the pair singles instructions for x type instructions. */ |
794 | #define PSWM WS + 1 |
795 | /* The BO16 field in a BD8 form instruction. */ |
796 | #define BO16 PSWM |
797 | { 0x1, 10, 0, 0, 0 }, |
798 | |
799 | /* IDX bits for quantization in the pair singles instructions. */ |
800 | #define PSQ PSWM + 1 |
801 | { 0x7, 12, 0, 0, 0 }, |
802 | |
803 | /* IDX bits for quantization in the pair singles x-type instructions. */ |
804 | #define PSQM PSQ + 1 |
805 | { 0x7, 7, 0, 0, 0 }, |
806 | |
807 | /* Smaller D field for quantization in the pair singles instructions. */ |
808 | #define PSD PSQM + 1 |
809 | { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
810 | |
811 | /* The L field in an mtmsrd or A form instruction or R or W in an X form. */ |
812 | #define A_L PSD + 1 |
813 | #define W A_L |
814 | #define X_R A_L |
815 | { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
816 | |
817 | /* The RMC or CY field in a Z23 form instruction. */ |
818 | #define RMC A_L + 1 |
819 | #define CY RMC |
820 | { 0x3, 9, NULL, NULL, 0 }, |
821 | |
822 | #define R RMC + 1 |
823 | { 0x1, 16, NULL, NULL, 0 }, |
824 | |
825 | #define RIC R + 1 |
826 | { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
827 | |
828 | #define PRS RIC + 1 |
829 | { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
830 | |
831 | #define SP PRS + 1 |
832 | { 0x3, 19, NULL, NULL, 0 }, |
833 | |
834 | #define S SP + 1 |
835 | { 0x1, 20, NULL, NULL, 0 }, |
836 | |
837 | /* The S field in a XL form instruction. */ |
838 | #define SXL S + 1 |
839 | { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, |
840 | /* If the SXL operand is ommitted, use the value 1. */ |
841 | { -1, 1, NULL, NULL, 0}, |
842 | |
843 | /* SH field starting at bit position 16. */ |
844 | #define SH16 SXL + 2 |
845 | /* The DCM and DGM fields in a Z form instruction. */ |
846 | #define DCM SH16 |
847 | #define DGM DCM |
848 | { 0x3f, 10, NULL, NULL, 0 }, |
849 | |
850 | /* The EH field in larx instruction. */ |
851 | #define EH SH16 + 1 |
852 | { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
853 | |
854 | /* The L field in an mtfsf or XFL form instruction. */ |
855 | /* The A field in a HTM X form instruction. */ |
856 | #define XFL_L EH + 1 |
857 | #define HTM_A XFL_L |
858 | { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, |
859 | |
860 | /* Xilinx APU related masks and macros */ |
861 | #define FCRT XFL_L + 1 |
862 | #define FCRT_MASK (0x1f << 21) |
863 | { 0x1f, 21, 0, 0, PPC_OPERAND_FCR }, |
864 | |
865 | /* Xilinx FSL related masks and macros */ |
866 | #define FSL FCRT + 1 |
867 | #define FSL_MASK (0x1f << 11) |
868 | { 0x1f, 11, 0, 0, PPC_OPERAND_FSL }, |
869 | |
870 | /* Xilinx UDI related masks and macros */ |
871 | #define URT FSL + 1 |
872 | { 0x1f, 21, 0, 0, PPC_OPERAND_UDI }, |
873 | |
874 | #define URA URT + 1 |
875 | { 0x1f, 16, 0, 0, PPC_OPERAND_UDI }, |
876 | |
877 | #define URB URA + 1 |
878 | { 0x1f, 11, 0, 0, PPC_OPERAND_UDI }, |
879 | |
880 | #define URC URB + 1 |
881 | { 0x1f, 6, 0, 0, PPC_OPERAND_UDI }, |
882 | |
883 | /* The VLESIMM field in a D form instruction. */ |
884 | #define VLESIMM URC + 1 |
885 | { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi, |
886 | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
887 | |
888 | /* The VLENSIMM field in a D form instruction. */ |
889 | #define VLENSIMM VLESIMM + 1 |
890 | { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi, |
891 | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
892 | |
893 | /* The VLEUIMM field in a D form instruction. */ |
894 | #define VLEUIMM VLENSIMM + 1 |
895 | { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 }, |
896 | |
897 | /* The VLEUIMML field in a D form instruction. */ |
898 | #define VLEUIMML VLEUIMM + 1 |
899 | { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 }, |
900 | |
901 | /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ |
902 | #define XS6 VLEUIMML + 1 |
903 | #define XT6 XS6 |
904 | { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR }, |
905 | |
906 | /* The XT and XS fields in an DQ form VSX instruction. This is split. */ |
907 | #define XSQ6 XT6 + 1 |
908 | #define XTQ6 XSQ6 |
909 | { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR }, |
910 | |
911 | /* The XA field in an XX3 form instruction. This is split. */ |
912 | #define XA6 XTQ6 + 1 |
913 | { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR }, |
914 | |
915 | /* The XB field in an XX2 or XX3 form instruction. This is split. */ |
916 | #define XB6 XA6 + 1 |
917 | { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR }, |
918 | |
919 | /* The XB field in an XX3 form instruction when it must be the same as |
920 | the XA field in the instruction. This is used in extended mnemonics |
921 | like xvmovdp. This is split. */ |
922 | #define XB6S XB6 + 1 |
923 | { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE }, |
924 | |
925 | /* The XC field in an XX4 form instruction. This is split. */ |
926 | #define XC6 XB6S + 1 |
927 | { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR }, |
928 | |
929 | /* The DM or SHW field in an XX3 form instruction. */ |
930 | #define DM XC6 + 1 |
931 | #define SHW DM |
932 | { 0x3, 8, NULL, NULL, 0 }, |
933 | |
934 | /* The DM field in an extended mnemonic XX3 form instruction. */ |
935 | #define DMEX DM + 1 |
936 | { 0x3, 8, insert_dm, extract_dm, 0 }, |
937 | |
938 | /* The UIM field in an XX2 form instruction. */ |
939 | #define UIM DMEX + 1 |
940 | /* The 2-bit UIMM field in a VX form instruction. */ |
941 | #define UIMM2 UIM |
942 | /* The 2-bit L field in a darn instruction. */ |
943 | #define LRAND UIM |
944 | { 0x3, 16, NULL, NULL, 0 }, |
945 | |
946 | #define ERAT_T UIM + 1 |
947 | { 0x7, 21, NULL, NULL, 0 }, |
948 | |
949 | #define IH ERAT_T + 1 |
950 | { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
951 | |
952 | /* The 8-bit IMM8 field in a XX1 form instruction. */ |
953 | #define IMM8 IH + 1 |
954 | { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT }, |
955 | }; |
956 | |
957 | const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) |
958 | / sizeof (powerpc_operands[0])); |
959 | |
960 | /* The functions used to insert and extract complicated operands. */ |
961 | |
962 | /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */ |
963 | |
964 | static unsigned long |
965 | insert_arx (unsigned long insn, |
966 | long value, |
967 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
968 | const char **errmsg ATTRIBUTE_UNUSED) |
969 | { |
970 | if (value >= 8 && value < 24) |
971 | return insn | ((value - 8) & 0xf); |
972 | else |
973 | { |
974 | *errmsg = _("invalid register" ); |
975 | return 0; |
976 | } |
977 | } |
978 | |
979 | static long |
980 | (unsigned long insn, |
981 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
982 | int *invalid ATTRIBUTE_UNUSED) |
983 | { |
984 | return (insn & 0xf) + 8; |
985 | } |
986 | |
987 | static unsigned long |
988 | insert_ary (unsigned long insn, |
989 | long value, |
990 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
991 | const char **errmsg ATTRIBUTE_UNUSED) |
992 | { |
993 | if (value >= 8 && value < 24) |
994 | return insn | (((value - 8) & 0xf) << 4); |
995 | else |
996 | { |
997 | *errmsg = _("invalid register" ); |
998 | return 0; |
999 | } |
1000 | } |
1001 | |
1002 | static long |
1003 | (unsigned long insn, |
1004 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1005 | int *invalid ATTRIBUTE_UNUSED) |
1006 | { |
1007 | return ((insn >> 4) & 0xf) + 8; |
1008 | } |
1009 | |
1010 | static unsigned long |
1011 | insert_rx (unsigned long insn, |
1012 | long value, |
1013 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1014 | const char **errmsg) |
1015 | { |
1016 | if (value >= 0 && value < 8) |
1017 | return insn | value; |
1018 | else if (value >= 24 && value <= 31) |
1019 | return insn | (value - 16); |
1020 | else |
1021 | { |
1022 | *errmsg = _("invalid register" ); |
1023 | return 0; |
1024 | } |
1025 | } |
1026 | |
1027 | static long |
1028 | (unsigned long insn, |
1029 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1030 | int *invalid ATTRIBUTE_UNUSED) |
1031 | { |
1032 | int value = insn & 0xf; |
1033 | if (value >= 0 && value < 8) |
1034 | return value; |
1035 | else |
1036 | return value + 16; |
1037 | } |
1038 | |
1039 | static unsigned long |
1040 | insert_ry (unsigned long insn, |
1041 | long value, |
1042 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1043 | const char **errmsg) |
1044 | { |
1045 | if (value >= 0 && value < 8) |
1046 | return insn | (value << 4); |
1047 | else if (value >= 24 && value <= 31) |
1048 | return insn | ((value - 16) << 4); |
1049 | else |
1050 | { |
1051 | *errmsg = _("invalid register" ); |
1052 | return 0; |
1053 | } |
1054 | } |
1055 | |
1056 | static long |
1057 | (unsigned long insn, |
1058 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1059 | int *invalid ATTRIBUTE_UNUSED) |
1060 | { |
1061 | int value = (insn >> 4) & 0xf; |
1062 | if (value >= 0 && value < 8) |
1063 | return value; |
1064 | else |
1065 | return value + 16; |
1066 | } |
1067 | |
1068 | /* The BA field in an XL form instruction when it must be the same as |
1069 | the BT field in the same instruction. This operand is marked FAKE. |
1070 | The insertion function just copies the BT field into the BA field, |
1071 | and the extraction function just checks that the fields are the |
1072 | same. */ |
1073 | |
1074 | static unsigned long |
1075 | insert_bat (unsigned long insn, |
1076 | long value ATTRIBUTE_UNUSED, |
1077 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1078 | const char **errmsg ATTRIBUTE_UNUSED) |
1079 | { |
1080 | return insn | (((insn >> 21) & 0x1f) << 16); |
1081 | } |
1082 | |
1083 | static long |
1084 | (unsigned long insn, |
1085 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1086 | int *invalid) |
1087 | { |
1088 | if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) |
1089 | *invalid = 1; |
1090 | return 0; |
1091 | } |
1092 | |
1093 | /* The BB field in an XL form instruction when it must be the same as |
1094 | the BA field in the same instruction. This operand is marked FAKE. |
1095 | The insertion function just copies the BA field into the BB field, |
1096 | and the extraction function just checks that the fields are the |
1097 | same. */ |
1098 | |
1099 | static unsigned long |
1100 | insert_bba (unsigned long insn, |
1101 | long value ATTRIBUTE_UNUSED, |
1102 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1103 | const char **errmsg ATTRIBUTE_UNUSED) |
1104 | { |
1105 | return insn | (((insn >> 16) & 0x1f) << 11); |
1106 | } |
1107 | |
1108 | static long |
1109 | (unsigned long insn, |
1110 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1111 | int *invalid) |
1112 | { |
1113 | if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) |
1114 | *invalid = 1; |
1115 | return 0; |
1116 | } |
1117 | |
1118 | /* The BD field in a B form instruction when the - modifier is used. |
1119 | This modifier means that the branch is not expected to be taken. |
1120 | For chips built to versions of the architecture prior to version 2 |
1121 | (ie. not Power4 compatible), we set the y bit of the BO field to 1 |
1122 | if the offset is negative. When extracting, we require that the y |
1123 | bit be 1 and that the offset be positive, since if the y bit is 0 |
1124 | we just want to print the normal form of the instruction. |
1125 | Power4 compatible targets use two bits, "a", and "t", instead of |
1126 | the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, |
1127 | "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 |
1128 | in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 |
1129 | for branch on CTR. We only handle the taken/not-taken hint here. |
1130 | Note that we don't relax the conditions tested here when |
1131 | disassembling with -Many because insns using extract_bdm and |
1132 | extract_bdp always occur in pairs. One or the other will always |
1133 | be valid. */ |
1134 | |
1135 | #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) |
1136 | |
1137 | static unsigned long |
1138 | insert_bdm (unsigned long insn, |
1139 | long value, |
1140 | ppc_cpu_t dialect, |
1141 | const char **errmsg ATTRIBUTE_UNUSED) |
1142 | { |
1143 | if ((dialect & ISA_V2) == 0) |
1144 | { |
1145 | if ((value & 0x8000) != 0) |
1146 | insn |= 1 << 21; |
1147 | } |
1148 | else |
1149 | { |
1150 | if ((insn & (0x14 << 21)) == (0x04 << 21)) |
1151 | insn |= 0x02 << 21; |
1152 | else if ((insn & (0x14 << 21)) == (0x10 << 21)) |
1153 | insn |= 0x08 << 21; |
1154 | } |
1155 | return insn | (value & 0xfffc); |
1156 | } |
1157 | |
1158 | static long |
1159 | (unsigned long insn, |
1160 | ppc_cpu_t dialect, |
1161 | int *invalid) |
1162 | { |
1163 | if ((dialect & ISA_V2) == 0) |
1164 | { |
1165 | if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) |
1166 | *invalid = 1; |
1167 | } |
1168 | else |
1169 | { |
1170 | if ((insn & (0x17 << 21)) != (0x06 << 21) |
1171 | && (insn & (0x1d << 21)) != (0x18 << 21)) |
1172 | *invalid = 1; |
1173 | } |
1174 | |
1175 | return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
1176 | } |
1177 | |
1178 | /* The BD field in a B form instruction when the + modifier is used. |
1179 | This is like BDM, above, except that the branch is expected to be |
1180 | taken. */ |
1181 | |
1182 | static unsigned long |
1183 | insert_bdp (unsigned long insn, |
1184 | long value, |
1185 | ppc_cpu_t dialect, |
1186 | const char **errmsg ATTRIBUTE_UNUSED) |
1187 | { |
1188 | if ((dialect & ISA_V2) == 0) |
1189 | { |
1190 | if ((value & 0x8000) == 0) |
1191 | insn |= 1 << 21; |
1192 | } |
1193 | else |
1194 | { |
1195 | if ((insn & (0x14 << 21)) == (0x04 << 21)) |
1196 | insn |= 0x03 << 21; |
1197 | else if ((insn & (0x14 << 21)) == (0x10 << 21)) |
1198 | insn |= 0x09 << 21; |
1199 | } |
1200 | return insn | (value & 0xfffc); |
1201 | } |
1202 | |
1203 | static long |
1204 | (unsigned long insn, |
1205 | ppc_cpu_t dialect, |
1206 | int *invalid) |
1207 | { |
1208 | if ((dialect & ISA_V2) == 0) |
1209 | { |
1210 | if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) |
1211 | *invalid = 1; |
1212 | } |
1213 | else |
1214 | { |
1215 | if ((insn & (0x17 << 21)) != (0x07 << 21) |
1216 | && (insn & (0x1d << 21)) != (0x19 << 21)) |
1217 | *invalid = 1; |
1218 | } |
1219 | |
1220 | return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
1221 | } |
1222 | |
1223 | static inline int |
1224 | valid_bo_pre_v2 (long value) |
1225 | { |
1226 | /* Certain encodings have bits that are required to be zero. |
1227 | These are (z must be zero, y may be anything): |
1228 | 0000y |
1229 | 0001y |
1230 | 001zy |
1231 | 0100y |
1232 | 0101y |
1233 | 011zy |
1234 | 1z00y |
1235 | 1z01y |
1236 | 1z1zz |
1237 | */ |
1238 | if ((value & 0x14) == 0) |
1239 | return 1; |
1240 | else if ((value & 0x14) == 0x4) |
1241 | return (value & 0x2) == 0; |
1242 | else if ((value & 0x14) == 0x10) |
1243 | return (value & 0x8) == 0; |
1244 | else |
1245 | return value == 0x14; |
1246 | } |
1247 | |
1248 | static inline int |
1249 | valid_bo_post_v2 (long value) |
1250 | { |
1251 | /* Certain encodings have bits that are required to be zero. |
1252 | These are (z must be zero, a & t may be anything): |
1253 | 0000z |
1254 | 0001z |
1255 | 001at |
1256 | 0100z |
1257 | 0101z |
1258 | 011at |
1259 | 1a00t |
1260 | 1a01t |
1261 | 1z1zz |
1262 | */ |
1263 | if ((value & 0x14) == 0) |
1264 | return (value & 0x1) == 0; |
1265 | else if ((value & 0x14) == 0x14) |
1266 | return value == 0x14; |
1267 | else |
1268 | return 1; |
1269 | } |
1270 | |
1271 | /* Check for legal values of a BO field. */ |
1272 | |
1273 | static int |
1274 | valid_bo (long value, ppc_cpu_t dialect, int ) |
1275 | { |
1276 | int valid_y = valid_bo_pre_v2 (value); |
1277 | int valid_at = valid_bo_post_v2 (value); |
1278 | |
1279 | /* When disassembling with -Many, accept either encoding on the |
1280 | second pass through opcodes. */ |
1281 | if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY) |
1282 | return valid_y || valid_at; |
1283 | if ((dialect & ISA_V2) == 0) |
1284 | return valid_y; |
1285 | else |
1286 | return valid_at; |
1287 | } |
1288 | |
1289 | /* The BO field in a B form instruction. Warn about attempts to set |
1290 | the field to an illegal value. */ |
1291 | |
1292 | static unsigned long |
1293 | insert_bo (unsigned long insn, |
1294 | long value, |
1295 | ppc_cpu_t dialect, |
1296 | const char **errmsg) |
1297 | { |
1298 | if (!valid_bo (value, dialect, extract: 0)) |
1299 | *errmsg = _("invalid conditional option" ); |
1300 | else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) |
1301 | *errmsg = _("invalid counter access" ); |
1302 | return insn | ((value & 0x1f) << 21); |
1303 | } |
1304 | |
1305 | static long |
1306 | (unsigned long insn, |
1307 | ppc_cpu_t dialect, |
1308 | int *invalid) |
1309 | { |
1310 | long value; |
1311 | |
1312 | value = (insn >> 21) & 0x1f; |
1313 | if (!valid_bo (value, dialect, extract: 1)) |
1314 | *invalid = 1; |
1315 | return value; |
1316 | } |
1317 | |
1318 | /* The BO field in a B form instruction when the + or - modifier is |
1319 | used. This is like the BO field, but it must be even. When |
1320 | extracting it, we force it to be even. */ |
1321 | |
1322 | static unsigned long |
1323 | insert_boe (unsigned long insn, |
1324 | long value, |
1325 | ppc_cpu_t dialect, |
1326 | const char **errmsg) |
1327 | { |
1328 | if (!valid_bo (value, dialect, extract: 0)) |
1329 | *errmsg = _("invalid conditional option" ); |
1330 | else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) |
1331 | *errmsg = _("invalid counter access" ); |
1332 | else if ((value & 1) != 0) |
1333 | *errmsg = _("attempt to set y bit when using + or - modifier" ); |
1334 | |
1335 | return insn | ((value & 0x1f) << 21); |
1336 | } |
1337 | |
1338 | static long |
1339 | (unsigned long insn, |
1340 | ppc_cpu_t dialect, |
1341 | int *invalid) |
1342 | { |
1343 | long value; |
1344 | |
1345 | value = (insn >> 21) & 0x1f; |
1346 | if (!valid_bo (value, dialect, extract: 1)) |
1347 | *invalid = 1; |
1348 | return value & 0x1e; |
1349 | } |
1350 | |
1351 | /* The DCMX field in a X form instruction when the field is split |
1352 | into separate DC, DM and DX fields. */ |
1353 | |
1354 | static unsigned long |
1355 | insert_dcmxs (unsigned long insn, |
1356 | long value, |
1357 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1358 | const char **errmsg ATTRIBUTE_UNUSED) |
1359 | { |
1360 | return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40); |
1361 | } |
1362 | |
1363 | static long |
1364 | (unsigned long insn, |
1365 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1366 | int *invalid ATTRIBUTE_UNUSED) |
1367 | { |
1368 | return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); |
1369 | } |
1370 | |
1371 | /* The D field in a DX form instruction when the field is split |
1372 | into separate D0, D1 and D2 fields. */ |
1373 | |
1374 | static unsigned long |
1375 | insert_dxd (unsigned long insn, |
1376 | long value, |
1377 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1378 | const char **errmsg ATTRIBUTE_UNUSED) |
1379 | { |
1380 | return insn | (value & 0xffc1) | ((value & 0x3e) << 15); |
1381 | } |
1382 | |
1383 | static long |
1384 | (unsigned long insn, |
1385 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1386 | int *invalid ATTRIBUTE_UNUSED) |
1387 | { |
1388 | unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e); |
1389 | return (dxd ^ 0x8000) - 0x8000; |
1390 | } |
1391 | |
1392 | static unsigned long |
1393 | insert_dxdn (unsigned long insn, |
1394 | long value, |
1395 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1396 | const char **errmsg ATTRIBUTE_UNUSED) |
1397 | { |
1398 | return insert_dxd (insn, value: -value, dialect, errmsg); |
1399 | } |
1400 | |
1401 | static long |
1402 | (unsigned long insn, |
1403 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1404 | int *invalid ATTRIBUTE_UNUSED) |
1405 | { |
1406 | return -extract_dxd (insn, dialect, invalid); |
1407 | } |
1408 | |
1409 | /* FXM mask in mfcr and mtcrf instructions. */ |
1410 | |
1411 | static unsigned long |
1412 | insert_fxm (unsigned long insn, |
1413 | long value, |
1414 | ppc_cpu_t dialect, |
1415 | const char **errmsg) |
1416 | { |
1417 | /* If we're handling the mfocrf and mtocrf insns ensure that exactly |
1418 | one bit of the mask field is set. */ |
1419 | if ((insn & (1 << 20)) != 0) |
1420 | { |
1421 | if (value == 0 || (value & -value) != value) |
1422 | { |
1423 | *errmsg = _("invalid mask field" ); |
1424 | value = 0; |
1425 | } |
1426 | } |
1427 | |
1428 | /* If only one bit of the FXM field is set, we can use the new form |
1429 | of the instruction, which is faster. Unlike the Power4 branch hint |
1430 | encoding, this is not backward compatible. Do not generate the |
1431 | new form unless -mpower4 has been given, or -many and the two |
1432 | operand form of mfcr was used. */ |
1433 | else if (value > 0 |
1434 | && (value & -value) == value |
1435 | && ((dialect & PPC_OPCODE_POWER4) != 0 |
1436 | || ((dialect & PPC_OPCODE_ANY) != 0 |
1437 | && (insn & (0x3ff << 1)) == 19 << 1))) |
1438 | insn |= 1 << 20; |
1439 | |
1440 | /* Any other value on mfcr is an error. */ |
1441 | else if ((insn & (0x3ff << 1)) == 19 << 1) |
1442 | { |
1443 | /* A value of -1 means we used the one operand form of |
1444 | mfcr which is valid. */ |
1445 | if (value != -1) |
1446 | *errmsg = _("invalid mfcr mask" ); |
1447 | value = 0; |
1448 | } |
1449 | |
1450 | return insn | ((value & 0xff) << 12); |
1451 | } |
1452 | |
1453 | static long |
1454 | (unsigned long insn, |
1455 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1456 | int *invalid) |
1457 | { |
1458 | long mask = (insn >> 12) & 0xff; |
1459 | |
1460 | /* Is this a Power4 insn? */ |
1461 | if ((insn & (1 << 20)) != 0) |
1462 | { |
1463 | /* Exactly one bit of MASK should be set. */ |
1464 | if (mask == 0 || (mask & -mask) != mask) |
1465 | *invalid = 1; |
1466 | } |
1467 | |
1468 | /* Check that non-power4 form of mfcr has a zero MASK. */ |
1469 | else if ((insn & (0x3ff << 1)) == 19 << 1) |
1470 | { |
1471 | if (mask != 0) |
1472 | *invalid = 1; |
1473 | else |
1474 | mask = -1; |
1475 | } |
1476 | |
1477 | return mask; |
1478 | } |
1479 | |
1480 | static unsigned long |
1481 | insert_li20 (unsigned long insn, |
1482 | long value, |
1483 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1484 | const char **errmsg ATTRIBUTE_UNUSED) |
1485 | { |
1486 | return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff); |
1487 | } |
1488 | |
1489 | static long |
1490 | (unsigned long insn, |
1491 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1492 | int *invalid ATTRIBUTE_UNUSED) |
1493 | { |
1494 | long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000; |
1495 | |
1496 | return ext |
1497 | | (((insn >> 11) & 0xf) << 16) |
1498 | | (((insn >> 17) & 0xf) << 12) |
1499 | | (((insn >> 16) & 0x1) << 11) |
1500 | | (insn & 0x7ff); |
1501 | } |
1502 | |
1503 | /* The 2-bit L field in a SYNC or WC field in a WAIT instruction. |
1504 | For SYNC, some L values are reserved: |
1505 | * Value 3 is reserved on newer server cpus. |
1506 | * Values 2 and 3 are reserved on all other cpus. */ |
1507 | |
1508 | static unsigned long |
1509 | insert_ls (unsigned long insn, |
1510 | long value, |
1511 | ppc_cpu_t dialect, |
1512 | const char **errmsg) |
1513 | { |
1514 | /* For SYNC, some L values are illegal. */ |
1515 | if (((insn >> 1) & 0x3ff) == 598) |
1516 | { |
1517 | long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1; |
1518 | if (value > max_lvalue) |
1519 | { |
1520 | *errmsg = _("illegal L operand value" ); |
1521 | return insn; |
1522 | } |
1523 | } |
1524 | |
1525 | return insn | ((value & 0x3) << 21); |
1526 | } |
1527 | |
1528 | /* The 4-bit E field in a sync instruction that accepts 2 operands. |
1529 | If ESYNC is non-zero, then the L field must be either 0 or 1 and |
1530 | the complement of ESYNC-bit2. */ |
1531 | |
1532 | static unsigned long |
1533 | insert_esync (unsigned long insn, |
1534 | long value, |
1535 | ppc_cpu_t dialect, |
1536 | const char **errmsg) |
1537 | { |
1538 | unsigned long ls = (insn >> 21) & 0x03; |
1539 | |
1540 | if (value == 0) |
1541 | { |
1542 | if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1) |
1543 | || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2)) |
1544 | *errmsg = _("illegal L operand value" ); |
1545 | return insn; |
1546 | } |
1547 | |
1548 | if ((ls & ~0x1) |
1549 | || (((value >> 1) & 0x1) ^ ls) == 0) |
1550 | *errmsg = _("incompatible L operand value" ); |
1551 | |
1552 | return insn | ((value & 0xf) << 16); |
1553 | } |
1554 | |
1555 | /* The MB and ME fields in an M form instruction expressed as a single |
1556 | operand which is itself a bitmask. The extraction function always |
1557 | marks it as invalid, since we never want to recognize an |
1558 | instruction which uses a field of this type. */ |
1559 | |
1560 | static unsigned long |
1561 | insert_mbe (unsigned long insn, |
1562 | long value, |
1563 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1564 | const char **errmsg) |
1565 | { |
1566 | unsigned long uval, mask; |
1567 | int mb, me, mx, count, last; |
1568 | |
1569 | uval = value; |
1570 | |
1571 | if (uval == 0) |
1572 | { |
1573 | *errmsg = _("illegal bitmask" ); |
1574 | return insn; |
1575 | } |
1576 | |
1577 | mb = 0; |
1578 | me = 32; |
1579 | if ((uval & 1) != 0) |
1580 | last = 1; |
1581 | else |
1582 | last = 0; |
1583 | count = 0; |
1584 | |
1585 | /* mb: location of last 0->1 transition */ |
1586 | /* me: location of last 1->0 transition */ |
1587 | /* count: # transitions */ |
1588 | |
1589 | for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) |
1590 | { |
1591 | if ((uval & mask) && !last) |
1592 | { |
1593 | ++count; |
1594 | mb = mx; |
1595 | last = 1; |
1596 | } |
1597 | else if (!(uval & mask) && last) |
1598 | { |
1599 | ++count; |
1600 | me = mx; |
1601 | last = 0; |
1602 | } |
1603 | } |
1604 | if (me == 0) |
1605 | me = 32; |
1606 | |
1607 | if (count != 2 && (count != 0 || ! last)) |
1608 | *errmsg = _("illegal bitmask" ); |
1609 | |
1610 | return insn | (mb << 6) | ((me - 1) << 1); |
1611 | } |
1612 | |
1613 | static long |
1614 | (unsigned long insn, |
1615 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1616 | int *invalid) |
1617 | { |
1618 | long ret; |
1619 | int mb, me; |
1620 | int i; |
1621 | |
1622 | *invalid = 1; |
1623 | |
1624 | mb = (insn >> 6) & 0x1f; |
1625 | me = (insn >> 1) & 0x1f; |
1626 | if (mb < me + 1) |
1627 | { |
1628 | ret = 0; |
1629 | for (i = mb; i <= me; i++) |
1630 | ret |= 1L << (31 - i); |
1631 | } |
1632 | else if (mb == me + 1) |
1633 | ret = ~0; |
1634 | else /* (mb > me + 1) */ |
1635 | { |
1636 | ret = ~0; |
1637 | for (i = me + 1; i < mb; i++) |
1638 | ret &= ~(1L << (31 - i)); |
1639 | } |
1640 | return ret; |
1641 | } |
1642 | |
1643 | /* The MB or ME field in an MD or MDS form instruction. The high bit |
1644 | is wrapped to the low end. */ |
1645 | |
1646 | static unsigned long |
1647 | insert_mb6 (unsigned long insn, |
1648 | long value, |
1649 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1650 | const char **errmsg ATTRIBUTE_UNUSED) |
1651 | { |
1652 | return insn | ((value & 0x1f) << 6) | (value & 0x20); |
1653 | } |
1654 | |
1655 | static long |
1656 | (unsigned long insn, |
1657 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1658 | int *invalid ATTRIBUTE_UNUSED) |
1659 | { |
1660 | return ((insn >> 6) & 0x1f) | (insn & 0x20); |
1661 | } |
1662 | |
1663 | /* The NB field in an X form instruction. The value 32 is stored as |
1664 | 0. */ |
1665 | |
1666 | static long |
1667 | (unsigned long insn, |
1668 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1669 | int *invalid ATTRIBUTE_UNUSED) |
1670 | { |
1671 | long ret; |
1672 | |
1673 | ret = (insn >> 11) & 0x1f; |
1674 | if (ret == 0) |
1675 | ret = 32; |
1676 | return ret; |
1677 | } |
1678 | |
1679 | /* The NB field in an lswi instruction, which has special value |
1680 | restrictions. The value 32 is stored as 0. */ |
1681 | |
1682 | static unsigned long |
1683 | insert_nbi (unsigned long insn, |
1684 | long value, |
1685 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1686 | const char **errmsg ATTRIBUTE_UNUSED) |
1687 | { |
1688 | long rtvalue = (insn & RT_MASK) >> 21; |
1689 | long ravalue = (insn & RA_MASK) >> 16; |
1690 | |
1691 | if (value == 0) |
1692 | value = 32; |
1693 | if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32 |
1694 | : ravalue)) |
1695 | *errmsg = _("address register in load range" ); |
1696 | return insn | ((value & 0x1f) << 11); |
1697 | } |
1698 | |
1699 | /* The NSI field in a D form instruction. This is the same as the SI |
1700 | field, only negated. The extraction function always marks it as |
1701 | invalid, since we never want to recognize an instruction which uses |
1702 | a field of this type. */ |
1703 | |
1704 | static unsigned long |
1705 | insert_nsi (unsigned long insn, |
1706 | long value, |
1707 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1708 | const char **errmsg ATTRIBUTE_UNUSED) |
1709 | { |
1710 | return insn | (-value & 0xffff); |
1711 | } |
1712 | |
1713 | static long |
1714 | (unsigned long insn, |
1715 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1716 | int *invalid) |
1717 | { |
1718 | *invalid = 1; |
1719 | return -(((insn & 0xffff) ^ 0x8000) - 0x8000); |
1720 | } |
1721 | |
1722 | /* The RA field in a D or X form instruction which is an updating |
1723 | load, which means that the RA field may not be zero and may not |
1724 | equal the RT field. */ |
1725 | |
1726 | static unsigned long |
1727 | insert_ral (unsigned long insn, |
1728 | long value, |
1729 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1730 | const char **errmsg) |
1731 | { |
1732 | if (value == 0 |
1733 | || (unsigned long) value == ((insn >> 21) & 0x1f)) |
1734 | *errmsg = "invalid register operand when updating" ; |
1735 | return insn | ((value & 0x1f) << 16); |
1736 | } |
1737 | |
1738 | /* The RA field in an lmw instruction, which has special value |
1739 | restrictions. */ |
1740 | |
1741 | static unsigned long |
1742 | insert_ram (unsigned long insn, |
1743 | long value, |
1744 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1745 | const char **errmsg) |
1746 | { |
1747 | if ((unsigned long) value >= ((insn >> 21) & 0x1f)) |
1748 | *errmsg = _("index register in load range" ); |
1749 | return insn | ((value & 0x1f) << 16); |
1750 | } |
1751 | |
1752 | /* The RA field in the DQ form lq or an lswx instruction, which have special |
1753 | value restrictions. */ |
1754 | |
1755 | static unsigned long |
1756 | insert_raq (unsigned long insn, |
1757 | long value, |
1758 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1759 | const char **errmsg) |
1760 | { |
1761 | long rtvalue = (insn & RT_MASK) >> 21; |
1762 | |
1763 | if (value == rtvalue) |
1764 | *errmsg = _("source and target register operands must be different" ); |
1765 | return insn | ((value & 0x1f) << 16); |
1766 | } |
1767 | |
1768 | /* The RA field in a D or X form instruction which is an updating |
1769 | store or an updating floating point load, which means that the RA |
1770 | field may not be zero. */ |
1771 | |
1772 | static unsigned long |
1773 | insert_ras (unsigned long insn, |
1774 | long value, |
1775 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1776 | const char **errmsg) |
1777 | { |
1778 | if (value == 0) |
1779 | *errmsg = _("invalid register operand when updating" ); |
1780 | return insn | ((value & 0x1f) << 16); |
1781 | } |
1782 | |
1783 | /* The RB field in an X form instruction when it must be the same as |
1784 | the RS field in the instruction. This is used for extended |
1785 | mnemonics like mr. This operand is marked FAKE. The insertion |
1786 | function just copies the BT field into the BA field, and the |
1787 | extraction function just checks that the fields are the same. */ |
1788 | |
1789 | static unsigned long |
1790 | insert_rbs (unsigned long insn, |
1791 | long value ATTRIBUTE_UNUSED, |
1792 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1793 | const char **errmsg ATTRIBUTE_UNUSED) |
1794 | { |
1795 | return insn | (((insn >> 21) & 0x1f) << 11); |
1796 | } |
1797 | |
1798 | static long |
1799 | (unsigned long insn, |
1800 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1801 | int *invalid) |
1802 | { |
1803 | if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) |
1804 | *invalid = 1; |
1805 | return 0; |
1806 | } |
1807 | |
1808 | /* The RB field in an lswx instruction, which has special value |
1809 | restrictions. */ |
1810 | |
1811 | static unsigned long |
1812 | insert_rbx (unsigned long insn, |
1813 | long value, |
1814 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1815 | const char **errmsg) |
1816 | { |
1817 | long rtvalue = (insn & RT_MASK) >> 21; |
1818 | |
1819 | if (value == rtvalue) |
1820 | *errmsg = _("source and target register operands must be different" ); |
1821 | return insn | ((value & 0x1f) << 11); |
1822 | } |
1823 | |
1824 | /* The SCI8 field is made up of SCL and {U,N}I8 fields. */ |
1825 | static unsigned long |
1826 | insert_sci8 (unsigned long insn, |
1827 | long value, |
1828 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1829 | const char **errmsg) |
1830 | { |
1831 | unsigned int fill_scale = 0; |
1832 | unsigned long ui8 = value; |
1833 | |
1834 | if ((ui8 & 0xffffff00) == 0) |
1835 | ; |
1836 | else if ((ui8 & 0xffffff00) == 0xffffff00) |
1837 | fill_scale = 0x400; |
1838 | else if ((ui8 & 0xffff00ff) == 0) |
1839 | { |
1840 | fill_scale = 1 << 8; |
1841 | ui8 >>= 8; |
1842 | } |
1843 | else if ((ui8 & 0xffff00ff) == 0xffff00ff) |
1844 | { |
1845 | fill_scale = 0x400 | (1 << 8); |
1846 | ui8 >>= 8; |
1847 | } |
1848 | else if ((ui8 & 0xff00ffff) == 0) |
1849 | { |
1850 | fill_scale = 2 << 8; |
1851 | ui8 >>= 16; |
1852 | } |
1853 | else if ((ui8 & 0xff00ffff) == 0xff00ffff) |
1854 | { |
1855 | fill_scale = 0x400 | (2 << 8); |
1856 | ui8 >>= 16; |
1857 | } |
1858 | else if ((ui8 & 0x00ffffff) == 0) |
1859 | { |
1860 | fill_scale = 3 << 8; |
1861 | ui8 >>= 24; |
1862 | } |
1863 | else if ((ui8 & 0x00ffffff) == 0x00ffffff) |
1864 | { |
1865 | fill_scale = 0x400 | (3 << 8); |
1866 | ui8 >>= 24; |
1867 | } |
1868 | else |
1869 | { |
1870 | *errmsg = _("illegal immediate value" ); |
1871 | ui8 = 0; |
1872 | } |
1873 | |
1874 | return insn | fill_scale | (ui8 & 0xff); |
1875 | } |
1876 | |
1877 | static long |
1878 | (unsigned long insn, |
1879 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1880 | int *invalid ATTRIBUTE_UNUSED) |
1881 | { |
1882 | int fill = insn & 0x400; |
1883 | int scale_factor = (insn & 0x300) >> 5; |
1884 | long value = (insn & 0xff) << scale_factor; |
1885 | |
1886 | if (fill != 0) |
1887 | value |= ~((long) 0xff << scale_factor); |
1888 | return value; |
1889 | } |
1890 | |
1891 | static unsigned long |
1892 | insert_sci8n (unsigned long insn, |
1893 | long value, |
1894 | ppc_cpu_t dialect, |
1895 | const char **errmsg) |
1896 | { |
1897 | return insert_sci8 (insn, value: -value, dialect, errmsg); |
1898 | } |
1899 | |
1900 | static long |
1901 | (unsigned long insn, |
1902 | ppc_cpu_t dialect, |
1903 | int *invalid) |
1904 | { |
1905 | return -extract_sci8 (insn, dialect, invalid); |
1906 | } |
1907 | |
1908 | static unsigned long |
1909 | insert_sd4h (unsigned long insn, |
1910 | long value, |
1911 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1912 | const char **errmsg ATTRIBUTE_UNUSED) |
1913 | { |
1914 | return insn | ((value & 0x1e) << 7); |
1915 | } |
1916 | |
1917 | static long |
1918 | (unsigned long insn, |
1919 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1920 | int *invalid ATTRIBUTE_UNUSED) |
1921 | { |
1922 | return ((insn >> 8) & 0xf) << 1; |
1923 | } |
1924 | |
1925 | static unsigned long |
1926 | insert_sd4w (unsigned long insn, |
1927 | long value, |
1928 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1929 | const char **errmsg ATTRIBUTE_UNUSED) |
1930 | { |
1931 | return insn | ((value & 0x3c) << 6); |
1932 | } |
1933 | |
1934 | static long |
1935 | (unsigned long insn, |
1936 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1937 | int *invalid ATTRIBUTE_UNUSED) |
1938 | { |
1939 | return ((insn >> 8) & 0xf) << 2; |
1940 | } |
1941 | |
1942 | static unsigned long |
1943 | insert_oimm (unsigned long insn, |
1944 | long value, |
1945 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1946 | const char **errmsg ATTRIBUTE_UNUSED) |
1947 | { |
1948 | return insn | (((value - 1) & 0x1f) << 4); |
1949 | } |
1950 | |
1951 | static long |
1952 | (unsigned long insn, |
1953 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1954 | int *invalid ATTRIBUTE_UNUSED) |
1955 | { |
1956 | return ((insn >> 4) & 0x1f) + 1; |
1957 | } |
1958 | |
1959 | /* The SH field in an MD form instruction. This is split. */ |
1960 | |
1961 | static unsigned long |
1962 | insert_sh6 (unsigned long insn, |
1963 | long value, |
1964 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1965 | const char **errmsg ATTRIBUTE_UNUSED) |
1966 | { |
1967 | /* SH6 operand in the rldixor instructions. */ |
1968 | if (PPC_OP (insn) == 4) |
1969 | return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5); |
1970 | else |
1971 | return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); |
1972 | } |
1973 | |
1974 | static long |
1975 | (unsigned long insn, |
1976 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1977 | int *invalid ATTRIBUTE_UNUSED) |
1978 | { |
1979 | /* SH6 operand in the rldixor instructions. */ |
1980 | if (PPC_OP (insn) == 4) |
1981 | return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20); |
1982 | else |
1983 | return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); |
1984 | } |
1985 | |
1986 | /* The SPR field in an XFX form instruction. This is flipped--the |
1987 | lower 5 bits are stored in the upper 5 and vice- versa. */ |
1988 | |
1989 | static unsigned long |
1990 | insert_spr (unsigned long insn, |
1991 | long value, |
1992 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
1993 | const char **errmsg ATTRIBUTE_UNUSED) |
1994 | { |
1995 | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); |
1996 | } |
1997 | |
1998 | static long |
1999 | (unsigned long insn, |
2000 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2001 | int *invalid ATTRIBUTE_UNUSED) |
2002 | { |
2003 | return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); |
2004 | } |
2005 | |
2006 | /* Some dialects have 8 SPRG registers instead of the standard 4. */ |
2007 | #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405) |
2008 | |
2009 | static unsigned long |
2010 | insert_sprg (unsigned long insn, |
2011 | long value, |
2012 | ppc_cpu_t dialect, |
2013 | const char **errmsg) |
2014 | { |
2015 | if (value > 7 |
2016 | || (value > 3 && (dialect & ALLOW8_SPRG) == 0)) |
2017 | *errmsg = _("invalid sprg number" ); |
2018 | |
2019 | /* If this is mfsprg4..7 then use spr 260..263 which can be read in |
2020 | user mode. Anything else must use spr 272..279. */ |
2021 | if (value <= 3 || (insn & 0x100) != 0) |
2022 | value |= 0x10; |
2023 | |
2024 | return insn | ((value & 0x17) << 16); |
2025 | } |
2026 | |
2027 | static long |
2028 | (unsigned long insn, |
2029 | ppc_cpu_t dialect, |
2030 | int *invalid) |
2031 | { |
2032 | unsigned long val = (insn >> 16) & 0x1f; |
2033 | |
2034 | /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 |
2035 | If not BOOKE, 405 or VLE, then both use only 272..275. */ |
2036 | if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0) |
2037 | || (val - 0x10 > 7 && (insn & 0x100) != 0) |
2038 | || val <= 3 |
2039 | || (val & 8) != 0) |
2040 | *invalid = 1; |
2041 | return val & 7; |
2042 | } |
2043 | |
2044 | /* The TBR field in an XFX instruction. This is just like SPR, but it |
2045 | is optional. */ |
2046 | |
2047 | static unsigned long |
2048 | insert_tbr (unsigned long insn, |
2049 | long value, |
2050 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2051 | const char **errmsg) |
2052 | { |
2053 | if (value != 268 && value != 269) |
2054 | *errmsg = _("invalid tbr number" ); |
2055 | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); |
2056 | } |
2057 | |
2058 | static long |
2059 | (unsigned long insn, |
2060 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2061 | int *invalid) |
2062 | { |
2063 | long ret; |
2064 | |
2065 | ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); |
2066 | if (ret != 268 && ret != 269) |
2067 | *invalid = 1; |
2068 | return ret; |
2069 | } |
2070 | |
2071 | /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ |
2072 | |
2073 | static unsigned long |
2074 | insert_xt6 (unsigned long insn, |
2075 | long value, |
2076 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2077 | const char **errmsg ATTRIBUTE_UNUSED) |
2078 | { |
2079 | return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5); |
2080 | } |
2081 | |
2082 | static long |
2083 | (unsigned long insn, |
2084 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2085 | int *invalid ATTRIBUTE_UNUSED) |
2086 | { |
2087 | return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f); |
2088 | } |
2089 | |
2090 | /* The XT and XS fields in an DQ form VSX instruction. This is split. */ |
2091 | static unsigned long |
2092 | insert_xtq6 (unsigned long insn, |
2093 | long value, |
2094 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2095 | const char **errmsg ATTRIBUTE_UNUSED) |
2096 | { |
2097 | return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2); |
2098 | } |
2099 | |
2100 | static long |
2101 | (unsigned long insn, |
2102 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2103 | int *invalid ATTRIBUTE_UNUSED) |
2104 | { |
2105 | return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f); |
2106 | } |
2107 | |
2108 | /* The XA field in an XX3 form instruction. This is split. */ |
2109 | |
2110 | static unsigned long |
2111 | insert_xa6 (unsigned long insn, |
2112 | long value, |
2113 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2114 | const char **errmsg ATTRIBUTE_UNUSED) |
2115 | { |
2116 | return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3); |
2117 | } |
2118 | |
2119 | static long |
2120 | (unsigned long insn, |
2121 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2122 | int *invalid ATTRIBUTE_UNUSED) |
2123 | { |
2124 | return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); |
2125 | } |
2126 | |
2127 | /* The XB field in an XX3 form instruction. This is split. */ |
2128 | |
2129 | static unsigned long |
2130 | insert_xb6 (unsigned long insn, |
2131 | long value, |
2132 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2133 | const char **errmsg ATTRIBUTE_UNUSED) |
2134 | { |
2135 | return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); |
2136 | } |
2137 | |
2138 | static long |
2139 | (unsigned long insn, |
2140 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2141 | int *invalid ATTRIBUTE_UNUSED) |
2142 | { |
2143 | return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f); |
2144 | } |
2145 | |
2146 | /* The XB field in an XX3 form instruction when it must be the same as |
2147 | the XA field in the instruction. This is used for extended |
2148 | mnemonics like xvmovdp. This operand is marked FAKE. The insertion |
2149 | function just copies the XA field into the XB field, and the |
2150 | extraction function just checks that the fields are the same. */ |
2151 | |
2152 | static unsigned long |
2153 | insert_xb6s (unsigned long insn, |
2154 | long value ATTRIBUTE_UNUSED, |
2155 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2156 | const char **errmsg ATTRIBUTE_UNUSED) |
2157 | { |
2158 | return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1); |
2159 | } |
2160 | |
2161 | static long |
2162 | (unsigned long insn, |
2163 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2164 | int *invalid) |
2165 | { |
2166 | if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) |
2167 | || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1))) |
2168 | *invalid = 1; |
2169 | return 0; |
2170 | } |
2171 | |
2172 | /* The XC field in an XX4 form instruction. This is split. */ |
2173 | |
2174 | static unsigned long |
2175 | insert_xc6 (unsigned long insn, |
2176 | long value, |
2177 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2178 | const char **errmsg ATTRIBUTE_UNUSED) |
2179 | { |
2180 | return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2); |
2181 | } |
2182 | |
2183 | static long |
2184 | (unsigned long insn, |
2185 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2186 | int *invalid ATTRIBUTE_UNUSED) |
2187 | { |
2188 | return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f); |
2189 | } |
2190 | |
2191 | static unsigned long |
2192 | insert_dm (unsigned long insn, |
2193 | long value, |
2194 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2195 | const char **errmsg) |
2196 | { |
2197 | if (value != 0 && value != 1) |
2198 | *errmsg = _("invalid constant" ); |
2199 | return insn | (((value) ? 3 : 0) << 8); |
2200 | } |
2201 | |
2202 | static long |
2203 | (unsigned long insn, |
2204 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2205 | int *invalid) |
2206 | { |
2207 | long value; |
2208 | |
2209 | value = (insn >> 8) & 3; |
2210 | if (value != 0 && value != 3) |
2211 | *invalid = 1; |
2212 | return (value) ? 1 : 0; |
2213 | } |
2214 | |
2215 | /* The VLESIMM field in an I16A form instruction. This is split. */ |
2216 | |
2217 | static unsigned long |
2218 | insert_vlesi (unsigned long insn, |
2219 | long value, |
2220 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2221 | const char **errmsg ATTRIBUTE_UNUSED) |
2222 | { |
2223 | return insn | ((value & 0xf800) << 10) | (value & 0x7ff); |
2224 | } |
2225 | |
2226 | static long |
2227 | (unsigned long insn, |
2228 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2229 | int *invalid ATTRIBUTE_UNUSED) |
2230 | { |
2231 | long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); |
2232 | value = (value ^ 0x8000) - 0x8000; |
2233 | return value; |
2234 | } |
2235 | |
2236 | static unsigned long |
2237 | insert_vlensi (unsigned long insn, |
2238 | long value, |
2239 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2240 | const char **errmsg ATTRIBUTE_UNUSED) |
2241 | { |
2242 | value = -value; |
2243 | return insn | ((value & 0xf800) << 10) | (value & 0x7ff); |
2244 | } |
2245 | static long |
2246 | (unsigned long insn, |
2247 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2248 | int *invalid ATTRIBUTE_UNUSED) |
2249 | { |
2250 | long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); |
2251 | value = (value ^ 0x8000) - 0x8000; |
2252 | /* Don't use for disassembly. */ |
2253 | *invalid = 1; |
2254 | return -value; |
2255 | } |
2256 | |
2257 | /* The VLEUIMM field in an I16A form instruction. This is split. */ |
2258 | |
2259 | static unsigned long |
2260 | insert_vleui (unsigned long insn, |
2261 | long value, |
2262 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2263 | const char **errmsg ATTRIBUTE_UNUSED) |
2264 | { |
2265 | return insn | ((value & 0xf800) << 10) | (value & 0x7ff); |
2266 | } |
2267 | |
2268 | static long |
2269 | (unsigned long insn, |
2270 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2271 | int *invalid ATTRIBUTE_UNUSED) |
2272 | { |
2273 | return ((insn >> 10) & 0xf800) | (insn & 0x7ff); |
2274 | } |
2275 | |
2276 | /* The VLEUIMML field in an I16L form instruction. This is split. */ |
2277 | |
2278 | static unsigned long |
2279 | insert_vleil (unsigned long insn, |
2280 | long value, |
2281 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2282 | const char **errmsg ATTRIBUTE_UNUSED) |
2283 | { |
2284 | return insn | ((value & 0xf800) << 5) | (value & 0x7ff); |
2285 | } |
2286 | |
2287 | static long |
2288 | (unsigned long insn, |
2289 | ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
2290 | int *invalid ATTRIBUTE_UNUSED) |
2291 | { |
2292 | return ((insn >> 5) & 0xf800) | (insn & 0x7ff); |
2293 | } |
2294 | |
2295 | |
2296 | /* Macros used to form opcodes. */ |
2297 | |
2298 | /* The main opcode. */ |
2299 | #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) |
2300 | #define OP_MASK OP (0x3f) |
2301 | |
2302 | /* The main opcode combined with a trap code in the TO field of a D |
2303 | form instruction. Used for extended mnemonics for the trap |
2304 | instructions. */ |
2305 | #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) |
2306 | #define OPTO_MASK (OP_MASK | TO_MASK) |
2307 | |
2308 | /* The main opcode combined with a comparison size bit in the L field |
2309 | of a D form or X form instruction. Used for extended mnemonics for |
2310 | the comparison instructions. */ |
2311 | #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) |
2312 | #define OPL_MASK OPL (0x3f,1) |
2313 | |
2314 | /* The main opcode combined with an update code in D form instruction. |
2315 | Used for extended mnemonics for VLE memory instructions. */ |
2316 | #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8)) |
2317 | #define OPVUP_MASK OPVUP (0x3f, 0xff) |
2318 | |
2319 | /* The main opcode combined with an update code and the RT fields specified in |
2320 | D form instruction. Used for VLE volatile context save/restore |
2321 | instructions. */ |
2322 | #define OPVUPRT(x,vup,rt) (OPVUP (x, vup) | ((((unsigned long)(rt)) & 0x1f) << 21)) |
2323 | #define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f) |
2324 | |
2325 | /* An A form instruction. */ |
2326 | #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) |
2327 | #define A_MASK A (0x3f, 0x1f, 1) |
2328 | |
2329 | /* An A_MASK with the FRB field fixed. */ |
2330 | #define AFRB_MASK (A_MASK | FRB_MASK) |
2331 | |
2332 | /* An A_MASK with the FRC field fixed. */ |
2333 | #define AFRC_MASK (A_MASK | FRC_MASK) |
2334 | |
2335 | /* An A_MASK with the FRA and FRC fields fixed. */ |
2336 | #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) |
2337 | |
2338 | /* An AFRAFRC_MASK, but with L bit clear. */ |
2339 | #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16)) |
2340 | |
2341 | /* A B form instruction. */ |
2342 | #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) |
2343 | #define B_MASK B (0x3f, 1, 1) |
2344 | |
2345 | /* A BD8 form instruction. This is a 16-bit instruction. */ |
2346 | #define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8)) |
2347 | #define BD8_MASK BD8 (0x3f, 1, 1) |
2348 | |
2349 | /* Another BD8 form instruction. This is a 16-bit instruction. */ |
2350 | #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11) |
2351 | #define BD8IO_MASK BD8IO (0x1f) |
2352 | |
2353 | /* A BD8 form instruction for simplified mnemonics. */ |
2354 | #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8)) |
2355 | /* A mask that excludes BO32 and BI32. */ |
2356 | #define EBD8IO1_MASK 0xf800 |
2357 | /* A mask that includes BO32 and excludes BI32. */ |
2358 | #define EBD8IO2_MASK 0xfc00 |
2359 | /* A mask that include BO32 AND BI32. */ |
2360 | #define EBD8IO3_MASK 0xff00 |
2361 | |
2362 | /* A BD15 form instruction. */ |
2363 | #define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1)) |
2364 | #define BD15_MASK BD15 (0x3f, 0xf, 1) |
2365 | |
2366 | /* A BD15 form instruction for extended conditional branch mnemonics. */ |
2367 | #define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1) |
2368 | #define EBD15_MASK 0xfff00001 |
2369 | |
2370 | /* A BD15 form instruction for extended conditional branch mnemonics with BI. */ |
2371 | #define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \ |
2372 | | (((aa) & 0xf) << 22) \ |
2373 | | (((bo) & 0x3) << 20) \ |
2374 | | (((bi) & 0x3) << 16) \ |
2375 | | ((lk) & 1) |
2376 | #define EBD15BI_MASK 0xfff30001 |
2377 | |
2378 | /* A BD24 form instruction. */ |
2379 | #define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1)) |
2380 | #define BD24_MASK BD24 (0x3f, 1, 1) |
2381 | |
2382 | /* A B form instruction setting the BO field. */ |
2383 | #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) |
2384 | #define BBO_MASK BBO (0x3f, 0x1f, 1, 1) |
2385 | |
2386 | /* A BBO_MASK with the y bit of the BO field removed. This permits |
2387 | matching a conditional branch regardless of the setting of the y |
2388 | bit. Similarly for the 'at' bits used for power4 branch hints. */ |
2389 | #define Y_MASK (((unsigned long) 1) << 21) |
2390 | #define AT1_MASK (((unsigned long) 3) << 21) |
2391 | #define AT2_MASK (((unsigned long) 9) << 21) |
2392 | #define BBOY_MASK (BBO_MASK &~ Y_MASK) |
2393 | #define BBOAT_MASK (BBO_MASK &~ AT1_MASK) |
2394 | |
2395 | /* A B form instruction setting the BO field and the condition bits of |
2396 | the BI field. */ |
2397 | #define BBOCB(op, bo, cb, aa, lk) \ |
2398 | (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) |
2399 | #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) |
2400 | |
2401 | /* A BBOCB_MASK with the y bit of the BO field removed. */ |
2402 | #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) |
2403 | #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) |
2404 | #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) |
2405 | |
2406 | /* A BBOYCB_MASK in which the BI field is fixed. */ |
2407 | #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) |
2408 | #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) |
2409 | |
2410 | /* A VLE C form instruction. */ |
2411 | #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1)) |
2412 | #define C_LK_MASK C_LK(0x7fff, 1) |
2413 | #define C(x) ((((unsigned long)(x)) & 0xffff)) |
2414 | #define C_MASK C(0xffff) |
2415 | |
2416 | /* An Context form instruction. */ |
2417 | #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) |
2418 | #define CTX_MASK CTX(0x3f, 0x7) |
2419 | |
2420 | /* A User Context form instruction. */ |
2421 | #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) |
2422 | #define UCTX_MASK UCTX(0x3f, 0x1f) |
2423 | |
2424 | /* The main opcode mask with the RA field clear. */ |
2425 | #define DRA_MASK (OP_MASK | RA_MASK) |
2426 | |
2427 | /* A DQ form VSX instruction. */ |
2428 | #define DQX(op, xop) (OP (op) | ((xop) & 0x7)) |
2429 | #define DQX_MASK DQX (0x3f, 7) |
2430 | |
2431 | /* A DS form instruction. */ |
2432 | #define DSO(op, xop) (OP (op) | ((xop) & 0x3)) |
2433 | #define DS_MASK DSO (0x3f, 3) |
2434 | |
2435 | /* An DX form instruction. */ |
2436 | #define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) |
2437 | #define DX_MASK DX (0x3f, 0x1f) |
2438 | |
2439 | /* An EVSEL form instruction. */ |
2440 | #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) |
2441 | #define EVSEL_MASK EVSEL(0x3f, 0xff) |
2442 | |
2443 | /* An IA16 form instruction. */ |
2444 | #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) |
2445 | #define IA16_MASK IA16(0x3f, 0x1f) |
2446 | |
2447 | /* An I16A form instruction. */ |
2448 | #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) |
2449 | #define I16A_MASK I16A(0x3f, 0x1f) |
2450 | |
2451 | /* An I16L form instruction. */ |
2452 | #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) |
2453 | #define I16L_MASK I16L(0x3f, 0x1f) |
2454 | |
2455 | /* An IM7 form instruction. */ |
2456 | #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11) |
2457 | #define IM7_MASK IM7(0x1f) |
2458 | |
2459 | /* An M form instruction. */ |
2460 | #define M(op, rc) (OP (op) | ((rc) & 1)) |
2461 | #define M_MASK M (0x3f, 1) |
2462 | |
2463 | /* An LI20 form instruction. */ |
2464 | #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15) |
2465 | #define LI20_MASK LI20(0x3f, 0x1) |
2466 | |
2467 | /* An M form instruction with the ME field specified. */ |
2468 | #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) |
2469 | |
2470 | /* An M_MASK with the MB and ME fields fixed. */ |
2471 | #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) |
2472 | |
2473 | /* An M_MASK with the SH and ME fields fixed. */ |
2474 | #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) |
2475 | |
2476 | /* An MD form instruction. */ |
2477 | #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1)) |
2478 | #define MD_MASK MD (0x3f, 0x7, 1) |
2479 | |
2480 | /* An MD_MASK with the MB field fixed. */ |
2481 | #define MDMB_MASK (MD_MASK | MB6_MASK) |
2482 | |
2483 | /* An MD_MASK with the SH field fixed. */ |
2484 | #define MDSH_MASK (MD_MASK | SH6_MASK) |
2485 | |
2486 | /* An MDS form instruction. */ |
2487 | #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1)) |
2488 | #define MDS_MASK MDS (0x3f, 0xf, 1) |
2489 | |
2490 | /* An MDS_MASK with the MB field fixed. */ |
2491 | #define MDSMB_MASK (MDS_MASK | MB6_MASK) |
2492 | |
2493 | /* An SC form instruction. */ |
2494 | #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) |
2495 | #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) |
2496 | |
2497 | /* An SCI8 form instruction. */ |
2498 | #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11)) |
2499 | #define SCI8_MASK SCI8(0x3f, 0x1f) |
2500 | |
2501 | /* An SCI8 form instruction. */ |
2502 | #define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23)) |
2503 | #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f) |
2504 | |
2505 | /* An SD4 form instruction. This is a 16-bit instruction. */ |
2506 | #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12) |
2507 | #define SD4_MASK SD4(0xf) |
2508 | |
2509 | /* An SE_IM5 form instruction. This is a 16-bit instruction. */ |
2510 | #define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9)) |
2511 | #define SE_IM5_MASK SE_IM5(0x3f, 1) |
2512 | |
2513 | /* An SE_R form instruction. This is a 16-bit instruction. */ |
2514 | #define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4)) |
2515 | #define SE_R_MASK SE_R(0x3f, 0x3f) |
2516 | |
2517 | /* An SE_RR form instruction. This is a 16-bit instruction. */ |
2518 | #define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8)) |
2519 | #define SE_RR_MASK SE_RR(0x3f, 3) |
2520 | |
2521 | /* A VX form instruction. */ |
2522 | #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) |
2523 | |
2524 | /* The mask for an VX form instruction. */ |
2525 | #define VX_MASK VX(0x3f, 0x7ff) |
2526 | |
2527 | /* A VX_MASK with the VA field fixed. */ |
2528 | #define VXVA_MASK (VX_MASK | (0x1f << 16)) |
2529 | |
2530 | /* A VX_MASK with the VB field fixed. */ |
2531 | #define VXVB_MASK (VX_MASK | (0x1f << 11)) |
2532 | |
2533 | /* A VX_MASK with the VA and VB fields fixed. */ |
2534 | #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11)) |
2535 | |
2536 | /* A VX_MASK with the VD and VA fields fixed. */ |
2537 | #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16)) |
2538 | |
2539 | /* A VX_MASK with a UIMM4 field. */ |
2540 | #define VXUIMM4_MASK (VX_MASK | (0x1 << 20)) |
2541 | |
2542 | /* A VX_MASK with a UIMM3 field. */ |
2543 | #define VXUIMM3_MASK (VX_MASK | (0x3 << 19)) |
2544 | |
2545 | /* A VX_MASK with a UIMM2 field. */ |
2546 | #define VXUIMM2_MASK (VX_MASK | (0x7 << 18)) |
2547 | |
2548 | /* A VX_MASK with a PS field. */ |
2549 | #define VXPS_MASK (VX_MASK & ~(0x1 << 9)) |
2550 | |
2551 | /* A VX_MASK with the VA field fixed with a PS field. */ |
2552 | #define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9)) |
2553 | |
2554 | /* A VA form instruction. */ |
2555 | #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) |
2556 | |
2557 | /* The mask for an VA form instruction. */ |
2558 | #define VXA_MASK VXA(0x3f, 0x3f) |
2559 | |
2560 | /* A VXA_MASK with a SHB field. */ |
2561 | #define VXASHB_MASK (VXA_MASK | (1 << 10)) |
2562 | |
2563 | /* A VXR form instruction. */ |
2564 | #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) |
2565 | |
2566 | /* The mask for a VXR form instruction. */ |
2567 | #define VXR_MASK VXR(0x3f, 0x3ff, 1) |
2568 | |
2569 | /* A VX form instruction with a VA tertiary opcode. */ |
2570 | #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16)) |
2571 | |
2572 | #define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) |
2573 | #define VXASH_MASK VXASH (0x3f, 0x1f) |
2574 | |
2575 | /* An X form instruction. */ |
2576 | #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) |
2577 | |
2578 | /* A X form instruction for Quad-Precision FP Instructions. */ |
2579 | #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16)) |
2580 | |
2581 | /* An EX form instruction. */ |
2582 | #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) |
2583 | |
2584 | /* The mask for an EX form instruction. */ |
2585 | #define EX_MASK EX (0x3f, 0x7ff) |
2586 | |
2587 | /* An XX2 form instruction. */ |
2588 | #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2)) |
2589 | |
2590 | /* A XX2 form instruction with the VA bits specified. */ |
2591 | #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16)) |
2592 | |
2593 | /* An XX3 form instruction. */ |
2594 | #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3)) |
2595 | |
2596 | /* An XX3 form instruction with the RC bit specified. */ |
2597 | #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3)) |
2598 | |
2599 | /* An XX4 form instruction. */ |
2600 | #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4)) |
2601 | |
2602 | /* A Z form instruction. */ |
2603 | #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1)) |
2604 | |
2605 | /* An X form instruction with the RC bit specified. */ |
2606 | #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) |
2607 | |
2608 | /* A X form instruction for Quad-Precision FP Instructions with RC bit. */ |
2609 | #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1)) |
2610 | |
2611 | /* An X form instruction with the RA bits specified as two ops. */ |
2612 | #define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16) |
2613 | |
2614 | /* A Z form instruction with the RC bit specified. */ |
2615 | #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) |
2616 | |
2617 | /* The mask for an X form instruction. */ |
2618 | #define X_MASK XRC (0x3f, 0x3ff, 1) |
2619 | |
2620 | /* The mask for an X form instruction with the BF bits specified. */ |
2621 | #define XBF_MASK (X_MASK | (3 << 21)) |
2622 | |
2623 | /* An X form wait instruction with everything filled in except the WC field. */ |
2624 | #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) |
2625 | |
2626 | /* The mask for an XX1 form instruction. */ |
2627 | #define XX1_MASK X (0x3f, 0x3ff) |
2628 | |
2629 | /* An XX1_MASK with the RB field fixed. */ |
2630 | #define XX1RB_MASK (XX1_MASK | RB_MASK) |
2631 | |
2632 | /* The mask for an XX2 form instruction. */ |
2633 | #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16)) |
2634 | |
2635 | /* The mask for an XX2 form instruction with the UIM bits specified. */ |
2636 | #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18)) |
2637 | |
2638 | /* The mask for an XX2 form instruction with the 4 UIM bits specified. */ |
2639 | #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20)) |
2640 | |
2641 | /* The mask for an XX2 form instruction with the BF bits specified. */ |
2642 | #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1)) |
2643 | |
2644 | /* The mask for an XX2 form instruction with the BF and DCMX bits specified. */ |
2645 | #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1) |
2646 | |
2647 | /* The mask for an XX2 form instruction with a split DCMX bits specified. */ |
2648 | #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee) |
2649 | |
2650 | /* The mask for an XX3 form instruction. */ |
2651 | #define XX3_MASK XX3 (0x3f, 0xff) |
2652 | |
2653 | /* The mask for an XX3 form instruction with the BF bits specified. */ |
2654 | #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1)) |
2655 | |
2656 | /* The mask for an XX3 form instruction with the DM or SHW bits specified. */ |
2657 | #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10)) |
2658 | #define XX3SHW_MASK XX3DM_MASK |
2659 | |
2660 | /* The mask for an XX4 form instruction. */ |
2661 | #define XX4_MASK XX4 (0x3f, 0x3) |
2662 | |
2663 | /* An X form wait instruction with everything filled in except the WC field. */ |
2664 | #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) |
2665 | |
2666 | /* The mask for an XMMF form instruction. */ |
2667 | #define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1)) |
2668 | |
2669 | /* The mask for a Z form instruction. */ |
2670 | #define Z_MASK ZRC (0x3f, 0x1ff, 1) |
2671 | #define Z2_MASK ZRC (0x3f, 0xff, 1) |
2672 | |
2673 | /* An X_MASK with the RA/VA field fixed. */ |
2674 | #define XRA_MASK (X_MASK | RA_MASK) |
2675 | #define XVA_MASK XRA_MASK |
2676 | |
2677 | /* An XRA_MASK with the A_L/W field clear. */ |
2678 | #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16)) |
2679 | #define XRLA_MASK XWRA_MASK |
2680 | |
2681 | /* An X_MASK with the RB field fixed. */ |
2682 | #define XRB_MASK (X_MASK | RB_MASK) |
2683 | |
2684 | /* An X_MASK with the RT field fixed. */ |
2685 | #define XRT_MASK (X_MASK | RT_MASK) |
2686 | |
2687 | /* An XRT_MASK mask with the L bits clear. */ |
2688 | #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21)) |
2689 | |
2690 | /* An X_MASK with the RA and RB fields fixed. */ |
2691 | #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) |
2692 | |
2693 | /* An XBF_MASK with the RA and RB fields fixed. */ |
2694 | #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK) |
2695 | |
2696 | /* An XRARB_MASK, but with the L bit clear. */ |
2697 | #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) |
2698 | |
2699 | /* An XRARB_MASK, but with the L bits in a darn instruction clear. */ |
2700 | #define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16)) |
2701 | |
2702 | /* An X_MASK with the RT and RA fields fixed. */ |
2703 | #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) |
2704 | |
2705 | /* An X_MASK with the RT and RB fields fixed. */ |
2706 | #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK) |
2707 | |
2708 | /* An XRTRA_MASK, but with L bit clear. */ |
2709 | #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) |
2710 | |
2711 | /* An X_MASK with the RT, RA and RB fields fixed. */ |
2712 | #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK) |
2713 | |
2714 | /* An XRTRARB_MASK, but with L bit clear. */ |
2715 | #define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21)) |
2716 | |
2717 | /* An XRTRARB_MASK, but with A bit clear. */ |
2718 | #define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25)) |
2719 | |
2720 | /* An XRTRARB_MASK, but with BF bits clear. */ |
2721 | #define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23)) |
2722 | |
2723 | /* An X form instruction with the L bit specified. */ |
2724 | #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) |
2725 | |
2726 | /* An X form instruction with the L bits specified. */ |
2727 | #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) |
2728 | |
2729 | /* An X form instruction with the L bit and RC bit specified. */ |
2730 | #define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21)) |
2731 | |
2732 | /* An X form instruction with RT fields specified */ |
2733 | #define XRT(op, xop, rt) (X ((op), (xop)) \ |
2734 | | ((((unsigned long)(rt)) & 0x1f) << 21)) |
2735 | |
2736 | /* An X form instruction with RT and RA fields specified */ |
2737 | #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \ |
2738 | | ((((unsigned long)(rt)) & 0x1f) << 21) \ |
2739 | | ((((unsigned long)(ra)) & 0x1f) << 16)) |
2740 | |
2741 | /* The mask for an X form comparison instruction. */ |
2742 | #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) |
2743 | |
2744 | /* The mask for an X form comparison instruction with the L field |
2745 | fixed. */ |
2746 | #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) |
2747 | |
2748 | /* An X form trap instruction with the TO field specified. */ |
2749 | #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) |
2750 | #define XTO_MASK (X_MASK | TO_MASK) |
2751 | |
2752 | /* An X form tlb instruction with the SH field specified. */ |
2753 | #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11)) |
2754 | #define XTLB_MASK (X_MASK | SH_MASK) |
2755 | |
2756 | /* An X form sync instruction. */ |
2757 | #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) |
2758 | |
2759 | /* An X form sync instruction with everything filled in except the LS field. */ |
2760 | #define XSYNC_MASK (0xff9fffff) |
2761 | |
2762 | /* An X form sync instruction with everything filled in except the L and E fields. */ |
2763 | #define XSYNCLE_MASK (0xff90ffff) |
2764 | |
2765 | /* An X_MASK, but with the EH bit clear. */ |
2766 | #define XEH_MASK (X_MASK & ~((unsigned long )1)) |
2767 | |
2768 | /* An X form AltiVec dss instruction. */ |
2769 | #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) |
2770 | #define XDSS_MASK XDSS(0x3f, 0x3ff, 1) |
2771 | |
2772 | /* An XFL form instruction. */ |
2773 | #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) |
2774 | #define XFL_MASK XFL (0x3f, 0x3ff, 1) |
2775 | |
2776 | /* An X form isel instruction. */ |
2777 | #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) |
2778 | #define XISEL_MASK XISEL(0x3f, 0x1f) |
2779 | |
2780 | /* An XL form instruction with the LK field set to 0. */ |
2781 | #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) |
2782 | |
2783 | /* An XL form instruction which uses the LK field. */ |
2784 | #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) |
2785 | |
2786 | /* The mask for an XL form instruction. */ |
2787 | #define XL_MASK XLLK (0x3f, 0x3ff, 1) |
2788 | |
2789 | /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */ |
2790 | #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11)) |
2791 | |
2792 | /* An XL form instruction which explicitly sets the BO field. */ |
2793 | #define XLO(op, bo, xop, lk) \ |
2794 | (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) |
2795 | #define XLO_MASK (XL_MASK | BO_MASK) |
2796 | |
2797 | /* An XL form instruction which explicitly sets the y bit of the BO |
2798 | field. */ |
2799 | #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21)) |
2800 | #define XLYLK_MASK (XL_MASK | Y_MASK) |
2801 | |
2802 | /* An XL form instruction which sets the BO field and the condition |
2803 | bits of the BI field. */ |
2804 | #define XLOCB(op, bo, cb, xop, lk) \ |
2805 | (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16)) |
2806 | #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) |
2807 | |
2808 | /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ |
2809 | #define XLBB_MASK (XL_MASK | BB_MASK) |
2810 | #define XLYBB_MASK (XLYLK_MASK | BB_MASK) |
2811 | #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) |
2812 | |
2813 | /* A mask for branch instructions using the BH field. */ |
2814 | #define XLBH_MASK (XL_MASK | (0x1c << 11)) |
2815 | |
2816 | /* An XL_MASK with the BO and BB fields fixed. */ |
2817 | #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) |
2818 | |
2819 | /* An XL_MASK with the BO, BI and BB fields fixed. */ |
2820 | #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) |
2821 | |
2822 | /* An X form mbar instruction with MO field. */ |
2823 | #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21)) |
2824 | |
2825 | /* An XO form instruction. */ |
2826 | #define XO(op, xop, oe, rc) \ |
2827 | (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) |
2828 | #define XO_MASK XO (0x3f, 0x1ff, 1, 1) |
2829 | |
2830 | /* An XO_MASK with the RB field fixed. */ |
2831 | #define XORB_MASK (XO_MASK | RB_MASK) |
2832 | |
2833 | /* An XOPS form instruction for paired singles. */ |
2834 | #define XOPS(op, xop, rc) \ |
2835 | (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) |
2836 | #define XOPS_MASK XOPS (0x3f, 0x3ff, 1) |
2837 | |
2838 | |
2839 | /* An XS form instruction. */ |
2840 | #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) |
2841 | #define XS_MASK XS (0x3f, 0x1ff, 1) |
2842 | |
2843 | /* A mask for the FXM version of an XFX form instruction. */ |
2844 | #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20)) |
2845 | |
2846 | /* An XFX form instruction with the FXM field filled in. */ |
2847 | #define XFXM(op, xop, fxm, p4) \ |
2848 | (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \ |
2849 | | ((unsigned long)(p4) << 20)) |
2850 | |
2851 | /* An XFX form instruction with the SPR field filled in. */ |
2852 | #define XSPR(op, xop, spr) \ |
2853 | (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6)) |
2854 | #define XSPR_MASK (X_MASK | SPR_MASK) |
2855 | |
2856 | /* An XFX form instruction with the SPR field filled in except for the |
2857 | SPRBAT field. */ |
2858 | #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) |
2859 | |
2860 | /* An XFX form instruction with the SPR field filled in except for the |
2861 | SPRG field. */ |
2862 | #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) |
2863 | |
2864 | /* An X form instruction with everything filled in except the E field. */ |
2865 | #define XE_MASK (0xffff7fff) |
2866 | |
2867 | /* An X form user context instruction. */ |
2868 | #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) |
2869 | #define XUC_MASK XUC(0x3f, 0x1f) |
2870 | |
2871 | /* An XW form instruction. */ |
2872 | #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1)) |
2873 | /* The mask for a G form instruction. rc not supported at present. */ |
2874 | #define XW_MASK XW (0x3f, 0x3f, 0) |
2875 | |
2876 | /* An APU form instruction. */ |
2877 | #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1)) |
2878 | |
2879 | /* The mask for an APU form instruction. */ |
2880 | #define APU_MASK APU (0x3f, 0x3ff, 1) |
2881 | #define APU_RT_MASK (APU_MASK | RT_MASK) |
2882 | #define APU_RA_MASK (APU_MASK | RA_MASK) |
2883 | |
2884 | /* The BO encodings used in extended conditional branch mnemonics. */ |
2885 | #define BODNZF (0x0) |
2886 | #define BODNZFP (0x1) |
2887 | #define BODZF (0x2) |
2888 | #define BODZFP (0x3) |
2889 | #define BODNZT (0x8) |
2890 | #define BODNZTP (0x9) |
2891 | #define BODZT (0xa) |
2892 | #define BODZTP (0xb) |
2893 | |
2894 | #define BOF (0x4) |
2895 | #define BOFP (0x5) |
2896 | #define BOFM4 (0x6) |
2897 | #define BOFP4 (0x7) |
2898 | #define BOT (0xc) |
2899 | #define BOTP (0xd) |
2900 | #define BOTM4 (0xe) |
2901 | #define BOTP4 (0xf) |
2902 | |
2903 | #define BODNZ (0x10) |
2904 | #define BODNZP (0x11) |
2905 | #define BODZ (0x12) |
2906 | #define BODZP (0x13) |
2907 | #define BODNZM4 (0x18) |
2908 | #define BODNZP4 (0x19) |
2909 | #define BODZM4 (0x1a) |
2910 | #define BODZP4 (0x1b) |
2911 | |
2912 | #define BOU (0x14) |
2913 | |
2914 | /* The BO16 encodings used in extended VLE conditional branch mnemonics. */ |
2915 | #define BO16F (0x0) |
2916 | #define BO16T (0x1) |
2917 | |
2918 | /* The BO32 encodings used in extended VLE conditional branch mnemonics. */ |
2919 | #define BO32F (0x0) |
2920 | #define BO32T (0x1) |
2921 | #define BO32DNZ (0x2) |
2922 | #define BO32DZ (0x3) |
2923 | |
2924 | /* The BI condition bit encodings used in extended conditional branch |
2925 | mnemonics. */ |
2926 | #define CBLT (0) |
2927 | #define CBGT (1) |
2928 | #define CBEQ (2) |
2929 | #define CBSO (3) |
2930 | |
2931 | /* The TO encodings used in extended trap mnemonics. */ |
2932 | #define TOLGT (0x1) |
2933 | #define TOLLT (0x2) |
2934 | #define TOEQ (0x4) |
2935 | #define TOLGE (0x5) |
2936 | #define TOLNL (0x5) |
2937 | #define TOLLE (0x6) |
2938 | #define TOLNG (0x6) |
2939 | #define TOGT (0x8) |
2940 | #define TOGE (0xc) |
2941 | #define TONL (0xc) |
2942 | #define TOLT (0x10) |
2943 | #define TOLE (0x14) |
2944 | #define TONG (0x14) |
2945 | #define TONE (0x18) |
2946 | #define TOU (0x1f) |
2947 | |
2948 | /* Smaller names for the flags so each entry in the opcodes table will |
2949 | fit on a single line. */ |
2950 | #undef PPC |
2951 | #define PPC PPC_OPCODE_PPC |
2952 | #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON |
2953 | #define POWER4 PPC_OPCODE_POWER4 |
2954 | #define POWER5 PPC_OPCODE_POWER5 |
2955 | #define POWER6 PPC_OPCODE_POWER6 |
2956 | #define POWER7 PPC_OPCODE_POWER7 |
2957 | #define POWER8 PPC_OPCODE_POWER8 |
2958 | #define POWER9 PPC_OPCODE_POWER9 |
2959 | #define CELL PPC_OPCODE_CELL |
2960 | #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE |
2961 | #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \ |
2962 | | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) |
2963 | #define PPC403 PPC_OPCODE_403 |
2964 | #define PPC405 PPC_OPCODE_405 |
2965 | #define PPC440 PPC_OPCODE_440 |
2966 | #define PPC464 PPC440 |
2967 | #define PPC476 PPC_OPCODE_476 |
2968 | #define PPC750 PPC_OPCODE_750 |
2969 | #define PPC7450 PPC_OPCODE_7450 |
2970 | #define PPC860 PPC_OPCODE_860 |
2971 | #define PPCPS PPC_OPCODE_PPCPS |
2972 | #define PPCVEC PPC_OPCODE_ALTIVEC |
2973 | #define PPCVEC2 PPC_OPCODE_ALTIVEC2 |
2974 | #define PPCVEC3 PPC_OPCODE_ALTIVEC2 |
2975 | #define PPCVSX PPC_OPCODE_VSX |
2976 | #define PPCVSX2 PPC_OPCODE_VSX |
2977 | #define PPCVSX3 PPC_OPCODE_VSX3 |
2978 | #define POWER PPC_OPCODE_POWER |
2979 | #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 |
2980 | #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON |
2981 | #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON |
2982 | #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON |
2983 | #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 |
2984 | #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON |
2985 | #define MFDEC1 PPC_OPCODE_POWER |
2986 | #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN |
2987 | #define BOOKE PPC_OPCODE_BOOKE |
2988 | #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS |
2989 | #define PPCE300 PPC_OPCODE_E300 |
2990 | #define PPCSPE PPC_OPCODE_SPE |
2991 | #define PPCISEL PPC_OPCODE_ISEL |
2992 | #define PPCEFS PPC_OPCODE_EFS |
2993 | #define PPCBRLK PPC_OPCODE_BRLOCK |
2994 | #define PPCPMR PPC_OPCODE_PMR |
2995 | #define PPCTMR PPC_OPCODE_TMR |
2996 | #define PPCCHLK PPC_OPCODE_CACHELCK |
2997 | #define PPCRFMCI PPC_OPCODE_RFMCI |
2998 | #define E500MC PPC_OPCODE_E500MC |
2999 | #define PPCA2 PPC_OPCODE_A2 |
3000 | #define TITAN PPC_OPCODE_TITAN |
3001 | #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN |
3002 | #define E500 PPC_OPCODE_E500 |
3003 | #define E6500 PPC_OPCODE_E6500 |
3004 | #define PPCVLE PPC_OPCODE_VLE |
3005 | #define PPCHTM PPC_OPCODE_HTM |
3006 | #define E200Z4 PPC_OPCODE_E200Z4 |
3007 | /* The list of embedded processors that use the embedded operand ordering |
3008 | for the 3 operand dcbt and dcbtst instructions. */ |
3009 | #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \ |
3010 | | PPC_OPCODE_A2) |
3011 | |
3012 | |
3013 | |
3014 | /* The opcode table. |
3015 | |
3016 | The format of the opcode table is: |
3017 | |
3018 | NAME OPCODE MASK FLAGS ANTI {OPERANDS} |
3019 | |
3020 | NAME is the name of the instruction. |
3021 | OPCODE is the instruction opcode. |
3022 | MASK is the opcode mask; this is used to tell the disassembler |
3023 | which bits in the actual opcode must match OPCODE. |
3024 | FLAGS are flags indicating which processors support the instruction. |
3025 | ANTI indicates which processors don't support the instruction. |
3026 | OPERANDS is the list of operands. |
3027 | |
3028 | The disassembler reads the table in order and prints the first |
3029 | instruction which matches, so this table is sorted to put more |
3030 | specific instructions before more general instructions. |
3031 | |
3032 | This table must be sorted by major opcode. Please try to keep it |
3033 | vaguely sorted within major opcode too, except of course where |
3034 | constrained otherwise by disassembler operation. */ |
3035 | |
3036 | const struct powerpc_opcode powerpc_opcodes[] = { |
3037 | {"attn" , X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}}, |
3038 | {"tdlgti" , OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
3039 | {"tdllti" , OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
3040 | {"tdeqi" , OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
3041 | {"tdlgei" , OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
3042 | {"tdlnli" , OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
3043 | {"tdllei" , OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
3044 | {"tdlngi" , OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
3045 | {"tdgti" , OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
3046 | {"tdgei" , OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
3047 | {"tdnli" , OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
3048 | {"tdlti" , OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
3049 | {"tdlei" , OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
3050 | {"tdngi" , OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
3051 | {"tdnei" , OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
3052 | {"tdui" , OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
3053 | {"tdi" , OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}}, |
3054 | |
3055 | {"twlgti" , OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, |
3056 | {"tlgti" , OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, |
3057 | {"twllti" , OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, |
3058 | {"tllti" , OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, |
3059 | {"tweqi" , OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, |
3060 | {"teqi" , OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, |
3061 | {"twlgei" , OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, |
3062 | {"tlgei" , OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, |
3063 | {"twlnli" , OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, |
3064 | {"tlnli" , OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, |
3065 | {"twllei" , OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, |
3066 | {"tllei" , OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, |
3067 | {"twlngi" , OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, |
3068 | {"tlngi" , OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, |
3069 | {"twgti" , OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, |
3070 | {"tgti" , OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, |
3071 | {"twgei" , OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, |
3072 | {"tgei" , OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, |
3073 | {"twnli" , OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, |
3074 | {"tnli" , OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, |
3075 | {"twlti" , OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, |
3076 | {"tlti" , OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, |
3077 | {"twlei" , OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, |
3078 | {"tlei" , OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, |
3079 | {"twngi" , OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, |
3080 | {"tngi" , OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, |
3081 | {"twnei" , OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, |
3082 | {"tnei" , OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, |
3083 | {"twui" , OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, |
3084 | {"tui" , OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, |
3085 | {"twi" , OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}}, |
3086 | {"ti" , OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}}, |
3087 | |
3088 | {"ps_cmpu0" , X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, |
3089 | {"vaddubm" , VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3090 | {"vmul10cuq" , VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, |
3091 | {"vmaxub" , VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3092 | {"vrlb" , VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3093 | {"vcmpequb" , VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3094 | {"vcmpneb" , VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3095 | {"vmuloub" , VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3096 | {"vaddfp" , VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3097 | {"psq_lx" , XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, |
3098 | {"vmrghb" , VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3099 | {"psq_stx" , XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, |
3100 | {"vpkuhum" , VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3101 | {"mulhhwu" , XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}}, |
3102 | {"mulhhwu." , XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}}, |
3103 | {"ps_sum0" , A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3104 | {"ps_sum0." , A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3105 | {"ps_sum1" , A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3106 | {"ps_sum1." , A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3107 | {"ps_muls0" , A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
3108 | {"machhwu" , XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3109 | {"ps_muls0." , A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
3110 | {"machhwu." , XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3111 | {"ps_muls1" , A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
3112 | {"ps_muls1." , A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
3113 | {"ps_madds0" , A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3114 | {"ps_madds0." , A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3115 | {"ps_madds1" , A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3116 | {"ps_madds1." , A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3117 | {"vmhaddshs" , VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, |
3118 | {"vmhraddshs" , VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, |
3119 | {"vmladduhm" , VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, |
3120 | {"vmsumudm" , VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, |
3121 | {"ps_div" , A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, |
3122 | {"vmsumubm" , VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, |
3123 | {"ps_div." , A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, |
3124 | {"vmsummbm" , VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, |
3125 | {"vmsumuhm" , VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, |
3126 | {"vmsumuhs" , VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, |
3127 | {"ps_sub" , A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, |
3128 | {"vmsumshm" , VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, |
3129 | {"ps_sub." , A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, |
3130 | {"vmsumshs" , VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, |
3131 | {"ps_add" , A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, |
3132 | {"vsel" , VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, |
3133 | {"ps_add." , A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, |
3134 | {"vperm" , VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, |
3135 | {"vsldoi" , VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}}, |
3136 | {"vpermxor" , VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, |
3137 | {"ps_sel" , A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3138 | {"vmaddfp" , VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}}, |
3139 | {"ps_sel." , A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3140 | {"vnmsubfp" , VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}}, |
3141 | {"ps_res" , A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, |
3142 | {"maddhd" , VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, |
3143 | {"ps_res." , A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, |
3144 | {"maddhdu" , VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, |
3145 | {"ps_mul" , A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
3146 | {"ps_mul." , A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, |
3147 | {"maddld" , VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, |
3148 | {"ps_rsqrte" , A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, |
3149 | {"ps_rsqrte." , A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, |
3150 | {"ps_msub" , A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3151 | {"ps_msub." , A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3152 | {"ps_madd" , A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3153 | {"ps_madd." , A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3154 | {"vpermr" , VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, |
3155 | {"ps_nmsub" , A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3156 | {"vaddeuqm" , VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, |
3157 | {"ps_nmsub." , A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3158 | {"vaddecuq" , VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, |
3159 | {"ps_nmadd" , A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3160 | {"vsubeuqm" , VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, |
3161 | {"ps_nmadd." , A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, |
3162 | {"vsubecuq" , VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, |
3163 | {"ps_cmpo0" , X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, |
3164 | {"vadduhm" , VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3165 | {"vmul10ecuq" , VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3166 | {"vmaxuh" , VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3167 | {"vrlh" , VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3168 | {"vcmpequh" , VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3169 | {"vcmpneh" , VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3170 | {"vmulouh" , VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3171 | {"vsubfp" , VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3172 | {"psq_lux" , XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, |
3173 | {"vmrghh" , VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3174 | {"psq_stux" , XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, |
3175 | {"vpkuwum" , VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3176 | {"ps_neg" , XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, |
3177 | {"mulhhw" , XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}}, |
3178 | {"ps_neg." , XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, |
3179 | {"mulhhw." , XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}}, |
3180 | {"machhw" , XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3181 | {"machhw." , XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3182 | {"nmachhw" , XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3183 | {"nmachhw." , XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3184 | {"ps_cmpu1" , X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, |
3185 | {"vadduwm" , VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3186 | {"vmaxuw" , VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3187 | {"vrlw" , VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3188 | {"vrlwmi" , VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3189 | {"vcmpequw" , VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3190 | {"vcmpnew" , VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3191 | {"vmulouw" , VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3192 | {"vmuluwm" , VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3193 | {"vmrghw" , VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3194 | {"vpkuhus" , VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3195 | {"ps_mr" , XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, |
3196 | {"ps_mr." , XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, |
3197 | {"machhwsu" , XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3198 | {"machhwsu." , XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3199 | {"ps_cmpo1" , X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, |
3200 | {"vaddudm" , VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3201 | {"vmaxud" , VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3202 | {"vrld" , VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3203 | {"vrldmi" , VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3204 | {"vcmpeqfp" , VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3205 | {"vcmpequd" , VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3206 | {"vpkuwus" , VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3207 | {"machhws" , XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3208 | {"machhws." , XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3209 | {"nmachhws" , XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3210 | {"nmachhws." , XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3211 | {"vadduqm" , VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3212 | {"vmaxsb" , VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3213 | {"vslb" , VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3214 | {"vcmpnezb" , VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3215 | {"vmulosb" , VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3216 | {"vrefp" , VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
3217 | {"vmrglb" , VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3218 | {"vpkshus" , VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3219 | {"ps_nabs" , XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, |
3220 | {"mulchwu" , XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}}, |
3221 | {"ps_nabs." , XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, |
3222 | {"mulchwu." , XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}}, |
3223 | {"macchwu" , XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3224 | {"macchwu." , XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3225 | {"vaddcuq" , VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3226 | {"vmaxsh" , VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3227 | {"vslh" , VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3228 | {"vcmpnezh" , VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3229 | {"vmulosh" , VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3230 | {"vrsqrtefp" , VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
3231 | {"vmrglh" , VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3232 | {"vpkswus" , VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3233 | {"mulchw" , XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}}, |
3234 | {"mulchw." , XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}}, |
3235 | {"macchw" , XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3236 | {"macchw." , XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3237 | {"nmacchw" , XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3238 | {"nmacchw." , XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3239 | {"vaddcuw" , VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3240 | {"vmaxsw" , VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3241 | {"vslw" , VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3242 | {"vrlwnm" , VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3243 | {"vcmpnezw" , VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3244 | {"vmulosw" , VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3245 | {"vexptefp" , VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
3246 | {"vmrglw" , VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3247 | {"vpkshss" , VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3248 | {"macchwsu" , XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3249 | {"macchwsu." , XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3250 | {"vmaxsd" , VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3251 | {"vsl" , VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3252 | {"vrldnm" , VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3253 | {"vcmpgefp" , VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3254 | {"vlogefp" , VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
3255 | {"vpkswss" , VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3256 | {"macchws" , XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3257 | {"macchws." , XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3258 | {"nmacchws" , XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3259 | {"nmacchws." , XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3260 | {"evaddw" , VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3261 | {"vaddubs" , VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3262 | {"vmul10uq" , VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, |
3263 | {"evaddiw" , VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, |
3264 | {"vminub" , VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3265 | {"evsubfw" , VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3266 | {"evsubw" , VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}}, |
3267 | {"vsrb" , VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3268 | {"evsubifw" , VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}}, |
3269 | {"evsubiw" , VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, |
3270 | {"vcmpgtub" , VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3271 | {"evabs" , VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3272 | {"vmuleub" , VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3273 | {"evneg" , VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3274 | {"evextsb" , VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3275 | {"vrfin" , VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
3276 | {"evextsh" , VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3277 | {"evrndw" , VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3278 | {"vspltb" , VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}}, |
3279 | {"vextractub" , VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, |
3280 | {"evcntlzw" , VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3281 | {"evcntlsw" , VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3282 | {"vupkhsb" , VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
3283 | {"brinc" , VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3284 | {"ps_abs" , XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, |
3285 | {"ps_abs." , XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, |
3286 | {"evand" , VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3287 | {"evandc" , VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3288 | {"evxor" , VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3289 | {"evmr" , VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}}, |
3290 | {"evor" , VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3291 | {"evnor" , VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3292 | {"evnot" , VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}}, |
3293 | {"get" , APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, |
3294 | {"eveqv" , VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3295 | {"evorc" , VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3296 | {"evnand" , VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3297 | {"evsrwu" , VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3298 | {"evsrws" , VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3299 | {"evsrwiu" , VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, |
3300 | {"evsrwis" , VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, |
3301 | {"evslw" , VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3302 | {"evslwi" , VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, |
3303 | {"evrlw" , VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3304 | {"evsplati" , VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}}, |
3305 | {"evrlwi" , VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, |
3306 | {"evsplatfi" , VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}}, |
3307 | {"evmergehi" , VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3308 | {"evmergelo" , VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3309 | {"evmergehilo" , VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3310 | {"evmergelohi" , VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3311 | {"evcmpgtu" , VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, |
3312 | {"evcmpgts" , VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, |
3313 | {"evcmpltu" , VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, |
3314 | {"evcmplts" , VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, |
3315 | {"evcmpeq" , VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, |
3316 | {"cget" , APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, |
3317 | {"vadduhs" , VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3318 | {"vmul10euq" , VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3319 | {"vminuh" , VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3320 | {"vsrh" , VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3321 | {"vcmpgtuh" , VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3322 | {"vmuleuh" , VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3323 | {"vrfiz" , VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
3324 | {"vsplth" , VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}}, |
3325 | {"vextractuh" , VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, |
3326 | {"vupkhsh" , VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
3327 | {"nget" , APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, |
3328 | {"evsel" , EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}}, |
3329 | {"ncget" , APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, |
3330 | {"evfsadd" , VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3331 | {"vadduws" , VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3332 | {"evfssub" , VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3333 | {"vminuw" , VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3334 | {"evfsabs" , VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3335 | {"vsrw" , VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3336 | {"evfsnabs" , VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3337 | {"evfsneg" , VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3338 | {"vcmpgtuw" , VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3339 | {"vmuleuw" , VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3340 | {"evfsmul" , VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3341 | {"evfsdiv" , VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3342 | {"vrfip" , VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
3343 | {"evfscmpgt" , VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, |
3344 | {"vspltw" , VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}}, |
3345 | {"vextractuw" , VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, |
3346 | {"evfscmplt" , VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, |
3347 | {"evfscmpeq" , VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, |
3348 | {"vupklsb" , VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
3349 | {"evfscfui" , VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}}, |
3350 | {"evfscfsi" , VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}}, |
3351 | {"evfscfuf" , VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}}, |
3352 | {"evfscfsf" , VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}}, |
3353 | {"evfsctui" , VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}}, |
3354 | {"evfsctsi" , VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}}, |
3355 | {"evfsctuf" , VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}}, |
3356 | {"evfsctsf" , VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}}, |
3357 | {"evfsctuiz" , VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}}, |
3358 | {"put" , APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, |
3359 | {"evfsctsiz" , VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}}, |
3360 | {"evfststgt" , VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, |
3361 | {"evfststlt" , VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, |
3362 | {"evfststeq" , VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, |
3363 | {"cput" , APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, |
3364 | {"efsadd" , VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
3365 | {"efssub" , VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
3366 | {"vminud" , VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3367 | {"efsabs" , VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}}, |
3368 | {"vsr" , VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3369 | {"efsnabs" , VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}}, |
3370 | {"efsneg" , VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}}, |
3371 | {"vcmpgtfp" , VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3372 | {"vcmpgtud" , VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3373 | {"efsmul" , VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
3374 | {"efsdiv" , VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
3375 | {"vrfim" , VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
3376 | {"efscmpgt" , VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
3377 | {"vextractd" , VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, |
3378 | {"efscmplt" , VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
3379 | {"efscmpeq" , VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
3380 | {"vupklsh" , VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
3381 | {"efscfd" , VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3382 | {"efscfui" , VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3383 | {"efscfsi" , VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3384 | {"efscfuf" , VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3385 | {"efscfsf" , VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3386 | {"efsctui" , VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3387 | {"efsctsi" , VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3388 | {"efsctuf" , VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3389 | {"efsctsf" , VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3390 | {"efsctuiz" , VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3391 | {"nput" , APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, |
3392 | {"efsctsiz" , VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3393 | {"efststgt" , VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
3394 | {"efststlt" , VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
3395 | {"efststeq" , VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
3396 | {"efdadd" , VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
3397 | {"efdsub" , VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
3398 | {"efdcfuid" , VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3399 | {"efdcfsid" , VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3400 | {"efdabs" , VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}}, |
3401 | {"efdnabs" , VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}}, |
3402 | {"efdneg" , VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}}, |
3403 | {"efdmul" , VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
3404 | {"efddiv" , VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, |
3405 | {"efdctuidz" , VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3406 | {"efdctsidz" , VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3407 | {"efdcmpgt" , VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
3408 | {"efdcmplt" , VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
3409 | {"efdcmpeq" , VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
3410 | {"efdcfs" , VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3411 | {"efdcfui" , VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3412 | {"efdcfsi" , VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3413 | {"efdcfuf" , VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3414 | {"efdcfsf" , VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3415 | {"efdctui" , VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3416 | {"efdctsi" , VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3417 | {"efdctuf" , VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3418 | {"efdctsf" , VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3419 | {"efdctuiz" , VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3420 | {"ncput" , APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, |
3421 | {"efdctsiz" , VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}}, |
3422 | {"efdtstgt" , VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
3423 | {"efdtstlt" , VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
3424 | {"efdtsteq" , VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, |
3425 | {"evlddx" , VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3426 | {"vaddsbs" , VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3427 | {"evldd" , VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, |
3428 | {"evldwx" , VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3429 | {"vminsb" , VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3430 | {"evldw" , VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, |
3431 | {"evldhx" , VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3432 | {"vsrab" , VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3433 | {"evldh" , VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, |
3434 | {"vcmpgtsb" , VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3435 | {"evlhhesplatx" ,VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3436 | {"vmulesb" , VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3437 | {"evlhhesplat" , VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, |
3438 | {"vcfux" , VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, |
3439 | {"vcuxwfp" , VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, |
3440 | {"evlhhousplatx" ,VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3441 | {"vspltisb" , VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, |
3442 | {"vinsertb" , VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, |
3443 | {"evlhhousplat" ,VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, |
3444 | {"evlhhossplatx" ,VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3445 | {"vpkpx" , VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3446 | {"evlhhossplat" ,VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, |
3447 | {"mullhwu" , XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}}, |
3448 | {"evlwhex" , VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3449 | {"mullhwu." , XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}}, |
3450 | {"evlwhe" , VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, |
3451 | {"evlwhoux" , VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3452 | {"evlwhou" , VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, |
3453 | {"evlwhosx" , VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3454 | {"evlwhos" , VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, |
3455 | {"maclhwu" , XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3456 | {"evlwwsplatx" , VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3457 | {"maclhwu." , XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3458 | {"evlwwsplat" , VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, |
3459 | {"evlwhsplatx" , VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3460 | {"evlwhsplat" , VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, |
3461 | {"evstddx" , VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3462 | {"evstdd" , VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, |
3463 | {"evstdwx" , VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3464 | {"evstdw" , VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, |
3465 | {"evstdhx" , VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3466 | {"evstdh" , VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, |
3467 | {"evstwhex" , VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3468 | {"evstwhe" , VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, |
3469 | {"evstwhox" , VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3470 | {"evstwho" , VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, |
3471 | {"evstwwex" , VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3472 | {"evstwwe" , VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, |
3473 | {"evstwwox" , VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3474 | {"evstwwo" , VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, |
3475 | {"vaddshs" , VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3476 | {"bcdcpsgn." , VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3477 | {"vminsh" , VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3478 | {"vsrah" , VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3479 | {"vcmpgtsh" , VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3480 | {"vmulesh" , VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3481 | {"vcfsx" , VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, |
3482 | {"vcsxwfp" , VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, |
3483 | {"vspltish" , VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, |
3484 | {"vinserth" , VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, |
3485 | {"vupkhpx" , VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
3486 | {"mullhw" , XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}}, |
3487 | {"mullhw." , XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}}, |
3488 | {"maclhw" , XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3489 | {"maclhw." , XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3490 | {"nmaclhw" , XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3491 | {"nmaclhw." , XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3492 | {"vaddsws" , VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3493 | {"vminsw" , VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3494 | {"vsraw" , VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3495 | {"vcmpgtsw" , VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3496 | {"vmulesw" , VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3497 | {"vctuxs" , VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, |
3498 | {"vcfpuxws" , VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, |
3499 | {"vspltisw" , VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, |
3500 | {"vinsertw" , VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, |
3501 | {"maclhwsu" , XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3502 | {"maclhwsu." , XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3503 | {"vminsd" , VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3504 | {"vsrad" , VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3505 | {"vcmpbfp" , VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3506 | {"vcmpgtsd" , VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3507 | {"vctsxs" , VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, |
3508 | {"vcfpsxws" , VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, |
3509 | {"vinsertd" , VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, |
3510 | {"vupklpx" , VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}}, |
3511 | {"maclhws" , XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3512 | {"maclhws." , XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3513 | {"nmaclhws" , XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3514 | {"nmaclhws." , XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3515 | {"vsububm" , VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3516 | {"bcdadd." , VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, |
3517 | {"vavgub" , VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3518 | {"vabsdub" , VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3519 | {"evmhessf" , VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3520 | {"vand" , VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3521 | {"vcmpequb." , VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3522 | {"vcmpneb." , VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3523 | {"udi0fcm." , APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3524 | {"udi0fcm" , APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3525 | {"evmhossf" , VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3526 | {"vpmsumb" , VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3527 | {"evmheumi" , VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3528 | {"evmhesmi" , VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3529 | {"vmaxfp" , VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3530 | {"evmhesmf" , VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3531 | {"evmhoumi" , VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3532 | {"vslo" , VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3533 | {"evmhosmi" , VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3534 | {"evmhosmf" , VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3535 | {"machhwuo" , XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3536 | {"machhwuo." , XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3537 | {"ps_merge00" , XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, |
3538 | {"ps_merge00." , XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, |
3539 | {"evmhessfa" , VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3540 | {"evmhossfa" , VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3541 | {"evmheumia" , VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3542 | {"evmhesmia" , VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3543 | {"evmhesmfa" , VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3544 | {"evmhoumia" , VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3545 | {"evmhosmia" , VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3546 | {"evmhosmfa" , VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3547 | {"vsubuhm" , VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3548 | {"bcdsub." , VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, |
3549 | {"vavguh" , VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3550 | {"vabsduh" , VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3551 | {"vandc" , VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3552 | {"vcmpequh." , VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3553 | {"udi1fcm." , APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3554 | {"udi1fcm" , APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3555 | {"vcmpneh." , VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3556 | {"evmwhssf" , VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3557 | {"vpmsumh" , VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3558 | {"evmwlumi" , VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3559 | {"vminfp" , VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3560 | {"evmwhumi" , VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3561 | {"vsro" , VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3562 | {"evmwhsmi" , VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3563 | {"vpkudum" , VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3564 | {"evmwhsmf" , VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3565 | {"evmwssf" , VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3566 | {"machhwo" , XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3567 | {"evmwumi" , VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3568 | {"machhwo." , XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3569 | {"evmwsmi" , VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3570 | {"evmwsmf" , VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3571 | {"nmachhwo" , XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3572 | {"nmachhwo." , XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3573 | {"ps_merge01" , XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, |
3574 | {"ps_merge01." , XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, |
3575 | {"evmwhssfa" , VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3576 | {"evmwlumia" , VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3577 | {"evmwhumia" , VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3578 | {"evmwhsmia" , VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3579 | {"evmwhsmfa" , VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3580 | {"evmwssfa" , VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3581 | {"evmwumia" , VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3582 | {"evmwsmia" , VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3583 | {"evmwsmfa" , VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3584 | {"vsubuwm" , VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3585 | {"bcdus." , VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3586 | {"vavguw" , VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3587 | {"vabsduw" , VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3588 | {"vmr" , VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}}, |
3589 | {"vor" , VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3590 | {"vcmpnew." , VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3591 | {"vpmsumw" , VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3592 | {"vcmpequw." , VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3593 | {"udi2fcm." , APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3594 | {"udi2fcm" , APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3595 | {"machhwsuo" , XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3596 | {"machhwsuo." , XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3597 | {"ps_merge10" , XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, |
3598 | {"ps_merge10." , XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, |
3599 | {"vsubudm" , VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3600 | {"evaddusiaaw" , VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3601 | {"bcds." , VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, |
3602 | {"evaddssiaaw" , VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3603 | {"evsubfusiaaw" ,VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3604 | {"evsubfssiaaw" ,VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3605 | {"evmra" , VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3606 | {"vxor" , VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3607 | {"evdivws" , VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3608 | {"vcmpeqfp." , VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3609 | {"udi3fcm." , APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3610 | {"vcmpequd." , VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3611 | {"udi3fcm" , APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3612 | {"evdivwu" , VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3613 | {"vpmsumd" , VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3614 | {"evaddumiaaw" , VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3615 | {"evaddsmiaaw" , VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3616 | {"evsubfumiaaw" ,VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3617 | {"evsubfsmiaaw" ,VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}}, |
3618 | {"vpkudus" , VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3619 | {"machhwso" , XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3620 | {"machhwso." , XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3621 | {"nmachhwso" , XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3622 | {"nmachhwso." , XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3623 | {"ps_merge11" , XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, |
3624 | {"ps_merge11." , XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, |
3625 | {"vsubuqm" , VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3626 | {"evmheusiaaw" , VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3627 | {"bcdtrunc." , VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, |
3628 | {"evmhessiaaw" , VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3629 | {"vavgsb" , VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3630 | {"evmhessfaaw" , VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3631 | {"evmhousiaaw" , VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3632 | {"vnot" , VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}}, |
3633 | {"vnor" , VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3634 | {"evmhossiaaw" , VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3635 | {"udi4fcm." , APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3636 | {"udi4fcm" , APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3637 | {"vcmpnezb." , VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3638 | {"evmhossfaaw" , VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3639 | {"evmheumiaaw" , VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3640 | {"vcipher" , VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3641 | {"vcipherlast" , VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3642 | {"evmhesmiaaw" , VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3643 | {"evmhesmfaaw" , VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3644 | {"vgbbd" , VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, |
3645 | {"evmhoumiaaw" , VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3646 | {"evmhosmiaaw" , VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3647 | {"evmhosmfaaw" , VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3648 | {"macchwuo" , XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3649 | {"macchwuo." , XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3650 | {"evmhegumiaa" , VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3651 | {"evmhegsmiaa" , VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3652 | {"evmhegsmfaa" , VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3653 | {"evmhogumiaa" , VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3654 | {"evmhogsmiaa" , VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3655 | {"evmhogsmfaa" , VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3656 | {"vsubcuq" , VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3657 | {"evmwlusiaaw" , VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3658 | {"bcdutrunc." , VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3659 | {"evmwlssiaaw" , VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3660 | {"vavgsh" , VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3661 | {"vorc" , VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3662 | {"udi5fcm." , APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3663 | {"udi5fcm" , APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3664 | {"vcmpnezh." , VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3665 | {"vncipher" , VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3666 | {"evmwlumiaaw" , VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3667 | {"vncipherlast" ,VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3668 | {"evmwlsmiaaw" , VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3669 | {"vbpermq" , VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3670 | {"vpksdus" , VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3671 | {"evmwssfaa" , VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3672 | {"macchwo" , XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3673 | {"evmwumiaa" , VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3674 | {"macchwo." , XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3675 | {"evmwsmiaa" , VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3676 | {"evmwsmfaa" , VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3677 | {"nmacchwo" , XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3678 | {"nmacchwo." , XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3679 | {"evmheusianw" , VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3680 | {"vsubcuw" , VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3681 | {"evmhessianw" , VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3682 | {"bcdctsq." , VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
3683 | {"bcdcfsq." , VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, |
3684 | {"bcdctz." , VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, |
3685 | {"bcdctn." , VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
3686 | {"bcdcfz." , VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, |
3687 | {"bcdcfn." , VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, |
3688 | {"bcdsetsgn." , VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, |
3689 | {"vavgsw" , VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3690 | {"evmhessfanw" , VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3691 | {"vnand" , VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3692 | {"evmhousianw" , VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3693 | {"evmhossianw" , VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3694 | {"udi6fcm." , APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3695 | {"udi6fcm" , APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3696 | {"vcmpnezw." , VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3697 | {"evmhossfanw" , VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3698 | {"evmheumianw" , VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3699 | {"evmhesmianw" , VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3700 | {"evmhesmfanw" , VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3701 | {"evmhoumianw" , VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3702 | {"evmhosmianw" , VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3703 | {"evmhosmfanw" , VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3704 | {"macchwsuo" , XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3705 | {"macchwsuo." , XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3706 | {"evmhegumian" , VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3707 | {"evmhegsmian" , VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3708 | {"evmhegsmfan" , VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3709 | {"evmhogumian" , VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3710 | {"evmhogsmian" , VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3711 | {"evmhogsmfan" , VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3712 | {"evmwlusianw" , VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3713 | {"bcdsr." , VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, |
3714 | {"evmwlssianw" , VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3715 | {"vsld" , VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3716 | {"vcmpgefp." , VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3717 | {"udi7fcm." , APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3718 | {"udi7fcm" , APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, |
3719 | {"vsbox" , VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}}, |
3720 | {"evmwlumianw" , VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3721 | {"evmwlsmianw" , VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3722 | {"vbpermd" , VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3723 | {"vpksdss" , VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3724 | {"evmwssfan" , VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3725 | {"macchwso" , XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3726 | {"evmwumian" , VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3727 | {"macchwso." , XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3728 | {"evmwsmian" , VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3729 | {"evmwsmfan" , VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, |
3730 | {"nmacchwso" , XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3731 | {"nmacchwso." , XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3732 | {"vsububs" , VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3733 | {"vclzlsbb" , VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, |
3734 | {"vctzlsbb" , VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, |
3735 | {"vnegw" , VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
3736 | {"vnegd" , VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
3737 | {"vprtybw" , VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
3738 | {"vprtybd" , VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
3739 | {"vprtybq" , VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
3740 | {"vextsb2w" , VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
3741 | {"vextsh2w" , VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
3742 | {"vextsb2d" , VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
3743 | {"vextsh2d" , VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
3744 | {"vextsw2d" , VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
3745 | {"vctzb" , VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
3746 | {"vctzh" , VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
3747 | {"vctzw" , VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
3748 | {"vctzd" , VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, |
3749 | {"mfvscr" , VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}}, |
3750 | {"vcmpgtub." , VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3751 | {"udi8fcm." , APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3752 | {"udi8fcm" , APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3753 | {"vsum4ubs" , VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3754 | {"vextublx" , VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, |
3755 | {"vsubuhs" , VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3756 | {"mtvscr" , VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}}, |
3757 | {"vcmpgtuh." , VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3758 | {"vsum4shs" , VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3759 | {"udi9fcm." , APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3760 | {"udi9fcm" , APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3761 | {"vextuhlx" , VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, |
3762 | {"vupkhsw" , VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, |
3763 | {"vsubuws" , VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3764 | {"vshasigmaw" , VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}}, |
3765 | {"veqv" , VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3766 | {"vcmpgtuw." , VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3767 | {"udi10fcm." , APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3768 | {"udi10fcm" , APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3769 | {"vsum2sws" , VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3770 | {"vmrgow" , VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3771 | {"vextuwlx" , VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, |
3772 | {"vshasigmad" , VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}}, |
3773 | {"vsrd" , VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3774 | {"vcmpgtfp." , VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3775 | {"udi11fcm." , APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3776 | {"vcmpgtud." , VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3777 | {"udi11fcm" , APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3778 | {"vupklsw" , VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, |
3779 | {"vsubsbs" , VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3780 | {"vclzb" , VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, |
3781 | {"vpopcntb" , VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, |
3782 | {"vsrv" , VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3783 | {"vcmpgtsb." , VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3784 | {"udi12fcm." , APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3785 | {"udi12fcm" , APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3786 | {"vsum4sbs" , VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3787 | {"vextubrx" , VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, |
3788 | {"maclhwuo" , XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3789 | {"maclhwuo." , XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3790 | {"vsubshs" , VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3791 | {"vclzh" , VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, |
3792 | {"vpopcnth" , VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, |
3793 | {"vslv" , VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, |
3794 | {"vcmpgtsh." , VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3795 | {"vextuhrx" , VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, |
3796 | {"udi13fcm." , APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3797 | {"udi13fcm" , APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3798 | {"maclhwo" , XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3799 | {"maclhwo." , XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3800 | {"nmaclhwo" , XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3801 | {"nmaclhwo." , XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3802 | {"vsubsws" , VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3803 | {"vclzw" , VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, |
3804 | {"vpopcntw" , VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, |
3805 | {"vcmpgtsw." , VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3806 | {"udi14fcm." , APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3807 | {"udi14fcm" , APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3808 | {"vsumsws" , VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3809 | {"vmrgew" , VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3810 | {"vextuwrx" , VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, |
3811 | {"maclhwsuo" , XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3812 | {"maclhwsuo." , XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3813 | {"vclzd" , VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, |
3814 | {"vpopcntd" , VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, |
3815 | {"vcmpbfp." , VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, |
3816 | {"udi15fcm." , APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3817 | {"vcmpgtsd." , VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, |
3818 | {"udi15fcm" , APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, |
3819 | {"maclhwso" , XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3820 | {"maclhwso." , XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3821 | {"nmaclhwso" , XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3822 | {"nmaclhwso." , XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, |
3823 | {"dcbz_l" , X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}}, |
3824 | |
3825 | {"mulli" , OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, |
3826 | {"muli" , OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, |
3827 | |
3828 | {"subfic" , OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, |
3829 | {"sfi" , OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, |
3830 | |
3831 | {"dozi" , OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}}, |
3832 | |
3833 | {"cmplwi" , OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}}, |
3834 | {"cmpldi" , OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}}, |
3835 | {"cmpli" , OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}}, |
3836 | {"cmpli" , OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}}, |
3837 | |
3838 | {"cmpwi" , OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}}, |
3839 | {"cmpdi" , OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}}, |
3840 | {"cmpi" , OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}}, |
3841 | {"cmpi" , OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}}, |
3842 | |
3843 | {"addic" , OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, |
3844 | {"ai" , OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, |
3845 | {"subic" , OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, |
3846 | |
3847 | {"addic." , OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, |
3848 | {"ai." , OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, |
3849 | {"subic." , OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, |
3850 | |
3851 | {"li" , OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}}, |
3852 | {"lil" , OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}}, |
3853 | {"addi" , OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}}, |
3854 | {"cal" , OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, |
3855 | {"subi" , OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}}, |
3856 | {"la" , OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, |
3857 | |
3858 | {"lis" , OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}}, |
3859 | {"liu" , OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}}, |
3860 | {"addis" , OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, |
3861 | {"cau" , OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, |
3862 | {"subis" , OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}}, |
3863 | |
3864 | {"bdnz-" , BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, |
3865 | {"bdnz+" , BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, |
3866 | {"bdnz" , BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}}, |
3867 | {"bdn" , BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}}, |
3868 | {"bdnzl-" , BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, |
3869 | {"bdnzl+" , BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, |
3870 | {"bdnzl" , BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}}, |
3871 | {"bdnl" , BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}}, |
3872 | {"bdnza-" , BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, |
3873 | {"bdnza+" , BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, |
3874 | {"bdnza" , BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}}, |
3875 | {"bdna" , BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}}, |
3876 | {"bdnzla-" , BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, |
3877 | {"bdnzla+" , BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, |
3878 | {"bdnzla" , BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}}, |
3879 | {"bdnla" , BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}}, |
3880 | {"bdz-" , BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, |
3881 | {"bdz+" , BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, |
3882 | {"bdz" , BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}}, |
3883 | {"bdzl-" , BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}}, |
3884 | {"bdzl+" , BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}}, |
3885 | {"bdzl" , BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}}, |
3886 | {"bdza-" , BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, |
3887 | {"bdza+" , BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, |
3888 | {"bdza" , BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}}, |
3889 | {"bdzla-" , BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}}, |
3890 | {"bdzla+" , BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}}, |
3891 | {"bdzla" , BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}}, |
3892 | |
3893 | {"bge-" , BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3894 | {"bge+" , BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3895 | {"bge" , BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
3896 | {"bnl-" , BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3897 | {"bnl+" , BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3898 | {"bnl" , BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
3899 | {"bgel-" , BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3900 | {"bgel+" , BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3901 | {"bgel" , BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
3902 | {"bnll-" , BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3903 | {"bnll+" , BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3904 | {"bnll" , BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
3905 | {"bgea-" , BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
3906 | {"bgea+" , BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
3907 | {"bgea" , BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
3908 | {"bnla-" , BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
3909 | {"bnla+" , BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
3910 | {"bnla" , BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
3911 | {"bgela-" , BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
3912 | {"bgela+" , BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
3913 | {"bgela" , BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
3914 | {"bnlla-" , BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
3915 | {"bnlla+" , BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
3916 | {"bnlla" , BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
3917 | {"ble-" , BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3918 | {"ble+" , BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3919 | {"ble" , BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
3920 | {"bng-" , BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3921 | {"bng+" , BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3922 | {"bng" , BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
3923 | {"blel-" , BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3924 | {"blel+" , BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3925 | {"blel" , BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
3926 | {"bngl-" , BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3927 | {"bngl+" , BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3928 | {"bngl" , BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
3929 | {"blea-" , BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
3930 | {"blea+" , BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
3931 | {"blea" , BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
3932 | {"bnga-" , BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
3933 | {"bnga+" , BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
3934 | {"bnga" , BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
3935 | {"blela-" , BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
3936 | {"blela+" , BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
3937 | {"blela" , BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
3938 | {"bngla-" , BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
3939 | {"bngla+" , BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
3940 | {"bngla" , BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
3941 | {"bne-" , BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3942 | {"bne+" , BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3943 | {"bne" , BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
3944 | {"bnel-" , BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3945 | {"bnel+" , BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3946 | {"bnel" , BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
3947 | {"bnea-" , BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
3948 | {"bnea+" , BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
3949 | {"bnea" , BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
3950 | {"bnela-" , BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
3951 | {"bnela+" , BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
3952 | {"bnela" , BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
3953 | {"bns-" , BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3954 | {"bns+" , BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3955 | {"bns" , BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
3956 | {"bnu-" , BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3957 | {"bnu+" , BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3958 | {"bnu" , BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, |
3959 | {"bnsl-" , BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3960 | {"bnsl+" , BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3961 | {"bnsl" , BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
3962 | {"bnul-" , BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3963 | {"bnul+" , BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3964 | {"bnul" , BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, |
3965 | {"bnsa-" , BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
3966 | {"bnsa+" , BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
3967 | {"bnsa" , BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
3968 | {"bnua-" , BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
3969 | {"bnua+" , BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
3970 | {"bnua" , BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, |
3971 | {"bnsla-" , BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
3972 | {"bnsla+" , BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
3973 | {"bnsla" , BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
3974 | {"bnula-" , BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
3975 | {"bnula+" , BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
3976 | {"bnula" , BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, |
3977 | |
3978 | {"blt-" , BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3979 | {"blt+" , BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3980 | {"blt" , BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
3981 | {"bltl-" , BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3982 | {"bltl+" , BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3983 | {"bltl" , BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
3984 | {"blta-" , BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
3985 | {"blta+" , BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
3986 | {"blta" , BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
3987 | {"bltla-" , BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
3988 | {"bltla+" , BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
3989 | {"bltla" , BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
3990 | {"bgt-" , BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3991 | {"bgt+" , BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3992 | {"bgt" , BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
3993 | {"bgtl-" , BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
3994 | {"bgtl+" , BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
3995 | {"bgtl" , BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
3996 | {"bgta-" , BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
3997 | {"bgta+" , BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
3998 | {"bgta" , BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
3999 | {"bgtla-" , BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
4000 | {"bgtla+" , BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
4001 | {"bgtla" , BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
4002 | {"beq-" , BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
4003 | {"beq+" , BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
4004 | {"beq" , BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
4005 | {"beql-" , BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
4006 | {"beql+" , BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
4007 | {"beql" , BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
4008 | {"beqa-" , BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
4009 | {"beqa+" , BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
4010 | {"beqa" , BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
4011 | {"beqla-" , BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
4012 | {"beqla+" , BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
4013 | {"beqla" , BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
4014 | {"bso-" , BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
4015 | {"bso+" , BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
4016 | {"bso" , BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
4017 | {"bun-" , BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
4018 | {"bun+" , BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
4019 | {"bun" , BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, |
4020 | {"bsol-" , BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
4021 | {"bsol+" , BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
4022 | {"bsol" , BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}}, |
4023 | {"bunl-" , BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}}, |
4024 | {"bunl+" , BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}}, |
4025 | {"bunl" , BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}}, |
4026 | {"bsoa-" , BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
4027 | {"bsoa+" , BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
4028 | {"bsoa" , BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
4029 | {"buna-" , BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
4030 | {"buna+" , BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
4031 | {"buna" , BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, |
4032 | {"bsola-" , BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
4033 | {"bsola+" , BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
4034 | {"bsola" , BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}}, |
4035 | {"bunla-" , BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}}, |
4036 | {"bunla+" , BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}}, |
4037 | {"bunla" , BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}}, |
4038 | |
4039 | {"bdnzf-" , BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, |
4040 | {"bdnzf+" , BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, |
4041 | {"bdnzf" , BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, |
4042 | {"bdnzfl-" , BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, |
4043 | {"bdnzfl+" , BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, |
4044 | {"bdnzfl" , BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, |
4045 | {"bdnzfa-" , BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, |
4046 | {"bdnzfa+" , BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, |
4047 | {"bdnzfa" , BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, |
4048 | {"bdnzfla-" , BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, |
4049 | {"bdnzfla+" , BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, |
4050 | {"bdnzfla" , BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, |
4051 | {"bdzf-" , BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, |
4052 | {"bdzf+" , BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, |
4053 | {"bdzf" , BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, |
4054 | {"bdzfl-" , BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, |
4055 | {"bdzfl+" , BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, |
4056 | {"bdzfl" , BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, |
4057 | {"bdzfa-" , BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, |
4058 | {"bdzfa+" , BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, |
4059 | {"bdzfa" , BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, |
4060 | {"bdzfla-" , BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, |
4061 | {"bdzfla+" , BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, |
4062 | {"bdzfla" , BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, |
4063 | |
4064 | {"bf-" , BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, |
4065 | {"bf+" , BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, |
4066 | {"bf" , BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, |
4067 | {"bbf" , BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, |
4068 | {"bfl-" , BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, |
4069 | {"bfl+" , BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, |
4070 | {"bfl" , BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, |
4071 | {"bbfl" , BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, |
4072 | {"bfa-" , BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, |
4073 | {"bfa+" , BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, |
4074 | {"bfa" , BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, |
4075 | {"bbfa" , BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, |
4076 | {"bfla-" , BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, |
4077 | {"bfla+" , BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, |
4078 | {"bfla" , BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, |
4079 | {"bbfla" , BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, |
4080 | |
4081 | {"bdnzt-" , BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, |
4082 | {"bdnzt+" , BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, |
4083 | {"bdnzt" , BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, |
4084 | {"bdnztl-" , BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, |
4085 | {"bdnztl+" , BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, |
4086 | {"bdnztl" , BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, |
4087 | {"bdnzta-" , BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, |
4088 | {"bdnzta+" , BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, |
4089 | {"bdnzta" , BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, |
4090 | {"bdnztla-" , BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, |
4091 | {"bdnztla+" , BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, |
4092 | {"bdnztla" , BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, |
4093 | {"bdzt-" , BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, |
4094 | {"bdzt+" , BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, |
4095 | {"bdzt" , BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, |
4096 | {"bdztl-" , BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}}, |
4097 | {"bdztl+" , BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}}, |
4098 | {"bdztl" , BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}}, |
4099 | {"bdzta-" , BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, |
4100 | {"bdzta+" , BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, |
4101 | {"bdzta" , BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, |
4102 | {"bdztla-" , BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}}, |
4103 | {"bdztla+" , BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}}, |
4104 | {"bdztla" , BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}}, |
4105 | |
4106 | {"bt-" , BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, |
4107 | {"bt+" , BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, |
4108 | {"bt" , BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, |
4109 | {"bbt" , BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, |
4110 | {"btl-" , BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}}, |
4111 | {"btl+" , BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}}, |
4112 | {"btl" , BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}}, |
4113 | {"bbtl" , BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}}, |
4114 | {"bta-" , BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, |
4115 | {"bta+" , BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, |
4116 | {"bta" , BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, |
4117 | {"bbta" , BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, |
4118 | {"btla-" , BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}}, |
4119 | {"btla+" , BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}}, |
4120 | {"btla" , BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, |
4121 | {"bbtla" , BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, |
4122 | |
4123 | {"bc-" , B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}}, |
4124 | {"bc+" , B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}}, |
4125 | {"bc" , B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}}, |
4126 | {"bcl-" , B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}}, |
4127 | {"bcl+" , B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}}, |
4128 | {"bcl" , B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}}, |
4129 | {"bca-" , B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}}, |
4130 | {"bca+" , B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}}, |
4131 | {"bca" , B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, |
4132 | {"bcla-" , B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}}, |
4133 | {"bcla+" , B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}}, |
4134 | {"bcla" , B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, |
4135 | |
4136 | {"svc" , SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, |
4137 | {"svcl" , SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, |
4138 | {"sc" , SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}}, |
4139 | {"svca" , SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}}, |
4140 | {"svcla" , SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}}, |
4141 | |
4142 | {"b" , B(18,0,0), B_MASK, COM, PPCVLE, {LI}}, |
4143 | {"bl" , B(18,0,1), B_MASK, COM, PPCVLE, {LI}}, |
4144 | {"ba" , B(18,1,0), B_MASK, COM, PPCVLE, {LIA}}, |
4145 | {"bla" , B(18,1,1), B_MASK, COM, PPCVLE, {LIA}}, |
4146 | |
4147 | {"mcrf" , XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, |
4148 | |
4149 | {"addpcis" , DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}}, |
4150 | {"subpcis" , DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}}, |
4151 | |
4152 | {"bdnzlr" , XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, |
4153 | {"bdnzlr-" , XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
4154 | {"bdnzlrl" , XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, |
4155 | {"bdnzlrl-" , XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
4156 | {"bdnzlr+" , XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
4157 | {"bdnzlrl+" , XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
4158 | {"bdzlr" , XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, |
4159 | {"bdzlr-" , XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
4160 | {"bdzlrl" , XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, |
4161 | {"bdzlrl-" , XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
4162 | {"bdzlr+" , XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
4163 | {"bdzlrl+" , XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}}, |
4164 | {"blr" , XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, |
4165 | {"br" , XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}}, |
4166 | {"blrl" , XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}}, |
4167 | {"brl" , XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}}, |
4168 | {"bdnzlr-" , XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, |
4169 | {"bdnzlrl-" , XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, |
4170 | {"bdnzlr+" , XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, |
4171 | {"bdnzlrl+" , XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, |
4172 | {"bdzlr-" , XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, |
4173 | {"bdzlrl-" , XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, |
4174 | {"bdzlr+" , XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, |
4175 | {"bdzlrl+" , XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}}, |
4176 | |
4177 | {"bgelr" , XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4178 | {"bgelr-" , XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4179 | {"bger" , XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4180 | {"bnllr" , XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4181 | {"bnllr-" , XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4182 | {"bnlr" , XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4183 | {"bgelrl" , XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4184 | {"bgelrl-" , XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4185 | {"bgerl" , XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4186 | {"bnllrl" , XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4187 | {"bnllrl-" , XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4188 | {"bnlrl" , XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4189 | {"blelr" , XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4190 | {"blelr-" , XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4191 | {"bler" , XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4192 | {"bnglr" , XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4193 | {"bnglr-" , XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4194 | {"bngr" , XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4195 | {"blelrl" , XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4196 | {"blelrl-" , XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4197 | {"blerl" , XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4198 | {"bnglrl" , XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4199 | {"bnglrl-" , XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4200 | {"bngrl" , XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4201 | {"bnelr" , XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4202 | {"bnelr-" , XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4203 | {"bner" , XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4204 | {"bnelrl" , XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4205 | {"bnelrl-" , XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4206 | {"bnerl" , XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4207 | {"bnslr" , XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4208 | {"bnslr-" , XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4209 | {"bnsr" , XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4210 | {"bnulr" , XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4211 | {"bnulr-" , XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4212 | {"bnslrl" , XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4213 | {"bnslrl-" , XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4214 | {"bnsrl" , XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4215 | {"bnulrl" , XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4216 | {"bnulrl-" , XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4217 | {"bgelr+" , XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4218 | {"bnllr+" , XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4219 | {"bgelrl+" , XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4220 | {"bnllrl+" , XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4221 | {"blelr+" , XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4222 | {"bnglr+" , XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4223 | {"blelrl+" , XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4224 | {"bnglrl+" , XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4225 | {"bnelr+" , XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4226 | {"bnelrl+" , XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4227 | {"bnslr+" , XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4228 | {"bnulr+" , XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4229 | {"bnslrl+" , XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4230 | {"bnulrl+" , XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4231 | {"bgelr-" , XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4232 | {"bnllr-" , XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4233 | {"bgelrl-" , XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4234 | {"bnllrl-" , XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4235 | {"blelr-" , XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4236 | {"bnglr-" , XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4237 | {"blelrl-" , XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4238 | {"bnglrl-" , XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4239 | {"bnelr-" , XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4240 | {"bnelrl-" , XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4241 | {"bnslr-" , XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4242 | {"bnulr-" , XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4243 | {"bnslrl-" , XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4244 | {"bnulrl-" , XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4245 | {"bgelr+" , XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4246 | {"bnllr+" , XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4247 | {"bgelrl+" , XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4248 | {"bnllrl+" , XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4249 | {"blelr+" , XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4250 | {"bnglr+" , XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4251 | {"blelrl+" , XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4252 | {"bnglrl+" , XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4253 | {"bnelr+" , XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4254 | {"bnelrl+" , XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4255 | {"bnslr+" , XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4256 | {"bnulr+" , XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4257 | {"bnslrl+" , XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4258 | {"bnulrl+" , XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4259 | {"bltlr" , XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4260 | {"bltlr-" , XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4261 | {"bltr" , XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4262 | {"bltlrl" , XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4263 | {"bltlrl-" , XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4264 | {"bltrl" , XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4265 | {"bgtlr" , XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4266 | {"bgtlr-" , XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4267 | {"bgtr" , XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4268 | {"bgtlrl" , XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4269 | {"bgtlrl-" , XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4270 | {"bgtrl" , XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4271 | {"beqlr" , XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4272 | {"beqlr-" , XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4273 | {"beqr" , XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4274 | {"beqlrl" , XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4275 | {"beqlrl-" , XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4276 | {"beqrl" , XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4277 | {"bsolr" , XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4278 | {"bsolr-" , XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4279 | {"bsor" , XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4280 | {"bunlr" , XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4281 | {"bunlr-" , XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4282 | {"bsolrl" , XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4283 | {"bsolrl-" , XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4284 | {"bsorl" , XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}}, |
4285 | {"bunlrl" , XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4286 | {"bunlrl-" , XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4287 | {"bltlr+" , XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4288 | {"bltlrl+" , XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4289 | {"bgtlr+" , XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4290 | {"bgtlrl+" , XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4291 | {"beqlr+" , XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4292 | {"beqlrl+" , XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4293 | {"bsolr+" , XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4294 | {"bunlr+" , XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4295 | {"bsolrl+" , XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4296 | {"bunlrl+" , XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4297 | {"bltlr-" , XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4298 | {"bltlrl-" , XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4299 | {"bgtlr-" , XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4300 | {"bgtlrl-" , XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4301 | {"beqlr-" , XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4302 | {"beqlrl-" , XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4303 | {"bsolr-" , XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4304 | {"bunlr-" , XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4305 | {"bsolrl-" , XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4306 | {"bunlrl-" , XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4307 | {"bltlr+" , XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4308 | {"bltlrl+" , XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4309 | {"bgtlr+" , XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4310 | {"bgtlrl+" , XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4311 | {"beqlr+" , XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4312 | {"beqlrl+" , XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4313 | {"bsolr+" , XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4314 | {"bunlr+" , XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4315 | {"bsolrl+" , XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4316 | {"bunlrl+" , XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4317 | |
4318 | {"bdnzflr" , XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
4319 | {"bdnzflr-" , XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4320 | {"bdnzflrl" , XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
4321 | {"bdnzflrl-" ,XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4322 | {"bdnzflr+" , XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4323 | {"bdnzflrl+" ,XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4324 | {"bdzflr" , XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
4325 | {"bdzflr-" , XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4326 | {"bdzflrl" , XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
4327 | {"bdzflrl-" , XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4328 | {"bdzflr+" , XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4329 | {"bdzflrl+" , XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4330 | {"bflr" , XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
4331 | {"bflr-" , XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4332 | {"bbfr" , XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, |
4333 | {"bflrl" , XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
4334 | {"bflrl-" , XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4335 | {"bbfrl" , XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, |
4336 | {"bflr+" , XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4337 | {"bflrl+" , XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4338 | {"bflr-" , XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
4339 | {"bflrl-" , XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
4340 | {"bflr+" , XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
4341 | {"bflrl+" , XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
4342 | {"bdnztlr" , XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
4343 | {"bdnztlr-" , XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4344 | {"bdnztlrl" , XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
4345 | {"bdnztlrl-" , XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4346 | {"bdnztlr+" , XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4347 | {"bdnztlrl+" , XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4348 | {"bdztlr" , XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
4349 | {"bdztlr-" , XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4350 | {"bdztlrl" , XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
4351 | {"bdztlrl-" , XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4352 | {"bdztlr+" , XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4353 | {"bdztlrl+" , XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4354 | {"btlr" , XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
4355 | {"btlr-" , XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4356 | {"bbtr" , XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, |
4357 | {"btlrl" , XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
4358 | {"btlrl-" , XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4359 | {"bbtrl" , XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}}, |
4360 | {"btlr+" , XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4361 | {"btlrl+" , XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4362 | {"btlr-" , XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
4363 | {"btlrl-" , XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
4364 | {"btlr+" , XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
4365 | {"btlrl+" , XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
4366 | |
4367 | {"bclr-" , XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, |
4368 | {"bclrl-" , XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, |
4369 | {"bclr+" , XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, |
4370 | {"bclrl+" , XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, |
4371 | {"bclr" , XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, |
4372 | {"bcr" , XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, |
4373 | {"bclrl" , XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, |
4374 | {"bcrl" , XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, |
4375 | |
4376 | {"rfid" , XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}}, |
4377 | |
4378 | {"crnot" , XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}}, |
4379 | {"crnor" , XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
4380 | {"rfmci" , X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}}, |
4381 | |
4382 | {"rfdi" , XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}}, |
4383 | {"rfi" , XL(19,50), 0xffffffff, COM, PPCVLE, {0}}, |
4384 | {"rfci" , XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}}, |
4385 | |
4386 | {"rfsvc" , XL(19,82), 0xffffffff, POWER, PPCVLE, {0}}, |
4387 | |
4388 | {"rfgi" , XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}}, |
4389 | |
4390 | {"crandc" , XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
4391 | |
4392 | {"rfebb" , XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}}, |
4393 | |
4394 | {"isync" , XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}}, |
4395 | {"ics" , XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}}, |
4396 | |
4397 | {"crclr" , XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}}, |
4398 | {"crxor" , XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
4399 | |
4400 | {"dnh" , X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}}, |
4401 | |
4402 | {"crnand" , XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
4403 | |
4404 | {"crand" , XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
4405 | |
4406 | {"hrfid" , XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}}, |
4407 | |
4408 | {"crset" , XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}}, |
4409 | {"creqv" , XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
4410 | |
4411 | {"urfid" , XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}}, |
4412 | {"stop" , XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}}, |
4413 | |
4414 | {"doze" , XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, |
4415 | |
4416 | {"crorc" , XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
4417 | |
4418 | {"nap" , XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, |
4419 | |
4420 | {"crmove" , XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}}, |
4421 | {"cror" , XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, |
4422 | |
4423 | {"sleep" , XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, |
4424 | {"rvwinkle" , XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, |
4425 | |
4426 | {"bctr" , XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}}, |
4427 | {"bctrl" , XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}}, |
4428 | |
4429 | {"bgectr" , XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4430 | {"bgectr-" , XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4431 | {"bnlctr" , XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4432 | {"bnlctr-" , XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4433 | {"bgectrl" , XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4434 | {"bgectrl-" ,XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4435 | {"bnlctrl" , XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4436 | {"bnlctrl-" ,XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4437 | {"blectr" , XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4438 | {"blectr-" , XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4439 | {"bngctr" , XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4440 | {"bngctr-" , XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4441 | {"blectrl" , XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4442 | {"blectrl-" ,XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4443 | {"bngctrl" , XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4444 | {"bngctrl-" ,XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4445 | {"bnectr" , XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4446 | {"bnectr-" , XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4447 | {"bnectrl" , XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4448 | {"bnectrl-" ,XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4449 | {"bnsctr" , XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4450 | {"bnsctr-" , XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4451 | {"bnuctr" , XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4452 | {"bnuctr-" , XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4453 | {"bnsctrl" , XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4454 | {"bnsctrl-" ,XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4455 | {"bnuctrl" , XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4456 | {"bnuctrl-" ,XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4457 | {"bgectr+" , XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4458 | {"bnlctr+" , XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4459 | {"bgectrl+" ,XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4460 | {"bnlctrl+" ,XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4461 | {"blectr+" , XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4462 | {"bngctr+" , XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4463 | {"blectrl+" ,XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4464 | {"bngctrl+" ,XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4465 | {"bnectr+" , XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4466 | {"bnectrl+" ,XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4467 | {"bnsctr+" , XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4468 | {"bnuctr+" , XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4469 | {"bnsctrl+" ,XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4470 | {"bnuctrl+" ,XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4471 | {"bgectr-" , XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4472 | {"bnlctr-" , XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4473 | {"bgectrl-" ,XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4474 | {"bnlctrl-" ,XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4475 | {"blectr-" , XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4476 | {"bngctr-" , XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4477 | {"blectrl-" ,XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4478 | {"bngctrl-" ,XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4479 | {"bnectr-" , XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4480 | {"bnectrl-" ,XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4481 | {"bnsctr-" , XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4482 | {"bnuctr-" , XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4483 | {"bnsctrl-" ,XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4484 | {"bnuctrl-" ,XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4485 | {"bgectr+" , XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4486 | {"bnlctr+" , XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4487 | {"bgectrl+" ,XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4488 | {"bnlctrl+" ,XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4489 | {"blectr+" , XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4490 | {"bngctr+" , XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4491 | {"blectrl+" ,XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4492 | {"bngctrl+" ,XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4493 | {"bnectr+" , XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4494 | {"bnectrl+" ,XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4495 | {"bnsctr+" , XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4496 | {"bnuctr+" , XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4497 | {"bnsctrl+" ,XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4498 | {"bnuctrl+" ,XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4499 | {"bltctr" , XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4500 | {"bltctr-" , XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4501 | {"bltctrl" , XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4502 | {"bltctrl-" ,XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4503 | {"bgtctr" , XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4504 | {"bgtctr-" , XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4505 | {"bgtctrl" , XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4506 | {"bgtctrl-" ,XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4507 | {"beqctr" , XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4508 | {"beqctr-" , XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4509 | {"beqctrl" , XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4510 | {"beqctrl-" ,XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4511 | {"bsoctr" , XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4512 | {"bsoctr-" , XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4513 | {"bunctr" , XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4514 | {"bunctr-" , XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4515 | {"bsoctrl" , XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4516 | {"bsoctrl-" ,XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4517 | {"bunctrl" , XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}}, |
4518 | {"bunctrl-" ,XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4519 | {"bltctr+" , XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4520 | {"bltctrl+" ,XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4521 | {"bgtctr+" , XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4522 | {"bgtctrl+" ,XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4523 | {"beqctr+" , XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4524 | {"beqctrl+" ,XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4525 | {"bsoctr+" , XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4526 | {"bunctr+" , XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4527 | {"bsoctrl+" ,XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4528 | {"bunctrl+" ,XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}}, |
4529 | {"bltctr-" , XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4530 | {"bltctrl-" ,XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4531 | {"bgtctr-" , XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4532 | {"bgtctrl-" ,XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4533 | {"beqctr-" , XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4534 | {"beqctrl-" ,XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4535 | {"bsoctr-" , XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4536 | {"bunctr-" , XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4537 | {"bsoctrl-" ,XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4538 | {"bunctrl-" ,XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4539 | {"bltctr+" , XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4540 | {"bltctrl+" ,XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4541 | {"bgtctr+" , XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4542 | {"bgtctrl+" ,XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4543 | {"beqctr+" , XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4544 | {"beqctrl+" ,XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4545 | {"bsoctr+" , XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4546 | {"bunctr+" , XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4547 | {"bsoctrl+" ,XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4548 | {"bunctrl+" ,XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}}, |
4549 | |
4550 | {"bfctr" , XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
4551 | {"bfctr-" , XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4552 | {"bfctrl" , XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
4553 | {"bfctrl-" , XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4554 | {"bfctr+" , XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4555 | {"bfctrl+" , XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4556 | {"bfctr-" , XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
4557 | {"bfctrl-" , XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
4558 | {"bfctr+" , XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
4559 | {"bfctrl+" , XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
4560 | {"btctr" , XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
4561 | {"btctr-" , XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4562 | {"btctrl" , XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}}, |
4563 | {"btctrl-" , XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4564 | {"btctr+" , XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4565 | {"btctrl+" , XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}}, |
4566 | {"btctr-" , XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
4567 | {"btctrl-" , XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
4568 | {"btctr+" , XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
4569 | {"btctrl+" , XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, |
4570 | |
4571 | {"bcctr-" , XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, |
4572 | {"bcctrl-" , XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, |
4573 | {"bcctr+" , XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, |
4574 | {"bcctrl+" , XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, |
4575 | {"bcctr" , XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, |
4576 | {"bcc" , XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, |
4577 | {"bcctrl" , XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, |
4578 | {"bccl" , XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, |
4579 | |
4580 | {"bctar-" , XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, |
4581 | {"bctarl-" , XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, |
4582 | {"bctar+" , XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, |
4583 | {"bctarl+" , XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, |
4584 | {"bctar" , XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, |
4585 | {"bctarl" , XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, |
4586 | |
4587 | {"rlwimi" , M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, |
4588 | {"rlimi" , M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, |
4589 | |
4590 | {"rlwimi." , M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, |
4591 | {"rlimi." , M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, |
4592 | |
4593 | {"rotlwi" , MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, |
4594 | {"clrlwi" , MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, |
4595 | {"rlwinm" , M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, |
4596 | {"rlinm" , M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, |
4597 | {"rotlwi." , MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, |
4598 | {"clrlwi." , MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, |
4599 | {"rlwinm." , M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, |
4600 | {"rlinm." , M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, |
4601 | |
4602 | {"rlmi" , M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, |
4603 | {"rlmi." , M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, |
4604 | |
4605 | {"rotlw" , MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, |
4606 | {"rlwnm" , M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, |
4607 | {"rlnm" , M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, |
4608 | {"rotlw." , MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, |
4609 | {"rlwnm." , M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, |
4610 | {"rlnm." , M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, |
4611 | |
4612 | {"nop" , OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}}, |
4613 | {"ori" , OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, |
4614 | {"oril" , OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, |
4615 | |
4616 | {"oris" , OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, |
4617 | {"oriu" , OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, |
4618 | |
4619 | {"xnop" , OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}}, |
4620 | {"xori" , OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, |
4621 | {"xoril" , OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, |
4622 | |
4623 | {"xoris" , OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, |
4624 | {"xoriu" , OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, |
4625 | |
4626 | {"andi." , OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, |
4627 | {"andil." , OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, |
4628 | |
4629 | {"andis." , OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, |
4630 | {"andiu." , OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, |
4631 | |
4632 | {"rotldi" , MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, |
4633 | {"clrldi" , MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, |
4634 | {"rldicl" , MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, |
4635 | {"rotldi." , MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, |
4636 | {"clrldi." , MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, |
4637 | {"rldicl." , MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, |
4638 | |
4639 | {"rldicr" , MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, |
4640 | {"rldicr." , MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, |
4641 | |
4642 | {"rldic" , MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, |
4643 | {"rldic." , MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, |
4644 | |
4645 | {"rldimi" , MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, |
4646 | {"rldimi." , MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, |
4647 | |
4648 | {"rotld" , MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, |
4649 | {"rldcl" , MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, |
4650 | {"rotld." , MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, |
4651 | {"rldcl." , MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, |
4652 | |
4653 | {"rldcr" , MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, |
4654 | {"rldcr." , MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, |
4655 | |
4656 | {"cmpw" , XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, |
4657 | {"cmpd" , XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, |
4658 | {"cmp" , X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, |
4659 | {"cmp" , X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, |
4660 | |
4661 | {"twlgt" , XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
4662 | {"tlgt" , XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, |
4663 | {"twllt" , XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
4664 | {"tllt" , XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, |
4665 | {"tweq" , XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
4666 | {"teq" , XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}}, |
4667 | {"twlge" , XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
4668 | {"tlge" , XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, |
4669 | {"twlnl" , XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
4670 | {"tlnl" , XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}}, |
4671 | {"twlle" , XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
4672 | {"tlle" , XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, |
4673 | {"twlng" , XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
4674 | {"tlng" , XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}}, |
4675 | {"twgt" , XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
4676 | {"tgt" , XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, |
4677 | {"twge" , XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
4678 | {"tge" , XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, |
4679 | {"twnl" , XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
4680 | {"tnl" , XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}}, |
4681 | {"twlt" , XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
4682 | {"tlt" , XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, |
4683 | {"twle" , XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
4684 | {"tle" , XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, |
4685 | {"twng" , XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
4686 | {"tng" , XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}}, |
4687 | {"twne" , XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
4688 | {"tne" , XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}}, |
4689 | {"trap" , XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}}, |
4690 | {"twu" , XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}}, |
4691 | {"tu" , XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}}, |
4692 | {"tw" , X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}}, |
4693 | {"t" , X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}}, |
4694 | |
4695 | {"lvsl" , X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, |
4696 | {"lvebx" , X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, |
4697 | {"lbfcmx" , APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
4698 | |
4699 | {"subfc" , XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
4700 | {"sf" , XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
4701 | {"subc" , XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, |
4702 | {"subfc." , XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
4703 | {"sf." , XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
4704 | {"subc." , XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, |
4705 | |
4706 | {"mulhdu" , XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
4707 | {"mulhdu." , XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
4708 | |
4709 | {"addc" , XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
4710 | {"a" , XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
4711 | {"addc." , XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
4712 | {"a." , XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
4713 | |
4714 | {"mulhwu" , XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
4715 | {"mulhwu." , XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, |
4716 | |
4717 | {"lxsiwzx" , X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, |
4718 | |
4719 | {"isellt" , X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, |
4720 | |
4721 | {"tlbilxlpid" , XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}}, |
4722 | {"tlbilxpid" , XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}}, |
4723 | {"tlbilxva" , XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
4724 | {"tlbilx" , X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}}, |
4725 | |
4726 | {"mfcr" , XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}}, |
4727 | {"mfocrf" , XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}}, |
4728 | |
4729 | {"lwarx" , X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}}, |
4730 | |
4731 | {"ldx" , X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}}, |
4732 | |
4733 | {"icbt" , X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}}, |
4734 | |
4735 | {"lwzx" , X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, |
4736 | {"lx" , X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}}, |
4737 | |
4738 | {"slw" , XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, |
4739 | {"sl" , XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, |
4740 | {"slw." , XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, |
4741 | {"sl." , XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, |
4742 | |
4743 | {"cntlzw" , XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, |
4744 | {"cntlz" , XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, |
4745 | {"cntlzw." , XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, |
4746 | {"cntlz." , XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, |
4747 | |
4748 | {"sld" , XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}}, |
4749 | {"sld." , XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}}, |
4750 | |
4751 | {"and" , XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}}, |
4752 | {"and." , XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}}, |
4753 | |
4754 | {"maskg" , XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}}, |
4755 | {"maskg." , XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}}, |
4756 | |
4757 | {"ldepx" , X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
4758 | |
4759 | {"waitasec" , X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}}, |
4760 | {"wait" , X(31,30), XWC_MASK, POWER9, 0, {WC}}, |
4761 | |
4762 | {"lwepx" , X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
4763 | |
4764 | {"cmplw" , XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, |
4765 | {"cmpld" , XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, |
4766 | {"cmpl" , X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, |
4767 | {"cmpl" , X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, |
4768 | |
4769 | {"lvsr" , X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, |
4770 | {"lvehx" , X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, |
4771 | {"lhfcmx" , APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
4772 | |
4773 | {"mviwsplt" , X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}}, |
4774 | |
4775 | {"iselgt" , X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, |
4776 | |
4777 | {"lvewx" , X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, |
4778 | |
4779 | {"addg6s" , XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}}, |
4780 | |
4781 | {"lxsiwax" , X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, |
4782 | |
4783 | {"iseleq" , X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, |
4784 | |
4785 | {"isel" , XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}}, |
4786 | |
4787 | {"subf" , XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
4788 | {"sub" , XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}}, |
4789 | {"subf." , XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, |
4790 | {"sub." , XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}}, |
4791 | |
4792 | {"mfvsrd" , X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, |
4793 | {"mffprd" , X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}}, |
4794 | {"mfvrd" , X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}}, |
4795 | {"eratilx" , X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}}, |
4796 | |
4797 | {"lbarx" , X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, |
4798 | |
4799 | {"ldux" , X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}}, |
4800 | |
4801 | {"dcbst" , X(31,54), XRT_MASK, PPC, 0, {RA0, RB}}, |
4802 | |
4803 | {"lwzux" , X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}}, |
4804 | {"lux" , X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}}, |
4805 | |
4806 | {"cntlzd" , XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}}, |
4807 | {"cntlzd." , XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}}, |
4808 | |
4809 | {"andc" , XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}}, |
4810 | {"andc." , XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}}, |
4811 | |
4812 | {"waitrsv" , X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, |
4813 | {"waitimpl" , X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}}, |
4814 | {"wait" , X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}}, |
4815 | |
4816 | {"dcbstep" , XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
4817 | |
4818 | {"tdlgt" , XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}}, |
4819 | {"tdllt" , XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}}, |
4820 | {"tdeq" , XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}}, |
4821 | {"tdlge" , XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}}, |
4822 | {"tdlnl" , XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}}, |
4823 | {"tdlle" , XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}}, |
4824 | {"tdlng" , XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}}, |
4825 | {"tdgt" , XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}}, |
4826 | {"tdge" , XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}}, |
4827 | {"tdnl" , XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}}, |
4828 | {"tdlt" , XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}}, |
4829 | {"tdle" , XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}}, |
4830 | {"tdng" , XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}}, |
4831 | {"tdne" , XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}}, |
4832 | {"tdu" , XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}}, |
4833 | {"td" , X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}}, |
4834 | |
4835 | {"lwfcmx" , APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
4836 | {"mulhd" , XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
4837 | {"mulhd." , XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
4838 | |
4839 | {"mulhw" , XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
4840 | {"mulhw." , XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, |
4841 | |
4842 | {"dlmzb" , XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}}, |
4843 | {"dlmzb." , XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}}, |
4844 | |
4845 | {"mtsrd" , X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}}, |
4846 | |
4847 | {"mfmsr" , X(31,83), XRARB_MASK, COM, 0, {RT}}, |
4848 | |
4849 | {"ldarx" , X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}}, |
4850 | |
4851 | {"dcbfl" , XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}}, |
4852 | {"dcbf" , X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}}, |
4853 | |
4854 | {"lbzx" , X(31,87), X_MASK, COM, 0, {RT, RA0, RB}}, |
4855 | |
4856 | {"lbepx" , X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
4857 | |
4858 | {"dni" , XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}}, |
4859 | |
4860 | {"lvx" , X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, |
4861 | {"lqfcmx" , APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
4862 | |
4863 | {"neg" , XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}}, |
4864 | {"neg." , XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}}, |
4865 | |
4866 | {"mul" , XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
4867 | {"mul." , XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, |
4868 | |
4869 | {"mvidsplt" , X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}}, |
4870 | |
4871 | {"mtsrdin" , X(31,114), XRA_MASK, PPC64, 0, {RS, RB}}, |
4872 | |
4873 | {"mffprwz" , X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}}, |
4874 | {"mfvrwz" , X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}}, |
4875 | {"mfvsrwz" , X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, |
4876 | |
4877 | {"lharx" , X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, |
4878 | |
4879 | {"clf" , X(31,118), XTO_MASK, POWER, 0, {RA, RB}}, |
4880 | |
4881 | {"lbzux" , X(31,119), X_MASK, COM, 0, {RT, RAL, RB}}, |
4882 | |
4883 | {"popcntb" , X(31,122), XRB_MASK, POWER5, 0, {RA, RS}}, |
4884 | |
4885 | {"not" , XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}}, |
4886 | {"nor" , XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}}, |
4887 | {"not." , XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}}, |
4888 | {"nor." , XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}}, |
4889 | |
4890 | {"dcbfep" , XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
4891 | |
4892 | {"setb" , X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}}, |
4893 | |
4894 | {"wrtee" , X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}}, |
4895 | |
4896 | {"dcbtstls" , X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, |
4897 | |
4898 | {"stvebx" , X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, |
4899 | {"stbfcmx" , APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
4900 | |
4901 | {"subfe" , XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
4902 | {"sfe" , XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
4903 | {"subfe." , XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
4904 | {"sfe." , XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
4905 | |
4906 | {"adde" , XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
4907 | {"ae" , XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
4908 | {"adde." , XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
4909 | {"ae." , XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
4910 | |
4911 | {"stxsiwx" , X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, |
4912 | |
4913 | {"msgsndp" , XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}}, |
4914 | {"dcbtstlse" , X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, |
4915 | |
4916 | {"mtcr" , XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}}, |
4917 | {"mtcrf" , XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}}, |
4918 | {"mtocrf" , XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}}, |
4919 | |
4920 | {"mtmsr" , X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}}, |
4921 | |
4922 | {"mtsle" , X(31,147), XRTLRARB_MASK, POWER8, 0, {L}}, |
4923 | |
4924 | {"eratsx" , XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}}, |
4925 | {"eratsx." , XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, |
4926 | |
4927 | {"stdx" , X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}}, |
4928 | |
4929 | {"stwcx." , XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}}, |
4930 | |
4931 | {"stwx" , X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, |
4932 | {"stx" , X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}}, |
4933 | |
4934 | {"slq" , XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}}, |
4935 | {"slq." , XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}}, |
4936 | |
4937 | {"sle" , XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}}, |
4938 | {"sle." , XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}}, |
4939 | |
4940 | {"prtyw" , X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}}, |
4941 | |
4942 | {"stdepx" , X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
4943 | |
4944 | {"stwepx" , X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
4945 | |
4946 | {"wrteei" , X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}}, |
4947 | |
4948 | {"dcbtls" , X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, |
4949 | |
4950 | {"stvehx" , X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, |
4951 | {"sthfcmx" , APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
4952 | |
4953 | {"addex" , ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}}, |
4954 | |
4955 | {"msgclrp" , XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}}, |
4956 | {"dcbtlse" , X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, |
4957 | |
4958 | {"mtmsrd" , X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}}, |
4959 | |
4960 | {"mtvsrd" , X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, |
4961 | {"mtfprd" , X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, |
4962 | {"mtvrd" , X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, |
4963 | {"eratre" , X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}}, |
4964 | |
4965 | {"stdux" , X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}}, |
4966 | |
4967 | {"stqcx." , XRC(31,182,1), X_MASK, POWER8, 0, {RSQ, RA0, RB}}, |
4968 | {"wchkall" , X(31,182), X_MASK, PPCA2, 0, {OBF}}, |
4969 | |
4970 | {"stwux" , X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}}, |
4971 | {"stux" , X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, |
4972 | |
4973 | {"sliq" , XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}}, |
4974 | {"sliq." , XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}}, |
4975 | |
4976 | {"prtyd" , X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}}, |
4977 | |
4978 | {"cmprb" , X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}}, |
4979 | |
4980 | {"icblq." , XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}}, |
4981 | |
4982 | {"stvewx" , X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, |
4983 | {"stwfcmx" , APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
4984 | |
4985 | {"subfze" , XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
4986 | {"sfze" , XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, |
4987 | {"subfze." , XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
4988 | {"sfze." , XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, |
4989 | |
4990 | {"addze" , XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
4991 | {"aze" , XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, |
4992 | {"addze." , XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
4993 | {"aze." , XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, |
4994 | |
4995 | {"msgsnd" , XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, |
4996 | |
4997 | {"mtsr" , X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}}, |
4998 | |
4999 | {"mtfprwa" , X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, |
5000 | {"mtvrwa" , X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, |
5001 | {"mtvsrwa" , X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, |
5002 | {"eratwe" , X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}}, |
5003 | |
5004 | {"ldawx." , XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, |
5005 | |
5006 | {"stdcx." , XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}}, |
5007 | |
5008 | {"stbx" , X(31,215), X_MASK, COM, 0, {RS, RA0, RB}}, |
5009 | |
5010 | {"sllq" , XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}}, |
5011 | {"sllq." , XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}}, |
5012 | |
5013 | {"sleq" , XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}}, |
5014 | {"sleq." , XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}}, |
5015 | |
5016 | {"stbepx" , X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
5017 | |
5018 | {"cmpeqb" , X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}}, |
5019 | |
5020 | {"icblc" , X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, |
5021 | |
5022 | {"stvx" , X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, |
5023 | {"stqfcmx" , APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
5024 | |
5025 | {"subfme" , XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
5026 | {"sfme" , XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, |
5027 | {"subfme." , XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
5028 | {"sfme." , XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, |
5029 | |
5030 | {"mulld" , XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
5031 | {"mulld." , XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
5032 | |
5033 | {"addme" , XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
5034 | {"ame" , XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, |
5035 | {"addme." , XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
5036 | {"ame." , XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, |
5037 | |
5038 | {"mullw" , XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5039 | {"muls" , XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
5040 | {"mullw." , XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5041 | {"muls." , XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
5042 | |
5043 | {"icblce" , X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}}, |
5044 | {"msgclr" , XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, |
5045 | {"mtsrin" , X(31,242), XRA_MASK, PPC, NON32, {RS, RB}}, |
5046 | {"mtsri" , X(31,242), XRA_MASK, POWER, NON32, {RS, RB}}, |
5047 | |
5048 | {"mtfprwz" , X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, |
5049 | {"mtvrwz" , X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, |
5050 | {"mtvsrwz" , X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, |
5051 | |
5052 | {"dcbtstt" , XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, |
5053 | {"dcbtst" , X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, |
5054 | {"dcbtst" , X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, |
5055 | {"dcbtst" , X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, |
5056 | |
5057 | {"stbux" , X(31,247), X_MASK, COM, 0, {RS, RAS, RB}}, |
5058 | |
5059 | {"slliq" , XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}}, |
5060 | {"slliq." , XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}}, |
5061 | |
5062 | {"bpermd" , X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}}, |
5063 | |
5064 | {"dcbtstep" , XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
5065 | |
5066 | {"mfdcrx" , X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}}, |
5067 | {"mfdcrx." , XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}}, |
5068 | |
5069 | {"lvexbx" , X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, |
5070 | |
5071 | {"icbt" , X(31,262), XRT_MASK, PPC403, 0, {RA, RB}}, |
5072 | |
5073 | {"lvepxl" , X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, |
5074 | |
5075 | {"ldfcmx" , APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
5076 | {"doz" , XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
5077 | {"doz." , XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, |
5078 | |
5079 | {"modud" , X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}}, |
5080 | |
5081 | {"add" , XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5082 | {"cax" , XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
5083 | {"add." , XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5084 | {"cax." , XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
5085 | |
5086 | {"moduw" , X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}}, |
5087 | |
5088 | {"lxvx" , X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}}, |
5089 | {"lxvl" , X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
5090 | |
5091 | {"ehpriv" , X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}}, |
5092 | |
5093 | {"tlbiel" , X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}}, |
5094 | {"tlbiel" , X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}}, |
5095 | |
5096 | {"mfapidi" , X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}}, |
5097 | |
5098 | {"lqarx" , X(31,276), XEH_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}}, |
5099 | |
5100 | {"lscbx" , XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}}, |
5101 | {"lscbx." , XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}}, |
5102 | |
5103 | {"dcbtt" , XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, |
5104 | {"dcbt" , X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, |
5105 | {"dcbt" , X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, |
5106 | {"dcbt" , X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, |
5107 | |
5108 | {"lhzx" , X(31,279), X_MASK, COM, 0, {RT, RA0, RB}}, |
5109 | |
5110 | {"cdtbcd" , X(31,282), XRB_MASK, POWER6, 0, {RA, RS}}, |
5111 | |
5112 | {"eqv" , XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}}, |
5113 | {"eqv." , XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}}, |
5114 | |
5115 | {"lhepx" , X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
5116 | |
5117 | {"mfdcrux" , X(31,291), X_MASK, PPC464, 0, {RS, RA}}, |
5118 | |
5119 | {"lvexhx" , X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, |
5120 | {"lvepx" , X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, |
5121 | |
5122 | {"lxvll" , X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
5123 | |
5124 | {"mfbhrbe" , X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}}, |
5125 | |
5126 | {"tlbie" , X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}}, |
5127 | {"tlbie" , X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}}, |
5128 | {"tlbie" , X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}}, |
5129 | {"tlbi" , X(31,306), XRT_MASK, POWER, 0, {RA0, RB}}, |
5130 | |
5131 | {"mfvsrld" , X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}}, |
5132 | |
5133 | {"ldmx" , X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}}, |
5134 | |
5135 | {"eciwx" , X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, |
5136 | |
5137 | {"lhzux" , X(31,311), X_MASK, COM, 0, {RT, RAL, RB}}, |
5138 | |
5139 | {"cbcdtd" , X(31,314), XRB_MASK, POWER6, 0, {RA, RS}}, |
5140 | |
5141 | {"xor" , XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}}, |
5142 | {"xor." , XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}}, |
5143 | |
5144 | {"dcbtep" , XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
5145 | |
5146 | {"mfexisr" , XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}}, |
5147 | {"mfexier" , XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}}, |
5148 | {"mfbr0" , XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}}, |
5149 | {"mfbr1" , XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}}, |
5150 | {"mfbr2" , XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}}, |
5151 | {"mfbr3" , XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}}, |
5152 | {"mfbr4" , XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}}, |
5153 | {"mfbr5" , XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}}, |
5154 | {"mfbr6" , XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}}, |
5155 | {"mfbr7" , XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}}, |
5156 | {"mfbear" , XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}}, |
5157 | {"mfbesr" , XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}}, |
5158 | {"mfiocr" , XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}}, |
5159 | {"mfdmacr0" , XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}}, |
5160 | {"mfdmact0" , XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}}, |
5161 | {"mfdmada0" , XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}}, |
5162 | {"mfdmasa0" , XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}}, |
5163 | {"mfdmacc0" , XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}}, |
5164 | {"mfdmacr1" , XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}}, |
5165 | {"mfdmact1" , XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}}, |
5166 | {"mfdmada1" , XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}}, |
5167 | {"mfdmasa1" , XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}}, |
5168 | {"mfdmacc1" , XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}}, |
5169 | {"mfdmacr2" , XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}}, |
5170 | {"mfdmact2" , XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}}, |
5171 | {"mfdmada2" , XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}}, |
5172 | {"mfdmasa2" , XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}}, |
5173 | {"mfdmacc2" , XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}}, |
5174 | {"mfdmacr3" , XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}}, |
5175 | {"mfdmact3" , XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}}, |
5176 | {"mfdmada3" , XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}}, |
5177 | {"mfdmasa3" , XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}}, |
5178 | {"mfdmacc3" , XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}}, |
5179 | {"mfdmasr" , XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}}, |
5180 | {"mfdcr" , X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}}, |
5181 | {"mfdcr." , XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}}, |
5182 | |
5183 | {"lvexwx" , X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, |
5184 | |
5185 | {"dcread" , X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}}, |
5186 | |
5187 | {"div" , XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
5188 | {"div." , XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, |
5189 | |
5190 | {"lxvdsx" , X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, |
5191 | |
5192 | {"mfpmr" , X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}}, |
5193 | {"mftmr" , X(31,366), X_MASK, PPCTMR|E6500, 0, {RT, TMR}}, |
5194 | |
5195 | {"slbsync" , X(31,338), 0xffffffff, POWER9, 0, {0}}, |
5196 | |
5197 | {"mfmq" , XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}}, |
5198 | {"mfxer" , XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}}, |
5199 | {"mfrtcu" , XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}}, |
5200 | {"mfrtcl" , XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}}, |
5201 | {"mfdec" , XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}}, |
5202 | {"mflr" , XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}}, |
5203 | {"mfctr" , XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}}, |
5204 | {"mfdscr" , XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}}, |
5205 | {"mftid" , XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}}, |
5206 | {"mfdsisr" , XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}}, |
5207 | {"mfdar" , XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}}, |
5208 | {"mfdec" , XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}}, |
5209 | {"mfsdr0" , XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}}, |
5210 | {"mfsdr1" , XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}}, |
5211 | {"mfsrr0" , XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}}, |
5212 | {"mfsrr1" , XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}}, |
5213 | {"mfcfar" , XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}}, |
5214 | {"mfpid" , XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}}, |
5215 | {"mfcsrr0" , XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}}, |
5216 | {"mfcsrr1" , XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}}, |
5217 | {"mfdear" , XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}}, |
5218 | {"mfesr" , XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}}, |
5219 | {"mfivpr" , XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}}, |
5220 | {"mfctrl" , XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}}, |
5221 | {"mfcmpa" , XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}}, |
5222 | {"mfcmpb" , XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}}, |
5223 | {"mfcmpc" , XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}}, |
5224 | {"mfcmpd" , XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}}, |
5225 | {"mficr" , XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}}, |
5226 | {"mfder" , XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}}, |
5227 | {"mfcounta" , XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}}, |
5228 | {"mfcountb" , XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}}, |
5229 | {"mfcmpe" , XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}}, |
5230 | {"mfcmpf" , XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}}, |
5231 | {"mfcmpg" , XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}}, |
5232 | {"mfcmph" , XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}}, |
5233 | {"mflctrl1" , XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}}, |
5234 | {"mflctrl2" , XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}}, |
5235 | {"mfictrl" , XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}}, |
5236 | {"mfbar" , XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}}, |
5237 | {"mfvrsave" , XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}}, |
5238 | {"mfusprg0" , XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}}, |
5239 | {"mfsprg" , XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}}, |
5240 | {"mfsprg4" , XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, |
5241 | {"mfsprg5" , XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, |
5242 | {"mfsprg6" , XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, |
5243 | {"mfsprg7" , XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, |
5244 | {"mftbu" , XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, |
5245 | {"mftb" , X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}}, |
5246 | {"mftbl" , XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}}, |
5247 | {"mfsprg0" , XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}}, |
5248 | {"mfsprg1" , XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}}, |
5249 | {"mfsprg2" , XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}}, |
5250 | {"mfsprg3" , XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}}, |
5251 | {"mfasr" , XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}}, |
5252 | {"mfear" , XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}}, |
5253 | {"mfpir" , XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}}, |
5254 | {"mfpvr" , XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}}, |
5255 | {"mfdbsr" , XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}}, |
5256 | {"mfdbcr0" , XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}}, |
5257 | {"mfdbcr1" , XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}}, |
5258 | {"mfdbcr2" , XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}}, |
5259 | {"mfiac1" , XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}}, |
5260 | {"mfiac2" , XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}}, |
5261 | {"mfiac3" , XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}}, |
5262 | {"mfiac4" , XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}}, |
5263 | {"mfdac1" , XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}}, |
5264 | {"mfdac2" , XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}}, |
5265 | {"mfdvc1" , XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}}, |
5266 | {"mfdvc2" , XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}}, |
5267 | {"mftsr" , XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}}, |
5268 | {"mftcr" , XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}}, |
5269 | {"mfivor0" , XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}}, |
5270 | {"mfivor1" , XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}}, |
5271 | {"mfivor2" , XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}}, |
5272 | {"mfivor3" , XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}}, |
5273 | {"mfivor4" , XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}}, |
5274 | {"mfivor5" , XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}}, |
5275 | {"mfivor6" , XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}}, |
5276 | {"mfivor7" , XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}}, |
5277 | {"mfivor8" , XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}}, |
5278 | {"mfivor9" , XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}}, |
5279 | {"mfivor10" , XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}}, |
5280 | {"mfivor11" , XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}}, |
5281 | {"mfivor12" , XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}}, |
5282 | {"mfivor13" , XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}}, |
5283 | {"mfivor14" , XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}}, |
5284 | {"mfivor15" , XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}}, |
5285 | {"mfspefscr" , XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}}, |
5286 | {"mfbbear" , XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}}, |
5287 | {"mfbbtar" , XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}}, |
5288 | {"mfivor32" , XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}}, |
5289 | {"mfibatu" , XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, |
5290 | {"mfivor33" , XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}}, |
5291 | {"mfibatl" , XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, |
5292 | {"mfivor34" , XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}}, |
5293 | {"mfivor35" , XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}}, |
5294 | {"mfdbatu" , XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, |
5295 | {"mfdbatl" , XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}}, |
5296 | {"mfic_cst" , XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}}, |
5297 | {"mfic_adr" , XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}}, |
5298 | {"mfic_dat" , XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}}, |
5299 | {"mfdc_cst" , XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}}, |
5300 | {"mfdc_adr" , XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}}, |
5301 | {"mfdc_dat" , XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}}, |
5302 | {"mfmcsrr0" , XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}}, |
5303 | {"mfmcsrr1" , XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}}, |
5304 | {"mfmcsr" , XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}}, |
5305 | {"mfmcar" , XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}}, |
5306 | {"mfdpdr" , XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}}, |
5307 | {"mfdpir" , XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}}, |
5308 | {"mfimmr" , XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}}, |
5309 | {"mfmi_ctr" , XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}}, |
5310 | {"mfmi_ap" , XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}}, |
5311 | {"mfmi_epn" , XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}}, |
5312 | {"mfmi_twc" , XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}}, |
5313 | {"mfmi_rpn" , XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}}, |
5314 | {"mfmd_ctr" , XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}}, |
5315 | {"mfm_casid" , XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}}, |
5316 | {"mfmd_ap" , XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}}, |
5317 | {"mfmd_epn" , XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}}, |
5318 | {"mfmd_twb" , XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}}, |
5319 | {"mfmd_twc" , XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}}, |
5320 | {"mfmd_rpn" , XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}}, |
5321 | {"mfm_tw" , XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}}, |
5322 | {"mfmi_dbcam" , XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}}, |
5323 | {"mfmi_dbram0" , XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}}, |
5324 | {"mfmi_dbram1" , XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}}, |
5325 | {"mfmd_dbcam" , XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}}, |
5326 | {"mfmd_dbram0" , XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}}, |
5327 | {"mfmd_dbram1" , XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}}, |
5328 | {"mfivndx" , XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}}, |
5329 | {"mfdvndx" , XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}}, |
5330 | {"mfivlim" , XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}}, |
5331 | {"mfdvlim" , XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}}, |
5332 | {"mfclcsr" , XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}}, |
5333 | {"mfccr1" , XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}}, |
5334 | {"mfppr" , XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}}, |
5335 | {"mfppr32" , XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}}, |
5336 | {"mfrstcfg" , XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}}, |
5337 | {"mfdcdbtrl" , XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}}, |
5338 | {"mfdcdbtrh" , XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}}, |
5339 | {"mficdbtr" , XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}}, |
5340 | {"mfummcr0" , XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}}, |
5341 | {"mfupmc1" , XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}}, |
5342 | {"mfupmc2" , XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}}, |
5343 | {"mfusia" , XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}}, |
5344 | {"mfummcr1" , XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}}, |
5345 | {"mfupmc3" , XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}}, |
5346 | {"mfupmc4" , XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}}, |
5347 | {"mfzpr" , XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}}, |
5348 | {"mfpid" , XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}}, |
5349 | {"mfmmucr" , XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}}, |
5350 | {"mfccr0" , XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}}, |
5351 | {"mfiac3" , XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}}, |
5352 | {"mfiac4" , XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}}, |
5353 | {"mfdvc1" , XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}}, |
5354 | {"mfdvc2" , XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}}, |
5355 | {"mfmmcr0" , XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}}, |
5356 | {"mfpmc1" , XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}}, |
5357 | {"mfsgr" , XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}}, |
5358 | {"mfdcwr" , XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}}, |
5359 | {"mfpmc2" , XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}}, |
5360 | {"mfsia" , XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}}, |
5361 | {"mfsler" , XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}}, |
5362 | {"mfmmcr1" , XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}}, |
5363 | {"mfsu0r" , XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}}, |
5364 | {"mfdbcr1" , XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}}, |
5365 | {"mfpmc3" , XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}}, |
5366 | {"mfpmc4" , XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}}, |
5367 | {"mficdbdr" , XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}}, |
5368 | {"mfesr" , XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}}, |
5369 | {"mfdear" , XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}}, |
5370 | {"mfevpr" , XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}}, |
5371 | {"mfcdbcr" , XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}}, |
5372 | {"mftsr" , XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}}, |
5373 | {"mftcr" , XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}}, |
5374 | {"mfpit" , XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}}, |
5375 | {"mftbhi" , XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}}, |
5376 | {"mftblo" , XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}}, |
5377 | {"mfsrr2" , XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}}, |
5378 | {"mfsrr3" , XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}}, |
5379 | {"mfdbsr" , XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}}, |
5380 | {"mfdbcr0" , XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}}, |
5381 | {"mfdbdr" , XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}}, |
5382 | {"mfiac1" , XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}}, |
5383 | {"mfiac2" , XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}}, |
5384 | {"mfdac1" , XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}}, |
5385 | {"mfdac2" , XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}}, |
5386 | {"mfl2cr" , XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}}, |
5387 | {"mfdccr" , XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}}, |
5388 | {"mficcr" , XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}}, |
5389 | {"mfictc" , XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}}, |
5390 | {"mfpbl1" , XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}}, |
5391 | {"mfthrm1" , XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}}, |
5392 | {"mfpbu1" , XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}}, |
5393 | {"mfthrm2" , XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}}, |
5394 | {"mfpbl2" , XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}}, |
5395 | {"mfthrm3" , XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}}, |
5396 | {"mfpbu2" , XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}}, |
5397 | {"mfspr" , X(31,339), X_MASK, COM, 0, {RT, SPR}}, |
5398 | |
5399 | {"lwax" , X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}}, |
5400 | |
5401 | {"dst" , XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, |
5402 | |
5403 | {"lhax" , X(31,343), X_MASK, COM, 0, {RT, RA0, RB}}, |
5404 | |
5405 | {"lvxl" , X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, |
5406 | |
5407 | {"abs" , XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}}, |
5408 | {"abs." , XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}}, |
5409 | |
5410 | {"divs" , XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
5411 | {"divs." , XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, |
5412 | |
5413 | {"lxvwsx" , X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
5414 | |
5415 | {"tlbia" , X(31,370), 0xffffffff, PPC, E500|TITAN, {0}}, |
5416 | |
5417 | {"mftbu" , XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}}, |
5418 | {"mftb" , X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}}, |
5419 | {"mftbl" , XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}}, |
5420 | |
5421 | {"lwaux" , X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}}, |
5422 | |
5423 | {"dstst" , XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, |
5424 | |
5425 | {"lhaux" , X(31,375), X_MASK, COM, 0, {RT, RAL, RB}}, |
5426 | |
5427 | {"popcntw" , X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, |
5428 | |
5429 | {"mtdcrx" , X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}}, |
5430 | {"mtdcrx." , XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}}, |
5431 | |
5432 | {"stvexbx" , X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, |
5433 | |
5434 | {"dcblc" , X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, |
5435 | {"stdfcmx" , APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
5436 | |
5437 | {"divdeu" , XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
5438 | {"divdeu." , XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
5439 | {"divweu" , XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
5440 | {"divweu." , XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
5441 | |
5442 | {"stxvx" , X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
5443 | {"stxvl" , X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
5444 | |
5445 | {"dcblce" , X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, |
5446 | |
5447 | {"slbmte" , X(31,402), XRA_MASK, PPC64, 0, {RS, RB}}, |
5448 | |
5449 | {"mtvsrws" , X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}}, |
5450 | |
5451 | {"pbt." , XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}}, |
5452 | |
5453 | {"icswx" , XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, |
5454 | {"icswx." , XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, |
5455 | |
5456 | {"sthx" , X(31,407), X_MASK, COM, 0, {RS, RA0, RB}}, |
5457 | |
5458 | {"orc" , XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}}, |
5459 | {"orc." , XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}}, |
5460 | |
5461 | {"sthepx" , X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, |
5462 | |
5463 | {"mtdcrux" , X(31,419), X_MASK, PPC464, 0, {RA, RS}}, |
5464 | |
5465 | {"stvexhx" , X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, |
5466 | |
5467 | {"dcblq." , XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}}, |
5468 | |
5469 | {"divde" , XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
5470 | {"divde." , XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
5471 | {"divwe" , XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
5472 | {"divwe." , XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
5473 | |
5474 | {"stxvll" , X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
5475 | |
5476 | {"clrbhrb" , X(31,430), 0xffffffff, POWER8, 0, {0}}, |
5477 | |
5478 | {"slbie" , X(31,434), XRTRA_MASK, PPC64, 0, {RB}}, |
5479 | |
5480 | {"mtvsrdd" , X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
5481 | |
5482 | {"ecowx" , X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, |
5483 | |
5484 | {"sthux" , X(31,439), X_MASK, COM, 0, {RS, RAS, RB}}, |
5485 | |
5486 | {"mdors" , 0x7f9ce378, 0xffffffff, E500MC, 0, {0}}, |
5487 | |
5488 | {"miso" , 0x7f5ad378, 0xffffffff, E6500, 0, {0}}, |
5489 | |
5490 | /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for |
5491 | "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */ |
5492 | {"yield" , 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}}, |
5493 | {"mdoio" , 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}}, |
5494 | {"mdoom" , 0x7fdef378, 0xffffffff, POWER7, 0, {0}}, |
5495 | {"mr" , XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}}, |
5496 | {"or" , XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}}, |
5497 | {"mr." , XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}}, |
5498 | {"or." , XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}}, |
5499 | |
5500 | {"mtexisr" , XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}}, |
5501 | {"mtexier" , XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}}, |
5502 | {"mtbr0" , XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}}, |
5503 | {"mtbr1" , XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}}, |
5504 | {"mtbr2" , XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}}, |
5505 | {"mtbr3" , XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}}, |
5506 | {"mtbr4" , XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}}, |
5507 | {"mtbr5" , XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}}, |
5508 | {"mtbr6" , XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}}, |
5509 | {"mtbr7" , XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}}, |
5510 | {"mtbear" , XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}}, |
5511 | {"mtbesr" , XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}}, |
5512 | {"mtiocr" , XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}}, |
5513 | {"mtdmacr0" , XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}}, |
5514 | {"mtdmact0" , XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}}, |
5515 | {"mtdmada0" , XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}}, |
5516 | {"mtdmasa0" , XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}}, |
5517 | {"mtdmacc0" , XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}}, |
5518 | {"mtdmacr1" , XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}}, |
5519 | {"mtdmact1" , XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}}, |
5520 | {"mtdmada1" , XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}}, |
5521 | {"mtdmasa1" , XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}}, |
5522 | {"mtdmacc1" , XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}}, |
5523 | {"mtdmacr2" , XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}}, |
5524 | {"mtdmact2" , XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}}, |
5525 | {"mtdmada2" , XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}}, |
5526 | {"mtdmasa2" , XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}}, |
5527 | {"mtdmacc2" , XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}}, |
5528 | {"mtdmacr3" , XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}}, |
5529 | {"mtdmact3" , XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}}, |
5530 | {"mtdmada3" , XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}}, |
5531 | {"mtdmasa3" , XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}}, |
5532 | {"mtdmacc3" , XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}}, |
5533 | {"mtdmasr" , XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}}, |
5534 | {"mtdcr" , X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}}, |
5535 | {"mtdcr." , XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}}, |
5536 | |
5537 | {"stvexwx" , X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, |
5538 | |
5539 | {"dccci" , X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, |
5540 | {"dci" , X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, |
5541 | |
5542 | {"divdu" , XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
5543 | {"divdu." , XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
5544 | |
5545 | {"divwu" , XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
5546 | {"divwu." , XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, |
5547 | |
5548 | {"mtpmr" , X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}}, |
5549 | {"mttmr" , X(31,494), X_MASK, PPCTMR|E6500, 0, {TMR, RS}}, |
5550 | |
5551 | {"slbieg" , X(31,466), XRA_MASK, POWER9, 0, {RS, RB}}, |
5552 | |
5553 | {"mtmq" , XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}}, |
5554 | {"mtxer" , XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}}, |
5555 | {"mtlr" , XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}}, |
5556 | {"mtctr" , XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}}, |
5557 | {"mtdscr" , XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}}, |
5558 | {"mttid" , XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}}, |
5559 | {"mtdsisr" , XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}}, |
5560 | {"mtdar" , XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}}, |
5561 | {"mtrtcu" , XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}}, |
5562 | {"mtrtcl" , XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}}, |
5563 | {"mtdec" , XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}}, |
5564 | {"mtsdr0" , XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}}, |
5565 | {"mtsdr1" , XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}}, |
5566 | {"mtsrr0" , XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}}, |
5567 | {"mtsrr1" , XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}}, |
5568 | {"mtcfar" , XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}}, |
5569 | {"mtpid" , XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}}, |
5570 | {"mtdecar" , XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}}, |
5571 | {"mtcsrr0" , XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}}, |
5572 | {"mtcsrr1" , XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}}, |
5573 | {"mtdear" , XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}}, |
5574 | {"mtesr" , XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}}, |
5575 | {"mtivpr" , XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}}, |
5576 | {"mtcmpa" , XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}}, |
5577 | {"mtcmpb" , XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}}, |
5578 | {"mtcmpc" , XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}}, |
5579 | {"mtcmpd" , XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}}, |
5580 | {"mticr" , XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}}, |
5581 | {"mtder" , XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}}, |
5582 | {"mtcounta" , XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}}, |
5583 | {"mtcountb" , XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}}, |
5584 | {"mtctrl" , XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}}, |
5585 | {"mtcmpe" , XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}}, |
5586 | {"mtcmpf" , XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}}, |
5587 | {"mtcmpg" , XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}}, |
5588 | {"mtcmph" , XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}}, |
5589 | {"mtlctrl1" , XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}}, |
5590 | {"mtlctrl2" , XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}}, |
5591 | {"mtictrl" , XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}}, |
5592 | {"mtbar" , XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}}, |
5593 | {"mtvrsave" , XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}}, |
5594 | {"mtusprg0" , XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}}, |
5595 | {"mtsprg" , XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}}, |
5596 | {"mtsprg0" , XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}}, |
5597 | {"mtsprg1" , XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}}, |
5598 | {"mtsprg2" , XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}}, |
5599 | {"mtsprg3" , XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}}, |
5600 | {"mtsprg4" , XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, |
5601 | {"mtsprg5" , XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, |
5602 | {"mtsprg6" , XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, |
5603 | {"mtsprg7" , XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}}, |
5604 | {"mtasr" , XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}}, |
5605 | {"mtear" , XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}}, |
5606 | {"mttbl" , XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}}, |
5607 | {"mttbu" , XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}}, |
5608 | {"mtdbsr" , XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}}, |
5609 | {"mtdbcr0" , XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}}, |
5610 | {"mtdbcr1" , XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}}, |
5611 | {"mtdbcr2" , XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}}, |
5612 | {"mtiac1" , XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}}, |
5613 | {"mtiac2" , XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}}, |
5614 | {"mtiac3" , XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}}, |
5615 | {"mtiac4" , XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}}, |
5616 | {"mtdac1" , XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}}, |
5617 | {"mtdac2" , XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}}, |
5618 | {"mtdvc1" , XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}}, |
5619 | {"mtdvc2" , XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}}, |
5620 | {"mttsr" , XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}}, |
5621 | {"mttcr" , XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}}, |
5622 | {"mtivor0" , XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}}, |
5623 | {"mtivor1" , XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}}, |
5624 | {"mtivor2" , XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}}, |
5625 | {"mtivor3" , XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}}, |
5626 | {"mtivor4" , XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}}, |
5627 | {"mtivor5" , XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}}, |
5628 | {"mtivor6" , XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}}, |
5629 | {"mtivor7" , XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}}, |
5630 | {"mtivor8" , XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}}, |
5631 | {"mtivor9" , XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}}, |
5632 | {"mtivor10" , XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}}, |
5633 | {"mtivor11" , XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}}, |
5634 | {"mtivor12" , XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}}, |
5635 | {"mtivor13" , XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}}, |
5636 | {"mtivor14" , XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}}, |
5637 | {"mtivor15" , XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}}, |
5638 | {"mtspefscr" , XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}}, |
5639 | {"mtbbear" , XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}}, |
5640 | {"mtbbtar" , XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}}, |
5641 | {"mtivor32" , XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}}, |
5642 | {"mtibatu" , XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, |
5643 | {"mtivor33" , XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}}, |
5644 | {"mtibatl" , XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, |
5645 | {"mtivor34" , XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}}, |
5646 | {"mtivor35" , XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}}, |
5647 | {"mtdbatu" , XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, |
5648 | {"mtdbatl" , XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, |
5649 | {"mtmcsrr0" , XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}}, |
5650 | {"mtmcsrr1" , XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}}, |
5651 | {"mtmcsr" , XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}}, |
5652 | {"mtivndx" , XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}}, |
5653 | {"mtdvndx" , XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}}, |
5654 | {"mtivlim" , XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}}, |
5655 | {"mtdvlim" , XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}}, |
5656 | {"mtclcsr" , XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}}, |
5657 | {"mtccr1" , XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}}, |
5658 | {"mtppr" , XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}}, |
5659 | {"mtppr32" , XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}}, |
5660 | {"mtummcr0" , XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}}, |
5661 | {"mtupmc1" , XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}}, |
5662 | {"mtupmc2" , XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}}, |
5663 | {"mtusia" , XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}}, |
5664 | {"mtummcr1" , XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}}, |
5665 | {"mtupmc3" , XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}}, |
5666 | {"mtupmc4" , XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}}, |
5667 | {"mtzpr" , XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}}, |
5668 | {"mtpid" , XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}}, |
5669 | {"mtrmmucr" , XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}}, |
5670 | {"mtccr0" , XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}}, |
5671 | {"mtiac3" , XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}}, |
5672 | {"mtiac4" , XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}}, |
5673 | {"mtdvc1" , XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}}, |
5674 | {"mtdvc2" , XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}}, |
5675 | {"mtmmcr0" , XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}}, |
5676 | {"mtpmc1" , XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}}, |
5677 | {"mtsgr" , XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}}, |
5678 | {"mtdcwr" , XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}}, |
5679 | {"mtpmc2" , XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}}, |
5680 | {"mtsia" , XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}}, |
5681 | {"mtsler" , XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}}, |
5682 | {"mtmmcr1" , XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}}, |
5683 | {"mtsu0r" , XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}}, |
5684 | {"mtdbcr1" , XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}}, |
5685 | {"mtpmc3" , XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}}, |
5686 | {"mtpmc4" , XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}}, |
5687 | {"mticdbdr" , XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}}, |
5688 | {"mtesr" , XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}}, |
5689 | {"mtdear" , XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}}, |
5690 | {"mtevpr" , XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}}, |
5691 | {"mtcdbcr" , XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}}, |
5692 | {"mttsr" , XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}}, |
5693 | {"mttcr" , XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}}, |
5694 | {"mtpit" , XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}}, |
5695 | {"mttbhi" , XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}}, |
5696 | {"mttblo" , XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}}, |
5697 | {"mtsrr2" , XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}}, |
5698 | {"mtsrr3" , XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}}, |
5699 | {"mtdbsr" , XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}}, |
5700 | {"mtdbdr" , XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}}, |
5701 | {"mtdbcr0" , XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}}, |
5702 | {"mtiac1" , XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}}, |
5703 | {"mtiac2" , XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}}, |
5704 | {"mtdac1" , XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}}, |
5705 | {"mtdac2" , XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}}, |
5706 | {"mtl2cr" , XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}}, |
5707 | {"mtdccr" , XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}}, |
5708 | {"mticcr" , XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}}, |
5709 | {"mtictc" , XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}}, |
5710 | {"mtpbl1" , XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}}, |
5711 | {"mtthrm1" , XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}}, |
5712 | {"mtpbu1" , XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}}, |
5713 | {"mtthrm2" , XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}}, |
5714 | {"mtpbl2" , XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}}, |
5715 | {"mtthrm3" , XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}}, |
5716 | {"mtpbu2" , XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}}, |
5717 | {"mtspr" , X(31,467), X_MASK, COM, 0, {SPR, RS}}, |
5718 | |
5719 | {"dcbi" , X(31,470), XRT_MASK, PPC, 0, {RA0, RB}}, |
5720 | |
5721 | {"nand" , XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}}, |
5722 | {"nand." , XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}}, |
5723 | |
5724 | {"dsn" , X(31,483), XRT_MASK, E500MC, 0, {RA, RB}}, |
5725 | |
5726 | {"dcread" , X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}}, |
5727 | |
5728 | {"icbtls" , X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, |
5729 | |
5730 | {"stvxl" , X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, |
5731 | |
5732 | {"nabs" , XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}}, |
5733 | {"nabs." , XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}}, |
5734 | |
5735 | {"divd" , XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
5736 | {"divd." , XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
5737 | |
5738 | {"divw" , XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
5739 | {"divw." , XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, |
5740 | |
5741 | {"icbtlse" , X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, |
5742 | |
5743 | {"slbia" , X(31,498), 0xff1fffff, POWER6, 0, {IH}}, |
5744 | {"slbia" , X(31,498), 0xffffffff, PPC64, POWER6, {0}}, |
5745 | |
5746 | {"cli" , X(31,502), XRB_MASK, POWER, 0, {RT, RA}}, |
5747 | |
5748 | {"popcntd" , X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, |
5749 | |
5750 | {"cmpb" , X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}}, |
5751 | |
5752 | {"mcrxr" , X(31,512), XBFRARB_MASK, COM, POWER7, {BF}}, |
5753 | |
5754 | {"lbdcbx" , X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}}, |
5755 | {"lbdx" , X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}}, |
5756 | |
5757 | {"bblels" , X(31,518), X_MASK, PPCBRLK, 0, {0}}, |
5758 | |
5759 | {"lvlx" , X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}}, |
5760 | {"lbfcmux" , APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
5761 | |
5762 | {"subfco" , XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5763 | {"sfo" , XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
5764 | {"subco" , XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, |
5765 | {"subfco." , XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5766 | {"sfo." , XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
5767 | {"subco." , XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, |
5768 | |
5769 | {"addco" , XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5770 | {"ao" , XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
5771 | {"addco." , XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5772 | {"ao." , XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
5773 | |
5774 | {"lxsspx" , X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, |
5775 | |
5776 | {"clcs" , X(31,531), XRB_MASK, M601, 0, {RT, RA}}, |
5777 | |
5778 | {"ldbrx" , X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}}, |
5779 | |
5780 | {"lswx" , X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}}, |
5781 | {"lsx" , X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}}, |
5782 | |
5783 | {"lwbrx" , X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, |
5784 | {"lbrx" , X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}}, |
5785 | |
5786 | {"lfsx" , X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, |
5787 | |
5788 | {"srw" , XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, |
5789 | {"sr" , XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, |
5790 | {"srw." , XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, |
5791 | {"sr." , XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, |
5792 | |
5793 | {"rrib" , XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}}, |
5794 | {"rrib." , XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}}, |
5795 | |
5796 | {"cnttzw" , XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}}, |
5797 | {"cnttzw." , XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}}, |
5798 | |
5799 | {"srd" , XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}}, |
5800 | {"srd." , XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}}, |
5801 | |
5802 | {"maskir" , XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}}, |
5803 | {"maskir." , XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}}, |
5804 | |
5805 | {"lhdcbx" , X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}}, |
5806 | {"lhdx" , X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}}, |
5807 | |
5808 | {"lvtrx" , X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, |
5809 | |
5810 | {"bbelr" , X(31,550), X_MASK, PPCBRLK, 0, {0}}, |
5811 | |
5812 | {"lvrx" , X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}}, |
5813 | {"lhfcmux" , APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
5814 | |
5815 | {"subfo" , XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
5816 | {"subo" , XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}}, |
5817 | {"subfo." , XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, |
5818 | {"subo." , XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}}, |
5819 | |
5820 | {"tlbsync" , X(31,566), 0xffffffff, PPC, 0, {0}}, |
5821 | |
5822 | {"lfsux" , X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, |
5823 | |
5824 | {"cnttzd" , XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}}, |
5825 | {"cnttzd." , XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}}, |
5826 | |
5827 | {"mcrxrx" , X(31,576), XBFRARB_MASK, POWER9, 0, {BF}}, |
5828 | |
5829 | {"lwdcbx" , X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}}, |
5830 | {"lwdx" , X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}}, |
5831 | |
5832 | {"lvtlx" , X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, |
5833 | |
5834 | {"lwat" , X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}}, |
5835 | |
5836 | {"lwfcmux" , APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
5837 | |
5838 | {"lxsdx" , X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, |
5839 | |
5840 | {"mfsr" , X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}}, |
5841 | |
5842 | {"lswi" , X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}}, |
5843 | {"lsi" , X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}}, |
5844 | |
5845 | {"hwsync" , XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}}, |
5846 | {"lwsync" , XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}}, |
5847 | {"ptesync" , XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}}, |
5848 | {"sync" , X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}}, |
5849 | {"sync" , X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}}, |
5850 | {"msync" , X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}}, |
5851 | {"sync" , X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}}, |
5852 | {"lwsync" , X(31,598), 0xffffffff, E500, 0, {0}}, |
5853 | {"dcs" , X(31,598), 0xffffffff, PWRCOM, 0, {0}}, |
5854 | |
5855 | {"lfdx" , X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, |
5856 | |
5857 | {"mffgpr" , XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}}, |
5858 | {"lfdepx" , X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}}, |
5859 | |
5860 | {"lddx" , X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}}, |
5861 | |
5862 | {"lvswx" , X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, |
5863 | |
5864 | {"ldat" , X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}}, |
5865 | |
5866 | {"lqfcmux" , APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
5867 | |
5868 | {"nego" , XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}}, |
5869 | {"nego." , XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}}, |
5870 | |
5871 | {"mulo" , XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
5872 | {"mulo." , XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, |
5873 | |
5874 | {"mfsri" , X(31,627), X_MASK, M601, 0, {RT, RA, RB}}, |
5875 | |
5876 | {"dclst" , X(31,630), XRB_MASK, M601, 0, {RS, RA}}, |
5877 | |
5878 | {"lfdux" , X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, |
5879 | |
5880 | {"stbdcbx" , X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}}, |
5881 | {"stbdx" , X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}}, |
5882 | |
5883 | {"stvlx" , X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}}, |
5884 | {"stbfcmux" , APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
5885 | |
5886 | {"stxsspx" , X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, |
5887 | |
5888 | {"tbegin." , XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}}, |
5889 | |
5890 | {"subfeo" , XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5891 | {"sfeo" , XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
5892 | {"subfeo." , XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5893 | {"sfeo." , XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
5894 | |
5895 | {"addeo" , XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5896 | {"aeo" , XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
5897 | {"addeo." , XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5898 | {"aeo." , XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
5899 | |
5900 | {"mfsrin" , X(31,659), XRA_MASK, PPC, NON32, {RT, RB}}, |
5901 | |
5902 | {"stdbrx" , X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}}, |
5903 | |
5904 | {"stswx" , X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}}, |
5905 | {"stsx" , X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, |
5906 | |
5907 | {"stwbrx" , X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, |
5908 | {"stbrx" , X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, |
5909 | |
5910 | {"stfsx" , X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, |
5911 | |
5912 | {"srq" , XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}}, |
5913 | {"srq." , XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}}, |
5914 | |
5915 | {"sre" , XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}}, |
5916 | {"sre." , XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}}, |
5917 | |
5918 | {"sthdcbx" , X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}}, |
5919 | {"sthdx" , X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}}, |
5920 | |
5921 | {"stvfrx" , X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, |
5922 | |
5923 | {"stvrx" , X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}}, |
5924 | {"sthfcmux" , APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
5925 | |
5926 | {"tendall." , XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}}, |
5927 | {"tend." , XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}}, |
5928 | |
5929 | {"stbcx." , XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, |
5930 | |
5931 | {"stfsux" , X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, |
5932 | |
5933 | {"sriq" , XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}}, |
5934 | {"sriq." , XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}}, |
5935 | |
5936 | {"stwdcbx" , X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}}, |
5937 | {"stwdx" , X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}}, |
5938 | |
5939 | {"stvflx" , X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, |
5940 | |
5941 | {"stwat" , X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}}, |
5942 | |
5943 | {"stwfcmux" , APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
5944 | |
5945 | {"stxsdx" , X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, |
5946 | |
5947 | {"tcheck" , X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}}, |
5948 | |
5949 | {"subfzeo" , XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
5950 | {"sfzeo" , XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, |
5951 | {"subfzeo." , XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
5952 | {"sfzeo." , XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, |
5953 | |
5954 | {"addzeo" , XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
5955 | {"azeo" , XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, |
5956 | {"addzeo." , XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
5957 | {"azeo." , XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, |
5958 | |
5959 | {"stswi" , X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}}, |
5960 | {"stsi" , X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}}, |
5961 | |
5962 | {"sthcx." , XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, |
5963 | |
5964 | {"stfdx" , X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, |
5965 | |
5966 | {"srlq" , XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}}, |
5967 | {"srlq." , XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}}, |
5968 | |
5969 | {"sreq" , XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}}, |
5970 | {"sreq." , XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}}, |
5971 | |
5972 | {"mftgpr" , XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}}, |
5973 | {"stfdepx" , X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}}, |
5974 | |
5975 | {"stddx" , X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}}, |
5976 | |
5977 | {"stvswx" , X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, |
5978 | |
5979 | {"stdat" , X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}}, |
5980 | |
5981 | {"stqfcmux" , APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
5982 | |
5983 | {"subfmeo" , XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
5984 | {"sfmeo" , XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, |
5985 | {"subfmeo." , XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
5986 | {"sfmeo." , XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, |
5987 | |
5988 | {"mulldo" , XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
5989 | {"mulldo." , XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
5990 | |
5991 | {"addmeo" , XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
5992 | {"ameo" , XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, |
5993 | {"addmeo." , XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, |
5994 | {"ameo." , XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, |
5995 | |
5996 | {"mullwo" , XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5997 | {"mulso" , XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
5998 | {"mullwo." , XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
5999 | {"mulso." , XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
6000 | |
6001 | {"tsuspend." , XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}}, |
6002 | {"tresume." , XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}}, |
6003 | {"tsr." , XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}}, |
6004 | |
6005 | {"darn" , X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}}, |
6006 | |
6007 | {"dcba" , X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, |
6008 | {"dcbal" , XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}}, |
6009 | |
6010 | {"stfdux" , X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, |
6011 | |
6012 | {"srliq" , XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}}, |
6013 | {"srliq." , XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}}, |
6014 | |
6015 | {"lvsm" , X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, |
6016 | |
6017 | {"copy" , XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}}, |
6018 | |
6019 | {"stvepxl" , X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, |
6020 | {"lvlxl" , X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}}, |
6021 | {"ldfcmux" , APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
6022 | |
6023 | {"dozo" , XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
6024 | {"dozo." , XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, |
6025 | |
6026 | {"addo" , XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
6027 | {"caxo" , XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
6028 | {"addo." , XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, |
6029 | {"caxo." , XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, |
6030 | |
6031 | {"modsd" , X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}}, |
6032 | {"modsw" , X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}}, |
6033 | |
6034 | {"lxvw4x" , X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, |
6035 | {"lxsibzx" , X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
6036 | |
6037 | {"tabortwc." , XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, |
6038 | |
6039 | {"tlbivax" , X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, |
6040 | |
6041 | {"lwzcix" , X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}}, |
6042 | |
6043 | {"lhbrx" , X(31,790), X_MASK, COM, 0, {RT, RA0, RB}}, |
6044 | |
6045 | {"lfdpx" , X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}}, |
6046 | {"lfqx" , X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}}, |
6047 | |
6048 | {"sraw" , XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, |
6049 | {"sra" , XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, |
6050 | {"sraw." , XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, |
6051 | {"sra." , XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, |
6052 | |
6053 | {"srad" , XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}}, |
6054 | {"srad." , XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}}, |
6055 | |
6056 | {"lfddx" , X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}}, |
6057 | |
6058 | {"lvtrxl" , X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, |
6059 | {"stvepx" , X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, |
6060 | {"lvrxl" , X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}}, |
6061 | |
6062 | {"lxvh8x" , X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
6063 | {"lxsihzx" , X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
6064 | |
6065 | {"tabortdc." , XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, |
6066 | |
6067 | {"rac" , X(31,818), X_MASK, M601, 0, {RT, RA, RB}}, |
6068 | |
6069 | {"erativax" , X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}}, |
6070 | |
6071 | {"lhzcix" , X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}}, |
6072 | |
6073 | {"dss" , XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}}, |
6074 | |
6075 | {"lfqux" , X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}}, |
6076 | |
6077 | {"srawi" , XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}}, |
6078 | {"srai" , XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}}, |
6079 | {"srawi." , XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}}, |
6080 | {"srai." , XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}}, |
6081 | |
6082 | {"sradi" , XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}}, |
6083 | {"sradi." , XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}}, |
6084 | |
6085 | {"lvtlxl" , X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, |
6086 | |
6087 | {"cpabort" , X(31,838), XRTRARB_MASK,POWER9, 0, {0}}, |
6088 | |
6089 | {"divo" , XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
6090 | {"divo." , XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, |
6091 | |
6092 | {"lxvd2x" , X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, |
6093 | {"lxvx" , X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}}, |
6094 | |
6095 | {"tabortwci." , XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, |
6096 | |
6097 | {"tlbsrx." , XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}}, |
6098 | |
6099 | {"slbiag" , X(31,850), XRARB_MASK, POWER9, 0, {RS}}, |
6100 | {"slbmfev" , X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, |
6101 | {"slbmfev" , X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}}, |
6102 | |
6103 | {"lbzcix" , X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}}, |
6104 | |
6105 | {"eieio" , X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}}, |
6106 | {"mbar" , X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}}, |
6107 | {"eieio" , XMBAR(31,854,1),0xffffffff, E500, 0, {0}}, |
6108 | {"eieio" , X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}}, |
6109 | |
6110 | {"lfiwax" , X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}}, |
6111 | |
6112 | {"lvswxl" , X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, |
6113 | |
6114 | {"abso" , XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}}, |
6115 | {"abso." , XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}}, |
6116 | |
6117 | {"divso" , XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, |
6118 | {"divso." , XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, |
6119 | |
6120 | {"lxvb16x" , X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, |
6121 | |
6122 | {"tabortdci." , XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, |
6123 | |
6124 | {"rmieg" , X(31,882), XRTRA_MASK, POWER9, 0, {RB}}, |
6125 | |
6126 | {"ldcix" , X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}}, |
6127 | |
6128 | {"msgsync" , X(31,886), 0xffffffff, POWER9, 0, {0}}, |
6129 | |
6130 | {"lfiwzx" , X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}}, |
6131 | |
6132 | {"extswsli" , XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}}, |
6133 | {"extswsli." , XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}}, |
6134 | |
6135 | {"paste." , XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}}, |
6136 | |
6137 | {"stvlxl" , X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}}, |
6138 | {"stdfcmux" , APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, |
6139 | |
6140 | {"divdeuo" , XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
6141 | {"divdeuo." , XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
6142 | {"divweuo" , XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
6143 | {"divweuo." , XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
6144 | |
6145 | {"stxvw4x" , X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, |
6146 | {"stxsibx" , X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
6147 | |
6148 | {"tabort." , XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}}, |
6149 | |
6150 | {"tlbsx" , XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, |
6151 | {"tlbsx." , XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, |
6152 | |
6153 | {"slbmfee" , X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, |
6154 | {"slbmfee" , X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}}, |
6155 | |
6156 | {"stwcix" , X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}}, |
6157 | |
6158 | {"sthbrx" , X(31,918), X_MASK, COM, 0, {RS, RA0, RB}}, |
6159 | |
6160 | {"stfdpx" , X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}}, |
6161 | {"stfqx" , X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}}, |
6162 | |
6163 | {"sraq" , XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6164 | {"sraq." , XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}}, |
6165 | |
6166 | {"srea" , XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}}, |
6167 | {"srea." , XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}}, |
6168 | |
6169 | {"extsh" , XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, |
6170 | {"exts" , XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, |
6171 | {"extsh." , XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, |
6172 | {"exts." , XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, |
6173 | |
6174 | {"stfddx" , X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}}, |
6175 | |
6176 | {"stvfrxl" , X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, |
6177 | |
6178 | {"wclrone" , XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}}, |
6179 | {"wclrall" , X(31,934), XRARB_MASK, PPCA2, 0, {L2}}, |
6180 | {"wclr" , X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}}, |
6181 | |
6182 | {"stvrxl" , X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}}, |
6183 | |
6184 | {"divdeo" , XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
6185 | {"divdeo." , XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
6186 | {"divweo" , XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
6187 | {"divweo." , XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, |
6188 | |
6189 | {"stxvh8x" , X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
6190 | {"stxsihx" , X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
6191 | |
6192 | {"treclaim." , XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}}, |
6193 | |
6194 | {"tlbrehi" , XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, |
6195 | {"tlbrelo" , XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, |
6196 | {"tlbre" , X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}}, |
6197 | |
6198 | {"sthcix" , X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}}, |
6199 | |
6200 | {"icswepx" , XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}}, |
6201 | {"icswepx." , XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}}, |
6202 | |
6203 | {"stfqux" , X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}}, |
6204 | |
6205 | {"sraiq" , XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}}, |
6206 | {"sraiq." , XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}}, |
6207 | |
6208 | {"extsb" , XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}}, |
6209 | {"extsb." , XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}}, |
6210 | |
6211 | {"stvflxl" , X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, |
6212 | |
6213 | {"iccci" , X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, |
6214 | {"ici" , X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, |
6215 | |
6216 | {"divduo" , XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
6217 | {"divduo." , XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
6218 | |
6219 | {"divwuo" , XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
6220 | {"divwuo." , XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, |
6221 | |
6222 | {"stxvd2x" , X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, |
6223 | {"stxvx" , X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}}, |
6224 | |
6225 | {"tlbld" , X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}}, |
6226 | {"tlbwehi" , XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}}, |
6227 | {"tlbwelo" , XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}}, |
6228 | {"tlbwe" , X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}}, |
6229 | |
6230 | {"slbfee." , XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}}, |
6231 | |
6232 | {"stbcix" , X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}}, |
6233 | |
6234 | {"icbi" , X(31,982), XRT_MASK, PPC, 0, {RA0, RB}}, |
6235 | |
6236 | {"stfiwx" , X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}}, |
6237 | |
6238 | {"extsw" , XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}}, |
6239 | {"extsw." , XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}}, |
6240 | |
6241 | {"icbiep" , XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
6242 | |
6243 | {"stvswxl" , X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, |
6244 | |
6245 | {"icread" , X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}}, |
6246 | |
6247 | {"nabso" , XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}}, |
6248 | {"nabso." , XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}}, |
6249 | |
6250 | {"divdo" , XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
6251 | {"divdo." , XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, |
6252 | |
6253 | {"divwo" , XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, |
6254 | {"divwo." , XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, |
6255 | |
6256 | {"stxvb16x" , X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, |
6257 | |
6258 | {"trechkpt." , XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}}, |
6259 | |
6260 | {"tlbli" , X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, |
6261 | |
6262 | {"stdcix" , X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}}, |
6263 | |
6264 | {"dcbz" , X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, |
6265 | {"dclz" , X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, |
6266 | |
6267 | {"dcbzep" , XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, |
6268 | |
6269 | {"dcbzl" , XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}}, |
6270 | |
6271 | {"cctpl" , 0x7c210b78, 0xffffffff, CELL, 0, {0}}, |
6272 | {"cctpm" , 0x7c421378, 0xffffffff, CELL, 0, {0}}, |
6273 | {"cctph" , 0x7c631b78, 0xffffffff, CELL, 0, {0}}, |
6274 | |
6275 | {"dstt" , XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, |
6276 | {"dststt" , XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, |
6277 | {"dssall" , XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}}, |
6278 | |
6279 | {"db8cyc" , 0x7f9ce378, 0xffffffff, CELL, 0, {0}}, |
6280 | {"db10cyc" , 0x7fbdeb78, 0xffffffff, CELL, 0, {0}}, |
6281 | {"db12cyc" , 0x7fdef378, 0xffffffff, CELL, 0, {0}}, |
6282 | {"db16cyc" , 0x7ffffb78, 0xffffffff, CELL, 0, {0}}, |
6283 | |
6284 | {"lwz" , OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, |
6285 | {"l" , OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, |
6286 | |
6287 | {"lwzu" , OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}}, |
6288 | {"lu" , OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, |
6289 | |
6290 | {"lbz" , OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, |
6291 | |
6292 | {"lbzu" , OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, |
6293 | |
6294 | {"stw" , OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, |
6295 | {"st" , OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, |
6296 | |
6297 | {"stwu" , OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}}, |
6298 | {"stu" , OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, |
6299 | |
6300 | {"stb" , OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, |
6301 | |
6302 | {"stbu" , OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, |
6303 | |
6304 | {"lhz" , OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, |
6305 | |
6306 | {"lhzu" , OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, |
6307 | |
6308 | {"lha" , OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, |
6309 | |
6310 | {"lhau" , OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, |
6311 | |
6312 | {"sth" , OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, |
6313 | |
6314 | {"sthu" , OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, |
6315 | |
6316 | {"lmw" , OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}}, |
6317 | {"lm" , OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, |
6318 | |
6319 | {"stmw" , OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, |
6320 | {"stm" , OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, |
6321 | |
6322 | {"lfs" , OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, |
6323 | |
6324 | {"lfsu" , OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}}, |
6325 | |
6326 | {"lfd" , OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, |
6327 | |
6328 | {"lfdu" , OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}}, |
6329 | |
6330 | {"stfs" , OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, |
6331 | |
6332 | {"stfsu" , OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}}, |
6333 | |
6334 | {"stfd" , OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, |
6335 | |
6336 | {"stfdu" , OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}}, |
6337 | |
6338 | {"lq" , OP(56), OP_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}}, |
6339 | {"psq_l" , OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, |
6340 | {"lfq" , OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, |
6341 | |
6342 | {"lxsd" , DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, |
6343 | {"lxssp" , DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, |
6344 | {"lfdp" , OP(57), OP_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}}, |
6345 | {"psq_lu" , OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, |
6346 | {"lfqu" , OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, |
6347 | |
6348 | {"ld" , DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, |
6349 | {"ldu" , DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}}, |
6350 | {"lwa" , DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, |
6351 | |
6352 | {"dadd" , XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
6353 | {"dadd." , XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
6354 | |
6355 | {"dqua" , ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}}, |
6356 | {"dqua." , ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}}, |
6357 | |
6358 | {"fdivs" , A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
6359 | {"fdivs." , A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
6360 | |
6361 | {"fsubs" , A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
6362 | {"fsubs." , A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
6363 | |
6364 | {"fadds" , A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
6365 | {"fadds." , A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
6366 | |
6367 | {"fsqrts" , A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}}, |
6368 | {"fsqrts." , A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}}, |
6369 | |
6370 | {"fres" , A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
6371 | {"fres" , A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, |
6372 | {"fres." , A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
6373 | {"fres." , A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, |
6374 | |
6375 | {"fmuls" , A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, |
6376 | {"fmuls." , A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, |
6377 | |
6378 | {"frsqrtes" , A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
6379 | {"frsqrtes" , A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, |
6380 | {"frsqrtes." , A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
6381 | {"frsqrtes." , A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, |
6382 | |
6383 | {"fmsubs" , A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6384 | {"fmsubs." , A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6385 | |
6386 | {"fmadds" , A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6387 | {"fmadds." , A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6388 | |
6389 | {"fnmsubs" , A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6390 | {"fnmsubs." , A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6391 | |
6392 | {"fnmadds" , A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6393 | {"fnmadds." , A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6394 | |
6395 | {"dmul" , XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
6396 | {"dmul." , XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
6397 | |
6398 | {"drrnd" , ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}}, |
6399 | {"drrnd." , ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}}, |
6400 | |
6401 | {"dscli" , ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, |
6402 | {"dscli." , ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, |
6403 | |
6404 | {"dquai" , ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}}, |
6405 | {"dquai." , ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}}, |
6406 | |
6407 | {"dscri" , ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, |
6408 | {"dscri." , ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, |
6409 | |
6410 | {"drintx" , ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, |
6411 | {"drintx." , ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, |
6412 | |
6413 | {"dcmpo" , X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, |
6414 | |
6415 | {"dtstex" , X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, |
6416 | {"dtstdc" , Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}}, |
6417 | {"dtstdg" , Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}}, |
6418 | |
6419 | {"drintn" , ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, |
6420 | {"drintn." , ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, |
6421 | |
6422 | {"dctdp" , XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, |
6423 | {"dctdp." , XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, |
6424 | |
6425 | {"dctfix" , XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, |
6426 | {"dctfix." , XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, |
6427 | |
6428 | {"ddedpd" , XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}}, |
6429 | {"ddedpd." , XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}}, |
6430 | |
6431 | {"dxex" , XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, |
6432 | {"dxex." , XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, |
6433 | |
6434 | {"dsub" , XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
6435 | {"dsub." , XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
6436 | |
6437 | {"ddiv" , XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
6438 | {"ddiv." , XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
6439 | |
6440 | {"dcmpu" , X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, |
6441 | |
6442 | {"dtstsf" , X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, |
6443 | {"dtstsfi" , X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}}, |
6444 | |
6445 | {"drsp" , XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, |
6446 | {"drsp." , XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, |
6447 | |
6448 | {"dcffix" , XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
6449 | {"dcffix." , XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
6450 | |
6451 | {"denbcd" , XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}}, |
6452 | {"denbcd." , XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}}, |
6453 | |
6454 | {"fcfids" , XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
6455 | {"fcfids." , XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
6456 | |
6457 | {"diex" , XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
6458 | {"diex." , XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, |
6459 | |
6460 | {"fcfidus" , XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
6461 | {"fcfidus." , XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
6462 | |
6463 | {"xsaddsp" , XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, |
6464 | {"xsmaddasp" , XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, |
6465 | {"xxsldwi" , XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}}, |
6466 | {"xscmpeqdp" , XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, |
6467 | {"xsrsqrtesp" , XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, |
6468 | {"xssqrtsp" , XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, |
6469 | {"xxsel" , XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}}, |
6470 | {"xssubsp" , XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, |
6471 | {"xsmaddmsp" , XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, |
6472 | {"xxspltd" , XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S, DMEX}}, |
6473 | {"xxmrghd" , XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6474 | {"xxswapd" , XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}}, |
6475 | {"xxmrgld" , XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6476 | {"xxpermdi" , XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}}, |
6477 | {"xscmpgtdp" , XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, |
6478 | {"xsresp" , XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, |
6479 | {"xsmulsp" , XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, |
6480 | {"xsmsubasp" , XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, |
6481 | {"xxmrghw" , XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6482 | {"xscmpgedp" , XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, |
6483 | {"xsdivsp" , XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, |
6484 | {"xsmsubmsp" , XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, |
6485 | {"xxperm" , XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, |
6486 | {"xsadddp" , XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6487 | {"xsmaddadp" , XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6488 | {"xscmpudp" , XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, |
6489 | {"xscvdpuxws" , XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6490 | {"xsrdpi" , XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6491 | {"xsrsqrtedp" , XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6492 | {"xssqrtdp" , XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6493 | {"xssubdp" , XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6494 | {"xsmaddmdp" , XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6495 | {"xscmpodp" , XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, |
6496 | {"xscvdpsxws" , XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6497 | {"xsrdpiz" , XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6498 | {"xsredp" , XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6499 | {"xsmuldp" , XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6500 | {"xsmsubadp" , XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6501 | {"xxmrglw" , XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6502 | {"xsrdpip" , XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6503 | {"xstsqrtdp" , XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, |
6504 | {"xsrdpic" , XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6505 | {"xsdivdp" , XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6506 | {"xsmsubmdp" , XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6507 | {"xxpermr" , XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, |
6508 | {"xscmpexpdp" , XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}}, |
6509 | {"xsrdpim" , XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6510 | {"xstdivdp" , XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, |
6511 | {"xvaddsp" , XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6512 | {"xvmaddasp" , XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6513 | {"xvcmpeqsp" , XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6514 | {"xvcmpeqsp." , XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6515 | {"xvcvspuxws" , XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6516 | {"xvrspi" , XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6517 | {"xvrsqrtesp" , XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6518 | {"xvsqrtsp" , XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6519 | {"xvsubsp" , XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6520 | {"xvmaddmsp" , XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6521 | {"xvcmpgtsp" , XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6522 | {"xvcmpgtsp." , XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6523 | {"xvcvspsxws" , XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6524 | {"xvrspiz" , XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6525 | {"xvresp" , XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6526 | {"xvmulsp" , XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6527 | {"xvmsubasp" , XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6528 | {"xxspltw" , XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}}, |
6529 | {"xxextractuw" , XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}}, |
6530 | {"xvcmpgesp" , XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6531 | {"xvcmpgesp." , XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6532 | {"xvcvuxwsp" , XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6533 | {"xvrspip" , XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6534 | {"xvtsqrtsp" , XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, |
6535 | {"xvrspic" , XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6536 | {"xvdivsp" , XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6537 | {"xvmsubmsp" , XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6538 | {"xxspltib" , X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}}, |
6539 | {"xxinsertw" , XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}}, |
6540 | {"xvcvsxwsp" , XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6541 | {"xvrspim" , XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6542 | {"xvtdivsp" , XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, |
6543 | {"xvadddp" , XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6544 | {"xvmaddadp" , XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6545 | {"xvcmpeqdp" , XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6546 | {"xvcmpeqdp." , XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6547 | {"xvcvdpuxws" , XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6548 | {"xvrdpi" , XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6549 | {"xvrsqrtedp" , XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6550 | {"xvsqrtdp" , XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6551 | {"xvsubdp" , XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6552 | {"xvmaddmdp" , XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6553 | {"xvcmpgtdp" , XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6554 | {"xvcmpgtdp." , XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6555 | {"xvcvdpsxws" , XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6556 | {"xvrdpiz" , XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6557 | {"xvredp" , XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6558 | {"xvmuldp" , XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6559 | {"xvmsubadp" , XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6560 | {"xvcmpgedp" , XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6561 | {"xvcmpgedp." , XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6562 | {"xvcvuxwdp" , XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6563 | {"xvrdpip" , XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6564 | {"xvtsqrtdp" , XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, |
6565 | {"xvrdpic" , XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6566 | {"xvdivdp" , XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6567 | {"xvmsubmdp" , XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6568 | {"xvcvsxwdp" , XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6569 | {"xvrdpim" , XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6570 | {"xvtdivdp" , XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, |
6571 | {"xsmaxcdp" , XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, |
6572 | {"xsnmaddasp" , XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, |
6573 | {"xxland" , XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6574 | {"xscvdpsp" , XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6575 | {"xscvdpspn" , XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, |
6576 | {"xsmincdp" , XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, |
6577 | {"xsnmaddmsp" , XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, |
6578 | {"xxlandc" , XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6579 | {"xsrsp" , XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, |
6580 | {"xsmaxjdp" , XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, |
6581 | {"xsnmsubasp" , XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, |
6582 | {"xxlor" , XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6583 | {"xscvuxdsp" , XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, |
6584 | {"xststdcsp" , XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}}, |
6585 | {"xsminjdp" , XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, |
6586 | {"xsnmsubmsp" , XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, |
6587 | {"xxlxor" , XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6588 | {"xscvsxdsp" , XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, |
6589 | {"xsmaxdp" , XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6590 | {"xsnmaddadp" , XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6591 | {"xxlnor" , XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6592 | {"xscvdpuxds" , XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6593 | {"xscvspdp" , XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6594 | {"xscvspdpn" , XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, |
6595 | {"xsmindp" , XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6596 | {"xsnmaddmdp" , XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6597 | {"xxlorc" , XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, |
6598 | {"xscvdpsxds" , XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6599 | {"xsabsdp" , XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6600 | {"xsxexpdp" , XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, |
6601 | {"xsxsigdp" , XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, |
6602 | {"xscvhpdp" , XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
6603 | {"xscvdphp" , XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
6604 | {"xscpsgndp" , XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6605 | {"xsnmsubadp" , XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6606 | {"xxlnand" , XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, |
6607 | {"xscvuxddp" , XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6608 | {"xsnabsdp" , XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6609 | {"xststdcdp" , XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}}, |
6610 | {"xsnmsubmdp" , XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6611 | {"xxleqv" , XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, |
6612 | {"xscvsxddp" , XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6613 | {"xsnegdp" , XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6614 | {"xvmaxsp" , XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6615 | {"xvnmaddasp" , XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6616 | {"xvcvspuxds" , XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6617 | {"xvcvdpsp" , XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6618 | {"xvminsp" , XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6619 | {"xvnmaddmsp" , XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6620 | {"xvcvspsxds" , XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6621 | {"xvabssp" , XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6622 | {"xvmovsp" , XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}}, |
6623 | {"xvcpsgnsp" , XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6624 | {"xvnmsubasp" , XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6625 | {"xvcvuxdsp" , XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6626 | {"xvnabssp" , XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6627 | {"xvtstdcsp" , XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}}, |
6628 | {"xviexpsp" , XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, |
6629 | {"xvnmsubmsp" , XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6630 | {"xvcvsxdsp" , XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6631 | {"xvnegsp" , XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6632 | {"xvmaxdp" , XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6633 | {"xvnmaddadp" , XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6634 | {"xvcvdpuxds" , XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6635 | {"xvcvspdp" , XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6636 | {"xsiexpdp" , X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}}, |
6637 | {"xvmindp" , XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6638 | {"xvnmaddmdp" , XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6639 | {"xvcvdpsxds" , XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6640 | {"xvabsdp" , XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6641 | {"xvxexpdp" , XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
6642 | {"xvxsigdp" , XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
6643 | {"xxbrh" , XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
6644 | {"xvxexpsp" , XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
6645 | {"xvxsigsp" , XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
6646 | {"xxbrw" , XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
6647 | {"xxbrd" , XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
6648 | {"xvcvhpsp" , XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
6649 | {"xvcvsphp" , XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
6650 | {"xxbrq" , XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, |
6651 | {"xvmovdp" , XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}}, |
6652 | {"xvcpsgndp" , XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6653 | {"xvnmsubadp" , XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6654 | {"xvcvuxddp" , XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6655 | {"xvnabsdp" , XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6656 | {"xvtstdcdp" , XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}}, |
6657 | {"xviexpdp" , XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, |
6658 | {"xvnmsubmdp" , XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, |
6659 | {"xvcvsxddp" , XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6660 | {"xvnegdp" , XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, |
6661 | |
6662 | {"psq_st" , OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, |
6663 | {"stfq" , OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, |
6664 | |
6665 | {"lxv" , DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}}, |
6666 | {"stxv" , DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}}, |
6667 | {"stxsd" , DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, |
6668 | {"stxssp" , DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, |
6669 | {"stfdp" , OP(61), OP_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}}, |
6670 | {"psq_stu" , OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, |
6671 | {"stfqu" , OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, |
6672 | |
6673 | {"std" , DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}}, |
6674 | {"stdu" , DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}}, |
6675 | {"stq" , DSO(62,2), DS_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}}, |
6676 | |
6677 | {"fcmpu" , X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}}, |
6678 | |
6679 | {"daddq" , XRC(63,2,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
6680 | {"daddq." , XRC(63,2,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
6681 | |
6682 | {"dquaq" , ZRC(63,3,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}}, |
6683 | {"dquaq." , ZRC(63,3,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}}, |
6684 | |
6685 | {"xsaddqp" , XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6686 | {"xsaddqpo" , XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6687 | |
6688 | {"xsrqpi" , ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, |
6689 | {"xsrqpix" , ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, |
6690 | |
6691 | {"fcpsgn" , XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}}, |
6692 | {"fcpsgn." , XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}}, |
6693 | |
6694 | {"frsp" , XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
6695 | {"frsp." , XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
6696 | |
6697 | {"fctiw" , XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, |
6698 | {"fcir" , XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, |
6699 | {"fctiw." , XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, |
6700 | {"fcir." , XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, |
6701 | |
6702 | {"fctiwz" , XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, |
6703 | {"fcirz" , XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, |
6704 | {"fctiwz." , XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, |
6705 | {"fcirz." , XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, |
6706 | |
6707 | {"fdiv" , A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
6708 | {"fd" , A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, |
6709 | {"fdiv." , A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
6710 | {"fd." , A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, |
6711 | |
6712 | {"fsub" , A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
6713 | {"fs" , A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, |
6714 | {"fsub." , A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
6715 | {"fs." , A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, |
6716 | |
6717 | {"fadd" , A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
6718 | {"fa" , A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, |
6719 | {"fadd." , A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, |
6720 | {"fa." , A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, |
6721 | |
6722 | {"fsqrt" , A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}}, |
6723 | {"fsqrt." , A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}}, |
6724 | |
6725 | {"fsel" , A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6726 | {"fsel." , A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6727 | |
6728 | {"fre" , A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
6729 | {"fre" , A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, |
6730 | {"fre." , A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
6731 | {"fre." , A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, |
6732 | |
6733 | {"fmul" , A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, |
6734 | {"fm" , A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}}, |
6735 | {"fmul." , A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, |
6736 | {"fm." , A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}}, |
6737 | |
6738 | {"frsqrte" , A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
6739 | {"frsqrte" , A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, |
6740 | {"frsqrte." , A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
6741 | {"frsqrte." , A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, |
6742 | |
6743 | {"fmsub" , A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6744 | {"fms" , A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, |
6745 | {"fmsub." , A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6746 | {"fms." , A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, |
6747 | |
6748 | {"fmadd" , A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6749 | {"fma" , A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, |
6750 | {"fmadd." , A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6751 | {"fma." , A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, |
6752 | |
6753 | {"fnmsub" , A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6754 | {"fnms" , A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, |
6755 | {"fnmsub." , A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6756 | {"fnms." , A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, |
6757 | |
6758 | {"fnmadd" , A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6759 | {"fnma" , A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, |
6760 | {"fnmadd." , A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, |
6761 | {"fnma." , A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, |
6762 | |
6763 | {"fcmpo" , X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}}, |
6764 | |
6765 | {"dmulq" , XRC(63,34,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
6766 | {"dmulq." , XRC(63,34,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
6767 | |
6768 | {"drrndq" , ZRC(63,35,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}}, |
6769 | {"drrndq." , ZRC(63,35,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}}, |
6770 | |
6771 | {"xsmulqp" , XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6772 | {"xsmulqpo" , XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6773 | |
6774 | {"xsrqpxp" , Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, |
6775 | |
6776 | {"mtfsb1" , XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}}, |
6777 | {"mtfsb1." , XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}}, |
6778 | |
6779 | {"fneg" , XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
6780 | {"fneg." , XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
6781 | |
6782 | {"mcrfs" , X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, |
6783 | |
6784 | {"dscliq" , ZRC(63,66,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, |
6785 | {"dscliq." , ZRC(63,66,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, |
6786 | |
6787 | {"dquaiq" , ZRC(63,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, |
6788 | {"dquaiq." , ZRC(63,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, |
6789 | |
6790 | {"mtfsb0" , XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}}, |
6791 | {"mtfsb0." , XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}}, |
6792 | |
6793 | {"fmr" , XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
6794 | {"fmr." , XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
6795 | |
6796 | {"dscriq" , ZRC(63,98,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, |
6797 | {"dscriq." , ZRC(63,98,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, |
6798 | |
6799 | {"drintxq" , ZRC(63,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, |
6800 | {"drintxq." , ZRC(63,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, |
6801 | |
6802 | {"xscpsgnqp" , X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6803 | |
6804 | {"ftdiv" , X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}}, |
6805 | |
6806 | {"dcmpoq" , X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, |
6807 | |
6808 | {"xscmpoqp" , X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, |
6809 | |
6810 | {"mtfsfi" , XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}}, |
6811 | {"mtfsfi" , XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}}, |
6812 | {"mtfsfi." , XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}}, |
6813 | {"mtfsfi." , XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}}, |
6814 | |
6815 | {"fnabs" , XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
6816 | {"fnabs." , XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
6817 | |
6818 | {"fctiwu" , XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
6819 | {"fctiwu." , XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
6820 | {"fctiwuz" , XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
6821 | {"fctiwuz." , XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, |
6822 | |
6823 | {"ftsqrt" , X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}}, |
6824 | |
6825 | {"dtstexq" , X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, |
6826 | |
6827 | {"xscmpexpqp" , X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, |
6828 | |
6829 | {"dtstdcq" , Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}}, |
6830 | {"dtstdgq" , Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}}, |
6831 | |
6832 | {"drintnq" , ZRC(63,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, |
6833 | {"drintnq." , ZRC(63,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, |
6834 | |
6835 | {"dctqpq" , XRC(63,258,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}}, |
6836 | {"dctqpq." , XRC(63,258,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}}, |
6837 | |
6838 | {"fabs" , XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
6839 | {"fabs." , XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, |
6840 | |
6841 | {"dctfixq" , XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, |
6842 | {"dctfixq." , XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, |
6843 | |
6844 | {"ddedpdq" , XRC(63,322,0), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}}, |
6845 | {"ddedpdq." , XRC(63,322,1), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}}, |
6846 | |
6847 | {"dxexq" , XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, |
6848 | {"dxexq." , XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, |
6849 | |
6850 | {"xsmaddqp" , XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6851 | {"xsmaddqpo" , XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6852 | |
6853 | {"frin" , XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
6854 | {"frin." , XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
6855 | |
6856 | {"xsmsubqp" , XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6857 | {"xsmsubqpo" , XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6858 | |
6859 | {"friz" , XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
6860 | {"friz." , XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
6861 | |
6862 | {"xsnmaddqp" , XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6863 | {"xsnmaddqpo" , XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6864 | |
6865 | {"frip" , XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
6866 | {"frip." , XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
6867 | |
6868 | {"xsnmsubqp" , XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6869 | {"xsnmsubqpo" , XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6870 | |
6871 | {"frim" , XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
6872 | {"frim." , XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, |
6873 | |
6874 | {"dsubq" , XRC(63,514,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
6875 | {"dsubq." , XRC(63,514,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
6876 | |
6877 | {"xssubqp" , XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6878 | {"xssubqpo" , XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6879 | |
6880 | {"ddivq" , XRC(63,546,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
6881 | {"ddivq." , XRC(63,546,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, |
6882 | |
6883 | {"xsdivqp" , XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6884 | {"xsdivqpo" , XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6885 | |
6886 | {"mffs" , XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, |
6887 | {"mffs." , XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, |
6888 | |
6889 | {"mffsce" , XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, |
6890 | {"mffscdrn" , XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, |
6891 | {"mffscdrni" , XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}}, |
6892 | {"mffscrn" , XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, |
6893 | {"mffscrni" , XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}}, |
6894 | {"mffsl" , XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, |
6895 | |
6896 | {"dcmpuq" , X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, |
6897 | |
6898 | {"xscmpuqp" , X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, |
6899 | |
6900 | {"dtstsfq" , X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}}, |
6901 | {"dtstsfiq" , X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}}, |
6902 | |
6903 | {"xststdcqp" , X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}}, |
6904 | |
6905 | {"mtfsf" , XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}}, |
6906 | {"mtfsf" , XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}}, |
6907 | {"mtfsf." , XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}}, |
6908 | {"mtfsf." , XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}}, |
6909 | |
6910 | {"drdpq" , XRC(63,770,0), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}}, |
6911 | {"drdpq." , XRC(63,770,1), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}}, |
6912 | |
6913 | {"dcffixq" , XRC(63,802,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}}, |
6914 | {"dcffixq." , XRC(63,802,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}}, |
6915 | |
6916 | {"xsabsqp" , XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
6917 | {"xsxexpqp" , XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
6918 | {"xsnabsqp" , XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
6919 | {"xsnegqp" , XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
6920 | {"xsxsigqp" , XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
6921 | {"xssqrtqp" , XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
6922 | {"xssqrtqpo" , XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
6923 | |
6924 | {"fctid" , XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, |
6925 | {"fctid" , XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, |
6926 | {"fctid." , XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, |
6927 | {"fctid." , XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, |
6928 | |
6929 | {"fctidz" , XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, |
6930 | {"fctidz" , XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, |
6931 | {"fctidz." , XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, |
6932 | {"fctidz." , XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, |
6933 | |
6934 | {"denbcdq" , XRC(63,834,0), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, |
6935 | {"denbcdq." , XRC(63,834,1), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, |
6936 | |
6937 | {"xscvqpuwz" , XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
6938 | {"xscvudqp" , XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
6939 | {"xscvqpswz" , XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
6940 | {"xscvsdqp" , XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
6941 | {"xscvqpudz" , XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
6942 | {"xscvqpdp" , XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
6943 | {"xscvqpdpo" , XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
6944 | {"xscvdpqp" , XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
6945 | {"xscvqpsdz" , XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, |
6946 | |
6947 | {"fmrgow" , X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}}, |
6948 | |
6949 | {"fcfid" , XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, |
6950 | {"fcfid" , XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, |
6951 | {"fcfid." , XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, |
6952 | {"fcfid." , XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, |
6953 | |
6954 | {"diexq" , XRC(63,866,0), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}}, |
6955 | {"diexq." , XRC(63,866,1), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}}, |
6956 | |
6957 | {"xsiexpqp" , X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, |
6958 | |
6959 | {"fctidu" , XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
6960 | {"fctidu." , XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
6961 | |
6962 | {"fctiduz" , XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
6963 | {"fctiduz." , XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
6964 | |
6965 | {"fmrgew" , X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}}, |
6966 | |
6967 | {"fcfidu" , XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
6968 | {"fcfidu." , XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, |
6969 | }; |
6970 | |
6971 | const int powerpc_num_opcodes = |
6972 | sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); |
6973 | |
6974 | /* The VLE opcode table. |
6975 | |
6976 | The format of this opcode table is the same as the main opcode table. */ |
6977 | |
6978 | const struct powerpc_opcode vle_opcodes[] = { |
6979 | {"se_illegal" , C(0), C_MASK, PPCVLE, 0, {}}, |
6980 | {"se_isync" , C(1), C_MASK, PPCVLE, 0, {}}, |
6981 | {"se_sc" , C(2), C_MASK, PPCVLE, 0, {}}, |
6982 | {"se_blr" , C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}}, |
6983 | {"se_blrl" , C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}}, |
6984 | {"se_bctr" , C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}}, |
6985 | {"se_bctrl" , C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}}, |
6986 | {"se_rfi" , C(8), C_MASK, PPCVLE, 0, {}}, |
6987 | {"se_rfci" , C(9), C_MASK, PPCVLE, 0, {}}, |
6988 | {"se_rfdi" , C(10), C_MASK, PPCVLE, 0, {}}, |
6989 | {"se_rfmci" , C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}}, |
6990 | {"se_not" , SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}}, |
6991 | {"se_neg" , SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}}, |
6992 | {"se_mflr" , SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}}, |
6993 | {"se_mtlr" , SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}}, |
6994 | {"se_mfctr" , SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}}, |
6995 | {"se_mtctr" , SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}}, |
6996 | {"se_extzb" , SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}}, |
6997 | {"se_extsb" , SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}}, |
6998 | {"se_extzh" , SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}}, |
6999 | {"se_extsh" , SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}}, |
7000 | {"se_mr" , SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, |
7001 | {"se_mtar" , SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}}, |
7002 | {"se_mfar" , SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}}, |
7003 | {"se_add" , SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, |
7004 | {"se_mullw" , SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, |
7005 | {"se_sub" , SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, |
7006 | {"se_subf" , SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, |
7007 | {"se_cmp" , SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, |
7008 | {"se_cmpl" , SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, |
7009 | {"se_cmph" , SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, |
7010 | {"se_cmphl" , SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, |
7011 | |
7012 | {"e_cmpi" , SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, |
7013 | {"e_cmpwi" , SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, |
7014 | {"e_cmpli" , SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, |
7015 | {"e_cmplwi" , SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, |
7016 | {"e_addi" , SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, |
7017 | {"e_subi" , SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, |
7018 | {"e_addi." , SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, |
7019 | {"e_addic" , SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, |
7020 | {"e_subic" , SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, |
7021 | {"e_addic." , SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, |
7022 | {"e_subic." , SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, |
7023 | {"e_mulli" , SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, |
7024 | {"e_subfic" , SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, |
7025 | {"e_subfic." , SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, |
7026 | {"e_andi" , SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, |
7027 | {"e_andi." , SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, |
7028 | {"e_nop" , SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}}, |
7029 | {"e_ori" , SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, |
7030 | {"e_ori." , SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, |
7031 | {"e_xori" , SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, |
7032 | {"e_xori." , SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, |
7033 | {"e_lbzu" , OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, |
7034 | {"e_lhau" , OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, |
7035 | {"e_lhzu" , OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, |
7036 | {"e_lmw" , OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, |
7037 | {"e_lwzu" , OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, |
7038 | {"e_stbu" , OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, |
7039 | {"e_sthu" , OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, |
7040 | {"e_stwu" , OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, |
7041 | {"e_stmw" , OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, |
7042 | {"e_ldmvgprw" , OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
7043 | {"e_stmvgprw" , OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
7044 | {"e_ldmvsprw" , OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
7045 | {"e_stmvsprw" , OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
7046 | {"e_ldmvsrrw" , OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
7047 | {"e_stmvsrrw" , OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
7048 | {"e_ldmvcsrrw" , OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
7049 | {"e_stmvcsrrw" , OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
7050 | {"e_ldmvdsrrw" , OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
7051 | {"e_stmvdsrrw" , OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, |
7052 | {"e_add16i" , OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}}, |
7053 | {"e_la" , OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, |
7054 | {"e_sub16i" , OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}}, |
7055 | |
7056 | {"se_addi" , SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, |
7057 | {"se_cmpli" , SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, |
7058 | {"se_subi" , SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, |
7059 | {"se_subi." , SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, |
7060 | {"se_cmpi" , SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, |
7061 | {"se_bmaski" , SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, |
7062 | {"se_andi" , SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, |
7063 | |
7064 | {"e_lbz" , OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, |
7065 | {"e_stb" , OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, |
7066 | {"e_lha" , OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, |
7067 | |
7068 | {"se_srw" , SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, |
7069 | {"se_sraw" , SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, |
7070 | {"se_slw" , SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, |
7071 | {"se_nop" , SE_RR(17,0), 0xffff, PPCVLE, 0, {0}}, |
7072 | {"se_or" , SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, |
7073 | {"se_andc" , SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, |
7074 | {"se_and" , SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, |
7075 | {"se_and." , SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, |
7076 | {"se_li" , IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}}, |
7077 | |
7078 | {"e_lwz" , OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, |
7079 | {"e_stw" , OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, |
7080 | {"e_lhz" , OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, |
7081 | {"e_sth" , OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, |
7082 | |
7083 | {"se_bclri" , SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, |
7084 | {"se_bgeni" , SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, |
7085 | {"se_bseti" , SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, |
7086 | {"se_btsti" , SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, |
7087 | {"se_srwi" , SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, |
7088 | {"se_srawi" , SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, |
7089 | {"se_slwi" , SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, |
7090 | |
7091 | {"e_lis" , I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, |
7092 | {"e_and2is." , I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, |
7093 | {"e_or2is" , I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, |
7094 | {"e_and2i." , I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, |
7095 | {"e_or2i" , I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, |
7096 | {"e_cmphl16i" , IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}}, |
7097 | {"e_cmph16i" , IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, |
7098 | {"e_cmpl16i" , I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}}, |
7099 | {"e_mull2i" , I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, |
7100 | {"e_cmp16i" , IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, |
7101 | {"e_sub2is" , I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}}, |
7102 | {"e_add2is" , I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, |
7103 | {"e_sub2i." , I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}}, |
7104 | {"e_add2i." , I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, |
7105 | {"e_li" , LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}}, |
7106 | {"e_rlwimi" , M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}}, |
7107 | {"e_rlwinm" , M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}}, |
7108 | {"e_b" , BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}}, |
7109 | {"e_bl" , BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}}, |
7110 | {"e_bdnz" , EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}}, |
7111 | {"e_bdnzl" , EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}}, |
7112 | {"e_bdz" , EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}}, |
7113 | {"e_bdzl" , EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}}, |
7114 | {"e_bge" , EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7115 | {"e_bgel" , EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7116 | {"e_bnl" , EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7117 | {"e_bnll" , EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7118 | {"e_blt" , EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7119 | {"e_bltl" , EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7120 | {"e_bgt" , EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7121 | {"e_bgtl" , EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7122 | {"e_ble" , EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7123 | {"e_blel" , EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7124 | {"e_bng" , EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7125 | {"e_bngl" , EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7126 | {"e_bne" , EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7127 | {"e_bnel" , EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7128 | {"e_beq" , EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7129 | {"e_beql" , EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7130 | {"e_bso" , EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7131 | {"e_bsol" , EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7132 | {"e_bun" , EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7133 | {"e_bunl" , EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7134 | {"e_bns" , EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7135 | {"e_bnsl" , EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7136 | {"e_bnu" , EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7137 | {"e_bnul" , EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}}, |
7138 | {"e_bc" , BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}}, |
7139 | {"e_bcl" , BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}}, |
7140 | |
7141 | {"e_bf" , EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, |
7142 | {"e_bfl" , EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, |
7143 | {"e_bt" , EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, |
7144 | {"e_btl" , EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}}, |
7145 | |
7146 | {"e_cmph" , X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, |
7147 | {"e_cmphl" , X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, |
7148 | {"e_crandc" , XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
7149 | {"e_crnand" , XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
7150 | {"e_crnot" , XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}}, |
7151 | {"e_crnor" , XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
7152 | {"e_crclr" , XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}}, |
7153 | {"e_crxor" , XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
7154 | {"e_mcrf" , XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}}, |
7155 | {"e_slwi" , EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, |
7156 | {"e_slwi." , EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, |
7157 | |
7158 | {"e_crand" , XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
7159 | |
7160 | {"e_rlw" , EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, |
7161 | {"e_rlw." , EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, |
7162 | |
7163 | {"e_crset" , XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}}, |
7164 | {"e_creqv" , XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
7165 | |
7166 | {"e_rlwi" , EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, |
7167 | {"e_rlwi." , EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, |
7168 | |
7169 | {"e_crorc" , XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
7170 | |
7171 | {"e_crmove" , XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}}, |
7172 | {"e_cror" , XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, |
7173 | |
7174 | {"mtmas1" , XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}}, |
7175 | |
7176 | {"e_srwi" , EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, |
7177 | {"e_srwi." , EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, |
7178 | |
7179 | {"se_lbz" , SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}}, |
7180 | |
7181 | {"se_stb" , SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}}, |
7182 | |
7183 | {"se_lhz" , SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}}, |
7184 | |
7185 | {"se_sth" , SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}}, |
7186 | |
7187 | {"se_lwz" , SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}}, |
7188 | |
7189 | {"se_stw" , SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}}, |
7190 | |
7191 | {"se_bge" , EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, |
7192 | {"se_bnl" , EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, |
7193 | {"se_ble" , EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, |
7194 | {"se_bng" , EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, |
7195 | {"se_bne" , EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}}, |
7196 | {"se_bns" , EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, |
7197 | {"se_bnu" , EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, |
7198 | {"se_bf" , EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}}, |
7199 | {"se_blt" , EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}}, |
7200 | {"se_bgt" , EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}}, |
7201 | {"se_beq" , EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}}, |
7202 | {"se_bso" , EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, |
7203 | {"se_bun" , EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}}, |
7204 | {"se_bt" , EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}}, |
7205 | {"se_bc" , BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}}, |
7206 | {"se_b" , BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}}, |
7207 | {"se_bl" , BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}}, |
7208 | }; |
7209 | |
7210 | const int vle_num_opcodes = |
7211 | sizeof (vle_opcodes) / sizeof (vle_opcodes[0]); |
7212 | |
7213 | /* The macro table. This is only used by the assembler. */ |
7214 | |
7215 | /* The expressions of the form (-x ! 31) & (x | 31) have the value 0 |
7216 | when x=0; 32-x when x is between 1 and 31; are negative if x is |
7217 | negative; and are 32 or more otherwise. This is what you want |
7218 | when, for instance, you are emulating a right shift by a |
7219 | rotate-left-and-mask, because the underlying instructions support |
7220 | shifts of size 0 but not shifts of size 32. By comparison, when |
7221 | extracting x bits from some word you want to use just 32-x, because |
7222 | the underlying instructions don't support extracting 0 bits but do |
7223 | support extracting the whole word (32 bits in this case). */ |
7224 | |
7225 | const struct powerpc_macro powerpc_macros[] = { |
7226 | {"extldi" , 4, PPC64, "rldicr %0,%1,%3,(%2)-1" }, |
7227 | {"extldi." , 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" }, |
7228 | {"extrdi" , 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)" }, |
7229 | {"extrdi." , 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)" }, |
7230 | {"insrdi" , 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" }, |
7231 | {"insrdi." , 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" }, |
7232 | {"rotrdi" , 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" }, |
7233 | {"rotrdi." , 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" }, |
7234 | {"sldi" , 3, PPC64, "rldicr %0,%1,%2,63-(%2)" }, |
7235 | {"sldi." , 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" }, |
7236 | {"srdi" , 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" }, |
7237 | {"srdi." , 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" }, |
7238 | {"clrrdi" , 3, PPC64, "rldicr %0,%1,0,63-(%2)" }, |
7239 | {"clrrdi." , 3, PPC64, "rldicr. %0,%1,0,63-(%2)" }, |
7240 | {"clrlsldi" , 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" }, |
7241 | {"clrlsldi." ,4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" }, |
7242 | |
7243 | {"extlwi" , 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, |
7244 | {"extlwi." , 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" }, |
7245 | {"extrwi" , 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, |
7246 | {"extrwi." , 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, |
7247 | {"inslwi" , 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, |
7248 | {"inslwi." , 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, |
7249 | {"insrwi" , 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, |
7250 | {"insrwi." , 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, |
7251 | {"rotrwi" , 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" }, |
7252 | {"rotrwi." , 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" }, |
7253 | {"slwi" , 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" }, |
7254 | {"sli" , 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" }, |
7255 | {"slwi." , 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" }, |
7256 | {"sli." , 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" }, |
7257 | {"srwi" , 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, |
7258 | {"sri" , 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, |
7259 | {"srwi." , 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, |
7260 | {"sri." , 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, |
7261 | {"clrrwi" , 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" }, |
7262 | {"clrrwi." , 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" }, |
7263 | {"clrlslwi" , 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, |
7264 | {"clrlslwi." ,4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, |
7265 | |
7266 | {"e_extlwi" , 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1" }, |
7267 | {"e_extrwi" , 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, |
7268 | {"e_inslwi" , 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, |
7269 | {"e_insrwi" , 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, |
7270 | {"e_rotlwi" , 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31" }, |
7271 | {"e_rotrwi" , 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" }, |
7272 | {"e_slwi" , 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)" }, |
7273 | {"e_srwi" , 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, |
7274 | {"e_clrlwi" , 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31" }, |
7275 | {"e_clrrwi" , 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)" }, |
7276 | {"e_clrlslwi" ,4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, |
7277 | }; |
7278 | |
7279 | const int powerpc_num_macros = |
7280 | sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); |
7281 | |