1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Support for SuperH MigoR Quarter VGA LCD Panel |
4 | * |
5 | * Copyright (C) 2008 Magnus Damm |
6 | * |
7 | * Based on lcd_powertip.c from Kenati Technologies Pvt Ltd. |
8 | * Copyright (c) 2007 Ujjwal Pande <ujjwal@kenati.com>, |
9 | */ |
10 | |
11 | #include <linux/delay.h> |
12 | #include <linux/err.h> |
13 | #include <linux/fb.h> |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> |
16 | #include <linux/module.h> |
17 | #include <linux/gpio.h> |
18 | #include <video/sh_mobile_lcdc.h> |
19 | #include <cpu/sh7722.h> |
20 | #include <mach/migor.h> |
21 | |
22 | /* LCD Module is a PH240320T according to board schematics. This module |
23 | * is made up of a 240x320 LCD hooked up to a R61505U (or HX8347-A01?) |
24 | * Driver IC. This IC is connected to the SH7722 built-in LCDC using a |
25 | * SYS-80 interface configured in 16 bit mode. |
26 | * |
27 | * Index 0: "Device Code Read" returns 0x1505. |
28 | */ |
29 | |
30 | static void reset_lcd_module(void) |
31 | { |
32 | gpio_set_value(gpio: GPIO_PTH2, value: 0); |
33 | mdelay(2); |
34 | gpio_set_value(gpio: GPIO_PTH2, value: 1); |
35 | mdelay(1); |
36 | } |
37 | |
38 | /* DB0-DB7 are connected to D1-D8, and DB8-DB15 to D10-D17 */ |
39 | |
40 | static unsigned long adjust_reg18(unsigned short data) |
41 | { |
42 | unsigned long tmp1, tmp2; |
43 | |
44 | tmp1 = (data<<1 | 0x00000001) & 0x000001FF; |
45 | tmp2 = (data<<2 | 0x00000200) & 0x0003FE00; |
46 | return tmp1 | tmp2; |
47 | } |
48 | |
49 | static void write_reg(void *sys_ops_handle, |
50 | struct sh_mobile_lcdc_sys_bus_ops *sys_ops, |
51 | unsigned short reg, unsigned short data) |
52 | { |
53 | sys_ops->write_index(sys_ops_handle, adjust_reg18(data: reg << 8 | data)); |
54 | } |
55 | |
56 | static void write_reg16(void *sys_ops_handle, |
57 | struct sh_mobile_lcdc_sys_bus_ops *sys_ops, |
58 | unsigned short reg, unsigned short data) |
59 | { |
60 | sys_ops->write_index(sys_ops_handle, adjust_reg18(data: reg)); |
61 | sys_ops->write_data(sys_ops_handle, adjust_reg18(data)); |
62 | } |
63 | |
64 | static unsigned long read_reg16(void *sys_ops_handle, |
65 | struct sh_mobile_lcdc_sys_bus_ops *sys_ops, |
66 | unsigned short reg) |
67 | { |
68 | unsigned long data; |
69 | |
70 | sys_ops->write_index(sys_ops_handle, adjust_reg18(data: reg)); |
71 | data = sys_ops->read_data(sys_ops_handle); |
72 | return ((data >> 1) & 0xff) | ((data >> 2) & 0xff00); |
73 | } |
74 | |
75 | static void migor_lcd_qvga_seq(void *sys_ops_handle, |
76 | struct sh_mobile_lcdc_sys_bus_ops *sys_ops, |
77 | unsigned short const *data, int no_data) |
78 | { |
79 | int i; |
80 | |
81 | for (i = 0; i < no_data; i += 2) |
82 | write_reg16(sys_ops_handle, sys_ops, reg: data[i], data: data[i + 1]); |
83 | } |
84 | |
85 | static const unsigned short sync_data[] = { |
86 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
87 | }; |
88 | |
89 | static const unsigned short magic0_data[] = { |
90 | 0x0060, 0x2700, 0x0008, 0x0808, 0x0090, 0x001A, 0x0007, 0x0001, |
91 | 0x0017, 0x0001, 0x0019, 0x0000, 0x0010, 0x17B0, 0x0011, 0x0116, |
92 | 0x0012, 0x0198, 0x0013, 0x1400, 0x0029, 0x000C, 0x0012, 0x01B8, |
93 | }; |
94 | |
95 | static const unsigned short magic1_data[] = { |
96 | 0x0030, 0x0307, 0x0031, 0x0303, 0x0032, 0x0603, 0x0033, 0x0202, |
97 | 0x0034, 0x0202, 0x0035, 0x0202, 0x0036, 0x1F1F, 0x0037, 0x0303, |
98 | 0x0038, 0x0303, 0x0039, 0x0603, 0x003A, 0x0202, 0x003B, 0x0102, |
99 | 0x003C, 0x0204, 0x003D, 0x0000, 0x0001, 0x0100, 0x0002, 0x0300, |
100 | 0x0003, 0x5028, 0x0020, 0x00ef, 0x0021, 0x0000, 0x0004, 0x0000, |
101 | 0x0009, 0x0000, 0x000A, 0x0008, 0x000C, 0x0000, 0x000D, 0x0000, |
102 | 0x0015, 0x8000, |
103 | }; |
104 | |
105 | static const unsigned short magic2_data[] = { |
106 | 0x0061, 0x0001, 0x0092, 0x0100, 0x0093, 0x0001, 0x0007, 0x0021, |
107 | }; |
108 | |
109 | static const unsigned short magic3_data[] = { |
110 | 0x0010, 0x16B0, 0x0011, 0x0111, 0x0007, 0x0061, |
111 | }; |
112 | |
113 | int migor_lcd_qvga_setup(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so) |
114 | { |
115 | unsigned long xres = 320; |
116 | unsigned long yres = 240; |
117 | int k; |
118 | |
119 | reset_lcd_module(); |
120 | migor_lcd_qvga_seq(sys_ops_handle: sohandle, sys_ops: so, data: sync_data, ARRAY_SIZE(sync_data)); |
121 | |
122 | if (read_reg16(sys_ops_handle: sohandle, sys_ops: so, reg: 0) != 0x1505) |
123 | return -ENODEV; |
124 | |
125 | pr_info("Migo-R QVGA LCD Module detected.\n" ); |
126 | |
127 | migor_lcd_qvga_seq(sys_ops_handle: sohandle, sys_ops: so, data: sync_data, ARRAY_SIZE(sync_data)); |
128 | write_reg16(sys_ops_handle: sohandle, sys_ops: so, reg: 0x00A4, data: 0x0001); |
129 | mdelay(10); |
130 | |
131 | migor_lcd_qvga_seq(sys_ops_handle: sohandle, sys_ops: so, data: magic0_data, ARRAY_SIZE(magic0_data)); |
132 | mdelay(100); |
133 | |
134 | migor_lcd_qvga_seq(sys_ops_handle: sohandle, sys_ops: so, data: magic1_data, ARRAY_SIZE(magic1_data)); |
135 | write_reg16(sys_ops_handle: sohandle, sys_ops: so, reg: 0x0050, data: 0xef - (yres - 1)); |
136 | write_reg16(sys_ops_handle: sohandle, sys_ops: so, reg: 0x0051, data: 0x00ef); |
137 | write_reg16(sys_ops_handle: sohandle, sys_ops: so, reg: 0x0052, data: 0x0000); |
138 | write_reg16(sys_ops_handle: sohandle, sys_ops: so, reg: 0x0053, data: xres - 1); |
139 | |
140 | migor_lcd_qvga_seq(sys_ops_handle: sohandle, sys_ops: so, data: magic2_data, ARRAY_SIZE(magic2_data)); |
141 | mdelay(10); |
142 | |
143 | migor_lcd_qvga_seq(sys_ops_handle: sohandle, sys_ops: so, data: magic3_data, ARRAY_SIZE(magic3_data)); |
144 | mdelay(40); |
145 | |
146 | /* clear GRAM to avoid displaying garbage */ |
147 | |
148 | write_reg16(sys_ops_handle: sohandle, sys_ops: so, reg: 0x0020, data: 0x0000); /* horiz addr */ |
149 | write_reg16(sys_ops_handle: sohandle, sys_ops: so, reg: 0x0021, data: 0x0000); /* vert addr */ |
150 | |
151 | for (k = 0; k < (xres * 256); k++) /* yes, 256 words per line */ |
152 | write_reg16(sys_ops_handle: sohandle, sys_ops: so, reg: 0x0022, data: 0x0000); |
153 | |
154 | write_reg16(sys_ops_handle: sohandle, sys_ops: so, reg: 0x0020, data: 0x0000); /* reset horiz addr */ |
155 | write_reg16(sys_ops_handle: sohandle, sys_ops: so, reg: 0x0021, data: 0x0000); /* reset vert addr */ |
156 | write_reg16(sys_ops_handle: sohandle, sys_ops: so, reg: 0x0007, data: 0x0173); |
157 | mdelay(40); |
158 | |
159 | /* enable display */ |
160 | write_reg(sys_ops_handle: sohandle, sys_ops: so, reg: 0x00, data: 0x22); |
161 | mdelay(100); |
162 | return 0; |
163 | } |
164 | |