1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. |
5 | * |
6 | * arch/shmedia/boot/compressed/head.S |
7 | * |
8 | * Copied from |
9 | * arch/shmedia/kernel/head.S |
10 | * which carried the copyright: |
11 | * Copyright (C) 2000, 2001 Paolo Alberelli |
12 | * |
13 | * Modification for compressed loader: |
14 | * Copyright (C) 2002 Stuart Menefy (stuart.menefy@st.com) |
15 | */ |
16 | #include <asm/cache.h> |
17 | #include <asm/tlb.h> |
18 | #include <cpu/mmu_context.h> |
19 | #include <cpu/registers.h> |
20 | |
21 | /* |
22 | * Fixed TLB entries to identity map the beginning of RAM |
23 | */ |
24 | #define MMUIR_TEXT_H 0x0000000000000003 | CONFIG_MEMORY_START |
25 | /* Enabled, Shared, ASID 0, Eff. Add. 0xA0000000 */ |
26 | #define MMUIR_TEXT_L 0x000000000000009a | CONFIG_MEMORY_START |
27 | /* 512 Mb, Cacheable (Write-back), execute, Not User, Ph. Add. */ |
28 | |
29 | #define MMUDR_CACHED_H 0x0000000000000003 | CONFIG_MEMORY_START |
30 | /* Enabled, Shared, ASID 0, Eff. Add. 0xA0000000 */ |
31 | #define MMUDR_CACHED_L 0x000000000000015a | CONFIG_MEMORY_START |
32 | /* 512 Mb, Cacheable (Write-back), read/write, Not User, Ph. Add. */ |
33 | |
34 | #define ICCR0_INIT_VAL ICCR0_ON | ICCR0_ICI /* ICE + ICI */ |
35 | #define ICCR1_INIT_VAL ICCR1_NOLOCK /* No locking */ |
36 | |
37 | #define OCCR0_INIT_VAL OCCR0_ON | OCCR0_OCI | OCCR0_WB /* OCE + OCI + WB */ |
38 | #define OCCR1_INIT_VAL OCCR1_NOLOCK /* No locking */ |
39 | |
40 | .text |
41 | |
42 | .global startup |
43 | startup: |
44 | /* |
45 | * Prevent speculative fetch on device memory due to |
46 | * uninitialized target registers. |
47 | * This must be executed before the first branch. |
48 | */ |
49 | ptabs/u r63, tr0 |
50 | ptabs/u r63, tr1 |
51 | ptabs/u r63, tr2 |
52 | ptabs/u r63, tr3 |
53 | ptabs/u r63, tr4 |
54 | ptabs/u r63, tr5 |
55 | ptabs/u r63, tr6 |
56 | ptabs/u r63, tr7 |
57 | synci |
58 | |
59 | /* |
60 | * Set initial TLB entries for cached and uncached regions. |
61 | * Note: PTA/BLINK is PIC code, PTABS/BLINK isn't ! |
62 | */ |
63 | /* Clear ITLBs */ |
64 | pta 1f, tr1 |
65 | movi ITLB_FIXED, r21 |
66 | movi ITLB_LAST_VAR_UNRESTRICTED+TLB_STEP, r22 |
67 | 1: putcfg r21, 0, r63 /* Clear MMUIR[n].PTEH.V */ |
68 | addi r21, TLB_STEP, r21 |
69 | bne r21, r22, tr1 |
70 | |
71 | /* Clear DTLBs */ |
72 | pta 1f, tr1 |
73 | movi DTLB_FIXED, r21 |
74 | movi DTLB_LAST_VAR_UNRESTRICTED+TLB_STEP, r22 |
75 | 1: putcfg r21, 0, r63 /* Clear MMUDR[n].PTEH.V */ |
76 | addi r21, TLB_STEP, r21 |
77 | bne r21, r22, tr1 |
78 | |
79 | /* Map one big (512Mb) page for ITLB */ |
80 | movi ITLB_FIXED, r21 |
81 | movi MMUIR_TEXT_L, r22 /* PTEL first */ |
82 | putcfg r21, 1, r22 /* Set MMUIR[0].PTEL */ |
83 | movi MMUIR_TEXT_H, r22 /* PTEH last */ |
84 | putcfg r21, 0, r22 /* Set MMUIR[0].PTEH */ |
85 | |
86 | /* Map one big CACHED (512Mb) page for DTLB */ |
87 | movi DTLB_FIXED, r21 |
88 | movi MMUDR_CACHED_L, r22 /* PTEL first */ |
89 | putcfg r21, 1, r22 /* Set MMUDR[0].PTEL */ |
90 | movi MMUDR_CACHED_H, r22 /* PTEH last */ |
91 | putcfg r21, 0, r22 /* Set MMUDR[0].PTEH */ |
92 | |
93 | /* ICache */ |
94 | movi ICCR_BASE, r21 |
95 | movi ICCR0_INIT_VAL, r22 |
96 | movi ICCR1_INIT_VAL, r23 |
97 | putcfg r21, ICCR_REG0, r22 |
98 | putcfg r21, ICCR_REG1, r23 |
99 | synci |
100 | |
101 | /* OCache */ |
102 | movi OCCR_BASE, r21 |
103 | movi OCCR0_INIT_VAL, r22 |
104 | movi OCCR1_INIT_VAL, r23 |
105 | putcfg r21, OCCR_REG0, r22 |
106 | putcfg r21, OCCR_REG1, r23 |
107 | synco |
108 | |
109 | /* |
110 | * Enable the MMU. |
111 | * From here-on code can be non-PIC. |
112 | */ |
113 | movi SR_HARMLESS | SR_ENABLE_MMU, r22 |
114 | putcon r22, SSR |
115 | movi 1f, r22 |
116 | putcon r22, SPC |
117 | synco |
118 | rte /* And now go into the hyperspace ... */ |
119 | 1: /* ... that's the next instruction ! */ |
120 | |
121 | /* Set initial stack pointer */ |
122 | movi datalabel stack_start, r0 |
123 | ld.l r0, 0, r15 |
124 | |
125 | /* |
126 | * Clear bss |
127 | */ |
128 | pt 1f, tr1 |
129 | movi datalabel __bss_start, r22 |
130 | movi datalabel _end, r23 |
131 | 1: st.l r22, 0, r63 |
132 | addi r22, 4, r22 |
133 | bne r22, r23, tr1 |
134 | |
135 | /* |
136 | * Decompress the kernel. |
137 | */ |
138 | pt decompress_kernel, tr0 |
139 | blink tr0, r18 |
140 | |
141 | /* |
142 | * Disable the MMU. |
143 | */ |
144 | movi SR_HARMLESS, r22 |
145 | putcon r22, SSR |
146 | movi 1f, r22 |
147 | putcon r22, SPC |
148 | synco |
149 | rte /* And now go into the hyperspace ... */ |
150 | 1: /* ... that's the next instruction ! */ |
151 | |
152 | /* Jump into the decompressed kernel */ |
153 | movi datalabel (CONFIG_MEMORY_START + 0x2000)+1, r19 |
154 | ptabs r19, tr0 |
155 | blink tr0, r18 |
156 | |
157 | /* Shouldn't return here, but just in case, loop forever */ |
158 | pt 1f, tr0 |
159 | 1: blink tr0, r63 |
160 | |