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| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
|---|---|
| 2 | #ifndef __ASM_SH_HITACHI_SE7343_H |
| 3 | #define __ASM_SH_HITACHI_SE7343_H |
| 4 | |
| 5 | /* |
| 6 | * include/asm-sh/se/se7343.h |
| 7 | * |
| 8 | * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> |
| 9 | * |
| 10 | * SH-Mobile SolutionEngine 7343 support |
| 11 | */ |
| 12 | #include <linux/sh_intc.h> |
| 13 | |
| 14 | /* Box specific addresses. */ |
| 15 | |
| 16 | /* Area 0 */ |
| 17 | #define PA_ROM 0x00000000 /* EPROM */ |
| 18 | #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */ |
| 19 | #define PA_FROM 0x00400000 /* Flash ROM */ |
| 20 | #define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */ |
| 21 | #define PA_SRAM 0x00800000 /* SRAM */ |
| 22 | #define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */ |
| 23 | /* Area 1 */ |
| 24 | #define PA_EXT1 0x04000000 |
| 25 | #define PA_EXT1_SIZE 0x04000000 |
| 26 | /* Area 2 */ |
| 27 | #define PA_EXT2 0x08000000 |
| 28 | #define PA_EXT2_SIZE 0x04000000 |
| 29 | /* Area 3 */ |
| 30 | #define PA_SDRAM 0x0c000000 |
| 31 | #define PA_SDRAM_SIZE 0x04000000 |
| 32 | /* Area 4 */ |
| 33 | #define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */ |
| 34 | #define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */ |
| 35 | #define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */ |
| 36 | #define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */ |
| 37 | #define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */ |
| 38 | #define MRSHPC_OPTION (PA_MRSHPC + 6) |
| 39 | #define MRSHPC_CSR (PA_MRSHPC + 8) |
| 40 | #define MRSHPC_ISR (PA_MRSHPC + 10) |
| 41 | #define MRSHPC_ICR (PA_MRSHPC + 12) |
| 42 | #define MRSHPC_CPWCR (PA_MRSHPC + 14) |
| 43 | #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) |
| 44 | #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) |
| 45 | #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) |
| 46 | #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) |
| 47 | #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) |
| 48 | #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) |
| 49 | #define MRSHPC_CDCR (PA_MRSHPC + 28) |
| 50 | #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) |
| 51 | #define PA_LED 0xb0C00000 /* LED */ |
| 52 | #define LED_SHIFT 0 |
| 53 | #define PA_DIPSW 0xb0900000 /* Dip switch 31 */ |
| 54 | /* Area 5 */ |
| 55 | #define PA_EXT5 0x14000000 |
| 56 | #define PA_EXT5_SIZE 0x04000000 |
| 57 | /* Area 6 */ |
| 58 | #define PA_LCD1 0xb8000000 |
| 59 | #define PA_LCD2 0xb8800000 |
| 60 | |
| 61 | #define PORT_PACR 0xA4050100 |
| 62 | #define PORT_PBCR 0xA4050102 |
| 63 | #define PORT_PCCR 0xA4050104 |
| 64 | #define PORT_PDCR 0xA4050106 |
| 65 | #define PORT_PECR 0xA4050108 |
| 66 | #define PORT_PFCR 0xA405010A |
| 67 | #define PORT_PGCR 0xA405010C |
| 68 | #define PORT_PHCR 0xA405010E |
| 69 | #define PORT_PJCR 0xA4050110 |
| 70 | #define PORT_PKCR 0xA4050112 |
| 71 | #define PORT_PLCR 0xA4050114 |
| 72 | #define PORT_PMCR 0xA4050116 |
| 73 | #define PORT_PNCR 0xA4050118 |
| 74 | #define PORT_PQCR 0xA405011A |
| 75 | #define PORT_PRCR 0xA405011C |
| 76 | #define PORT_PSCR 0xA405011E |
| 77 | #define PORT_PTCR 0xA4050140 |
| 78 | #define PORT_PUCR 0xA4050142 |
| 79 | #define PORT_PVCR 0xA4050144 |
| 80 | #define PORT_PWCR 0xA4050146 |
| 81 | #define PORT_PYCR 0xA4050148 |
| 82 | #define PORT_PZCR 0xA405014A |
| 83 | |
| 84 | #define PORT_PSELA 0xA405014C |
| 85 | #define PORT_PSELB 0xA405014E |
| 86 | #define PORT_PSELC 0xA4050150 |
| 87 | #define PORT_PSELD 0xA4050152 |
| 88 | #define PORT_PSELE 0xA4050154 |
| 89 | |
| 90 | #define PORT_HIZCRA 0xA4050156 |
| 91 | #define PORT_HIZCRB 0xA4050158 |
| 92 | #define PORT_HIZCRC 0xA405015C |
| 93 | |
| 94 | #define PORT_DRVCR 0xA4050180 |
| 95 | |
| 96 | #define PORT_PADR 0xA4050120 |
| 97 | #define PORT_PBDR 0xA4050122 |
| 98 | #define PORT_PCDR 0xA4050124 |
| 99 | #define PORT_PDDR 0xA4050126 |
| 100 | #define PORT_PEDR 0xA4050128 |
| 101 | #define PORT_PFDR 0xA405012A |
| 102 | #define PORT_PGDR 0xA405012C |
| 103 | #define PORT_PHDR 0xA405012E |
| 104 | #define PORT_PJDR 0xA4050130 |
| 105 | #define PORT_PKDR 0xA4050132 |
| 106 | #define PORT_PLDR 0xA4050134 |
| 107 | #define PORT_PMDR 0xA4050136 |
| 108 | #define PORT_PNDR 0xA4050138 |
| 109 | #define PORT_PQDR 0xA405013A |
| 110 | #define PORT_PRDR 0xA405013C |
| 111 | #define PORT_PTDR 0xA4050160 |
| 112 | #define PORT_PUDR 0xA4050162 |
| 113 | #define PORT_PVDR 0xA4050164 |
| 114 | #define PORT_PWDR 0xA4050166 |
| 115 | #define PORT_PYDR 0xA4050168 |
| 116 | |
| 117 | #define FPGA_IN 0xb1400000 |
| 118 | #define FPGA_OUT 0xb1400002 |
| 119 | |
| 120 | #define IRQ0_IRQ evt2irq(0x600) |
| 121 | #define IRQ1_IRQ evt2irq(0x620) |
| 122 | #define IRQ4_IRQ evt2irq(0x680) |
| 123 | #define IRQ5_IRQ evt2irq(0x6a0) |
| 124 | |
| 125 | #define SE7343_FPGA_IRQ_MRSHPC0 0 |
| 126 | #define SE7343_FPGA_IRQ_MRSHPC1 1 |
| 127 | #define SE7343_FPGA_IRQ_MRSHPC2 2 |
| 128 | #define SE7343_FPGA_IRQ_MRSHPC3 3 |
| 129 | #define SE7343_FPGA_IRQ_SMC 6 /* EXT_IRQ2 */ |
| 130 | #define SE7343_FPGA_IRQ_USB 8 |
| 131 | #define SE7343_FPGA_IRQ_UARTA 10 |
| 132 | #define SE7343_FPGA_IRQ_UARTB 11 |
| 133 | |
| 134 | #define SE7343_FPGA_IRQ_NR 12 |
| 135 | |
| 136 | struct irq_domain; |
| 137 | |
| 138 | /* arch/sh/boards/se/7343/irq.c */ |
| 139 | extern struct irq_domain *se7343_irq_domain; |
| 140 | |
| 141 | void init_7343se_IRQ(void); |
| 142 | |
| 143 | #endif /* __ASM_SH_HITACHI_SE7343_H */ |
| 144 |
Warning: This file is not a C or C++ file. It does not have highlighting.