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1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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2 | #ifndef __ASM_SH_HITACHI_7751SE_H |
3 | #define __ASM_SH_HITACHI_7751SE_H |
4 | |
5 | /* |
6 | * linux/include/asm-sh/hitachi_7751se.h |
7 | * |
8 | * Copyright (C) 2000 Kazumoto Kojima |
9 | * |
10 | * Hitachi SolutionEngine support |
11 | |
12 | * Modified for 7751 Solution Engine by |
13 | * Ian da Silva and Jeremy Siegel, 2001. |
14 | */ |
15 | #include <linux/sh_intc.h> |
16 | |
17 | /* Box specific addresses. */ |
18 | |
19 | #define PA_ROM 0x00000000 /* EPROM */ |
20 | #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ |
21 | #define PA_FROM 0x01000000 /* EPROM */ |
22 | #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ |
23 | #define PA_EXT1 0x04000000 |
24 | #define PA_EXT1_SIZE 0x04000000 |
25 | #define PA_EXT2 0x08000000 |
26 | #define PA_EXT2_SIZE 0x04000000 |
27 | #define PA_SDRAM 0x0c000000 |
28 | #define PA_SDRAM_SIZE 0x04000000 |
29 | |
30 | #define PA_EXT4 0x12000000 |
31 | #define PA_EXT4_SIZE 0x02000000 |
32 | #define PA_EXT5 0x14000000 |
33 | #define PA_EXT5_SIZE 0x04000000 |
34 | #define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ |
35 | |
36 | #define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */ |
37 | #define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */ |
38 | #define PA_LED 0xba000000 /* LED */ |
39 | #define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */ |
40 | |
41 | #define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ |
42 | #define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ |
43 | #define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ |
44 | #define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ |
45 | #define MRSHPC_MODE (PA_MRSHPC + 4) |
46 | #define MRSHPC_OPTION (PA_MRSHPC + 6) |
47 | #define MRSHPC_CSR (PA_MRSHPC + 8) |
48 | #define MRSHPC_ISR (PA_MRSHPC + 10) |
49 | #define MRSHPC_ICR (PA_MRSHPC + 12) |
50 | #define MRSHPC_CPWCR (PA_MRSHPC + 14) |
51 | #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) |
52 | #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) |
53 | #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) |
54 | #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) |
55 | #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) |
56 | #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) |
57 | #define MRSHPC_CDCR (PA_MRSHPC + 28) |
58 | #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) |
59 | |
60 | #define BCR_ILCRA (PA_BCR + 0) |
61 | #define BCR_ILCRB (PA_BCR + 2) |
62 | #define BCR_ILCRC (PA_BCR + 4) |
63 | #define BCR_ILCRD (PA_BCR + 6) |
64 | #define BCR_ILCRE (PA_BCR + 8) |
65 | #define BCR_ILCRF (PA_BCR + 10) |
66 | #define BCR_ILCRG (PA_BCR + 12) |
67 | |
68 | #define IRQ_79C973 evt2irq(0x3a0) |
69 | |
70 | void init_7751se_IRQ(void); |
71 | |
72 | #define __IO_PREFIX sh7751se |
73 | #include <asm/io_generic.h> |
74 | |
75 | #endif /* __ASM_SH_HITACHI_7751SE_H */ |
76 |
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