1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * SH3 Setup code for SH7710, SH7712 |
4 | * |
5 | * Copyright (C) 2006 - 2009 Paul Mundt |
6 | * Copyright (C) 2007 Nobuhiro Iwamatsu |
7 | */ |
8 | #include <linux/platform_device.h> |
9 | #include <linux/init.h> |
10 | #include <linux/irq.h> |
11 | #include <linux/serial.h> |
12 | #include <linux/serial_sci.h> |
13 | #include <linux/sh_timer.h> |
14 | #include <linux/sh_intc.h> |
15 | #include <asm/rtc.h> |
16 | #include <asm/platform_early.h> |
17 | |
18 | enum { |
19 | UNUSED = 0, |
20 | |
21 | /* interrupt sources */ |
22 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, |
23 | DMAC1, SCIF0, SCIF1, DMAC2, IPSEC, |
24 | EDMAC0, EDMAC1, EDMAC2, |
25 | SIOF0, SIOF1, |
26 | |
27 | TMU0, TMU1, TMU2, |
28 | RTC, WDT, REF, |
29 | }; |
30 | |
31 | static struct intc_vect vectors[] __initdata = { |
32 | /* IRQ0->5 are handled in setup-sh3.c */ |
33 | INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820), |
34 | INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860), |
35 | INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0), |
36 | INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0), |
37 | INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920), |
38 | INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960), |
39 | INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0), |
40 | #ifdef CONFIG_CPU_SUBTYPE_SH7710 |
41 | INTC_VECT(IPSEC, 0xbe0), |
42 | #endif |
43 | INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20), |
44 | INTC_VECT(EDMAC2, 0xc40), |
45 | INTC_VECT(SIOF0, 0xe00), INTC_VECT(SIOF0, 0xe20), |
46 | INTC_VECT(SIOF0, 0xe40), INTC_VECT(SIOF0, 0xe60), |
47 | INTC_VECT(SIOF1, 0xe80), INTC_VECT(SIOF1, 0xea0), |
48 | INTC_VECT(SIOF1, 0xec0), INTC_VECT(SIOF1, 0xee0), |
49 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), |
50 | INTC_VECT(TMU2, 0x440), |
51 | INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), |
52 | INTC_VECT(RTC, 0x4c0), |
53 | INTC_VECT(WDT, 0x560), |
54 | INTC_VECT(REF, 0x580), |
55 | }; |
56 | |
57 | static struct intc_prio_reg prio_registers[] __initdata = { |
58 | { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, |
59 | { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, |
60 | { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, |
61 | { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } }, |
62 | { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } }, |
63 | { 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC, DMAC2 } }, |
64 | { 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } }, |
65 | { 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } }, |
66 | { 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } }, |
67 | }; |
68 | |
69 | static DECLARE_INTC_DESC(intc_desc, "sh7710" , vectors, NULL, |
70 | NULL, prio_registers, NULL); |
71 | |
72 | static struct resource rtc_resources[] = { |
73 | [0] = { |
74 | .start = 0xa413fec0, |
75 | .end = 0xa413fec0 + 0x1e, |
76 | .flags = IORESOURCE_IO, |
77 | }, |
78 | [1] = { |
79 | .start = evt2irq(0x480), |
80 | .flags = IORESOURCE_IRQ, |
81 | }, |
82 | }; |
83 | |
84 | static struct sh_rtc_platform_info rtc_info = { |
85 | .capabilities = RTC_CAP_4_DIGIT_YEAR, |
86 | }; |
87 | |
88 | static struct platform_device rtc_device = { |
89 | .name = "sh-rtc" , |
90 | .id = -1, |
91 | .num_resources = ARRAY_SIZE(rtc_resources), |
92 | .resource = rtc_resources, |
93 | .dev = { |
94 | .platform_data = &rtc_info, |
95 | }, |
96 | }; |
97 | |
98 | static struct plat_sci_port scif0_platform_data = { |
99 | .scscr = SCSCR_REIE | SCSCR_CKE1, |
100 | .type = PORT_SCIF, |
101 | }; |
102 | |
103 | static struct resource scif0_resources[] = { |
104 | DEFINE_RES_MEM(0xa4400000, 0x100), |
105 | DEFINE_RES_IRQ(evt2irq(0x880)), |
106 | }; |
107 | |
108 | static struct platform_device scif0_device = { |
109 | .name = "sh-sci" , |
110 | .id = 0, |
111 | .resource = scif0_resources, |
112 | .num_resources = ARRAY_SIZE(scif0_resources), |
113 | .dev = { |
114 | .platform_data = &scif0_platform_data, |
115 | }, |
116 | }; |
117 | |
118 | static struct plat_sci_port scif1_platform_data = { |
119 | .scscr = SCSCR_REIE | SCSCR_CKE1, |
120 | .type = PORT_SCIF, |
121 | }; |
122 | |
123 | static struct resource scif1_resources[] = { |
124 | DEFINE_RES_MEM(0xa4410000, 0x100), |
125 | DEFINE_RES_IRQ(evt2irq(0x900)), |
126 | }; |
127 | |
128 | static struct platform_device scif1_device = { |
129 | .name = "sh-sci" , |
130 | .id = 1, |
131 | .resource = scif1_resources, |
132 | .num_resources = ARRAY_SIZE(scif1_resources), |
133 | .dev = { |
134 | .platform_data = &scif1_platform_data, |
135 | }, |
136 | }; |
137 | |
138 | static struct sh_timer_config tmu0_platform_data = { |
139 | .channels_mask = 7, |
140 | }; |
141 | |
142 | static struct resource tmu0_resources[] = { |
143 | DEFINE_RES_MEM(0xa412fe90, 0x28), |
144 | DEFINE_RES_IRQ(evt2irq(0x400)), |
145 | DEFINE_RES_IRQ(evt2irq(0x420)), |
146 | DEFINE_RES_IRQ(evt2irq(0x440)), |
147 | }; |
148 | |
149 | static struct platform_device tmu0_device = { |
150 | .name = "sh-tmu-sh3" , |
151 | .id = 0, |
152 | .dev = { |
153 | .platform_data = &tmu0_platform_data, |
154 | }, |
155 | .resource = tmu0_resources, |
156 | .num_resources = ARRAY_SIZE(tmu0_resources), |
157 | }; |
158 | |
159 | static struct platform_device *sh7710_devices[] __initdata = { |
160 | &scif0_device, |
161 | &scif1_device, |
162 | &tmu0_device, |
163 | &rtc_device, |
164 | }; |
165 | |
166 | static int __init sh7710_devices_setup(void) |
167 | { |
168 | return platform_add_devices(sh7710_devices, |
169 | ARRAY_SIZE(sh7710_devices)); |
170 | } |
171 | arch_initcall(sh7710_devices_setup); |
172 | |
173 | static struct platform_device *sh7710_early_devices[] __initdata = { |
174 | &scif0_device, |
175 | &scif1_device, |
176 | &tmu0_device, |
177 | }; |
178 | |
179 | void __init plat_early_device_setup(void) |
180 | { |
181 | sh_early_platform_add_devices(sh7710_early_devices, |
182 | ARRAY_SIZE(sh7710_early_devices)); |
183 | } |
184 | |
185 | void __init plat_irq_setup(void) |
186 | { |
187 | register_intc_controller(desc: &intc_desc); |
188 | plat_irq_setup_sh3(); |
189 | } |
190 | |