1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * arch/sh/kernel/cpu/sh4a/clock-sh7724.c |
4 | * |
5 | * SH7724 clock framework support |
6 | * |
7 | * Copyright (C) 2009 Magnus Damm |
8 | */ |
9 | #include <linux/init.h> |
10 | #include <linux/kernel.h> |
11 | #include <linux/io.h> |
12 | #include <linux/clk.h> |
13 | #include <linux/clkdev.h> |
14 | #include <linux/sh_clk.h> |
15 | #include <asm/clock.h> |
16 | #include <cpu/sh7724.h> |
17 | |
18 | /* SH7724 registers */ |
19 | #define FRQCRA 0xa4150000 |
20 | #define FRQCRB 0xa4150004 |
21 | #define VCLKCR 0xa4150048 |
22 | #define FCLKACR 0xa4150008 |
23 | #define FCLKBCR 0xa415000c |
24 | #define IRDACLKCR 0xa4150018 |
25 | #define PLLCR 0xa4150024 |
26 | #define MSTPCR0 0xa4150030 |
27 | #define MSTPCR1 0xa4150034 |
28 | #define MSTPCR2 0xa4150038 |
29 | #define SPUCLKCR 0xa415003c |
30 | #define FLLFRQ 0xa4150050 |
31 | #define LSTATS 0xa4150060 |
32 | |
33 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ |
34 | static struct clk r_clk = { |
35 | .rate = 32768, |
36 | }; |
37 | |
38 | /* |
39 | * Default rate for the root input clock, reset this with clk_set_rate() |
40 | * from the platform code. |
41 | */ |
42 | static struct clk extal_clk = { |
43 | .rate = 33333333, |
44 | }; |
45 | |
46 | /* The fll multiplies the 32khz r_clk, may be used instead of extal */ |
47 | static unsigned long fll_recalc(struct clk *clk) |
48 | { |
49 | unsigned long mult = 0; |
50 | unsigned long div = 1; |
51 | |
52 | if (__raw_readl(PLLCR) & 0x1000) |
53 | mult = __raw_readl(FLLFRQ) & 0x3ff; |
54 | |
55 | if (__raw_readl(FLLFRQ) & 0x4000) |
56 | div = 2; |
57 | |
58 | return (clk->parent->rate * mult) / div; |
59 | } |
60 | |
61 | static struct sh_clk_ops fll_clk_ops = { |
62 | .recalc = fll_recalc, |
63 | }; |
64 | |
65 | static struct clk fll_clk = { |
66 | .ops = &fll_clk_ops, |
67 | .parent = &r_clk, |
68 | .flags = CLK_ENABLE_ON_INIT, |
69 | }; |
70 | |
71 | static unsigned long pll_recalc(struct clk *clk) |
72 | { |
73 | unsigned long mult = 1; |
74 | |
75 | if (__raw_readl(PLLCR) & 0x4000) |
76 | mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2; |
77 | |
78 | return clk->parent->rate * mult; |
79 | } |
80 | |
81 | static struct sh_clk_ops pll_clk_ops = { |
82 | .recalc = pll_recalc, |
83 | }; |
84 | |
85 | static struct clk pll_clk = { |
86 | .ops = &pll_clk_ops, |
87 | .flags = CLK_ENABLE_ON_INIT, |
88 | }; |
89 | |
90 | /* A fixed divide-by-3 block use by the div6 clocks */ |
91 | static unsigned long div3_recalc(struct clk *clk) |
92 | { |
93 | return clk->parent->rate / 3; |
94 | } |
95 | |
96 | static struct sh_clk_ops div3_clk_ops = { |
97 | .recalc = div3_recalc, |
98 | }; |
99 | |
100 | static struct clk div3_clk = { |
101 | .ops = &div3_clk_ops, |
102 | .parent = &pll_clk, |
103 | }; |
104 | |
105 | /* External input clock (pin name: FSIMCKA/FSIMCKB/DV_CLKI ) */ |
106 | struct clk sh7724_fsimcka_clk = { |
107 | }; |
108 | |
109 | struct clk sh7724_fsimckb_clk = { |
110 | }; |
111 | |
112 | struct clk sh7724_dv_clki = { |
113 | }; |
114 | |
115 | static struct clk *main_clks[] = { |
116 | &r_clk, |
117 | &extal_clk, |
118 | &fll_clk, |
119 | &pll_clk, |
120 | &div3_clk, |
121 | &sh7724_fsimcka_clk, |
122 | &sh7724_fsimckb_clk, |
123 | &sh7724_dv_clki, |
124 | }; |
125 | |
126 | static void div4_kick(struct clk *clk) |
127 | { |
128 | unsigned long value; |
129 | |
130 | /* set KICK bit in FRQCRA to update hardware setting */ |
131 | value = __raw_readl(FRQCRA); |
132 | value |= (1 << 31); |
133 | __raw_writel(val: value, FRQCRA); |
134 | } |
135 | |
136 | static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 }; |
137 | |
138 | static struct clk_div_mult_table div4_div_mult_table = { |
139 | .divisors = divisors, |
140 | .nr_divisors = ARRAY_SIZE(divisors), |
141 | }; |
142 | |
143 | static struct clk_div4_table div4_table = { |
144 | .div_mult_table = &div4_div_mult_table, |
145 | .kick = div4_kick, |
146 | }; |
147 | |
148 | enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; |
149 | |
150 | #define DIV4(_reg, _bit, _mask, _flags) \ |
151 | SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) |
152 | |
153 | struct clk div4_clks[DIV4_NR] = { |
154 | [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), |
155 | [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), |
156 | [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), |
157 | [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0), |
158 | [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), |
159 | }; |
160 | |
161 | enum { DIV6_V, DIV6_I, DIV6_S, DIV6_FA, DIV6_FB, DIV6_NR }; |
162 | |
163 | /* Indices are important - they are the actual src selecting values */ |
164 | static struct clk *common_parent[] = { |
165 | [0] = &div3_clk, |
166 | [1] = NULL, |
167 | }; |
168 | |
169 | static struct clk *vclkcr_parent[8] = { |
170 | [0] = &div3_clk, |
171 | [2] = &sh7724_dv_clki, |
172 | [4] = &extal_clk, |
173 | }; |
174 | |
175 | static struct clk *fclkacr_parent[] = { |
176 | [0] = &div3_clk, |
177 | [1] = NULL, |
178 | [2] = &sh7724_fsimcka_clk, |
179 | [3] = NULL, |
180 | }; |
181 | |
182 | static struct clk *fclkbcr_parent[] = { |
183 | [0] = &div3_clk, |
184 | [1] = NULL, |
185 | [2] = &sh7724_fsimckb_clk, |
186 | [3] = NULL, |
187 | }; |
188 | |
189 | static struct clk div6_clks[DIV6_NR] = { |
190 | [DIV6_V] = SH_CLK_DIV6_EXT(VCLKCR, 0, |
191 | vclkcr_parent, ARRAY_SIZE(vclkcr_parent), 12, 3), |
192 | [DIV6_I] = SH_CLK_DIV6_EXT(IRDACLKCR, 0, |
193 | common_parent, ARRAY_SIZE(common_parent), 6, 1), |
194 | [DIV6_S] = SH_CLK_DIV6_EXT(SPUCLKCR, CLK_ENABLE_ON_INIT, |
195 | common_parent, ARRAY_SIZE(common_parent), 6, 1), |
196 | [DIV6_FA] = SH_CLK_DIV6_EXT(FCLKACR, 0, |
197 | fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2), |
198 | [DIV6_FB] = SH_CLK_DIV6_EXT(FCLKBCR, 0, |
199 | fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2), |
200 | }; |
201 | |
202 | static struct clk mstp_clks[HWBLK_NR] = { |
203 | [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), |
204 | [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), |
205 | [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), |
206 | [HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 28, CLK_ENABLE_ON_INIT), |
207 | [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT), |
208 | [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT), |
209 | [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT), |
210 | [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, CLK_ENABLE_ON_INIT), |
211 | [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0), |
212 | [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT), |
213 | [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0), |
214 | [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0), |
215 | [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), |
216 | [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0), |
217 | [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0), |
218 | [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0), |
219 | [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), |
220 | [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), |
221 | [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), |
222 | [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), |
223 | [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0), |
224 | [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0), |
225 | [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0), |
226 | [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0), |
227 | [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0), |
228 | |
229 | [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 12, 0), |
230 | [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 11, 0), |
231 | [HWBLK_IIC0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), |
232 | [HWBLK_IIC1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0), |
233 | |
234 | [HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 29, 0), |
235 | [HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 28, 0), |
236 | [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 26, 0), |
237 | [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0), |
238 | [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0), |
239 | [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0), |
240 | [HWBLK_USB1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, 0), |
241 | [HWBLK_USB0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 20, 0), |
242 | [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 19, 0), |
243 | [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0), |
244 | [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0), |
245 | [HWBLK_VEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 15, 0), |
246 | [HWBLK_CEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 13, 0), |
247 | [HWBLK_BEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 12, 0), |
248 | [HWBLK_2DDMAC] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 10, 0), |
249 | [HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0), |
250 | [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), |
251 | [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), |
252 | [HWBLK_BEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), |
253 | [HWBLK_CEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), |
254 | [HWBLK_VEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), |
255 | [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), |
256 | [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0), |
257 | }; |
258 | |
259 | static struct clk_lookup lookups[] = { |
260 | /* main clocks */ |
261 | CLKDEV_CON_ID("rclk" , &r_clk), |
262 | CLKDEV_CON_ID("extal" , &extal_clk), |
263 | CLKDEV_CON_ID("fll_clk" , &fll_clk), |
264 | CLKDEV_CON_ID("pll_clk" , &pll_clk), |
265 | CLKDEV_CON_ID("div3_clk" , &div3_clk), |
266 | |
267 | /* DIV4 clocks */ |
268 | CLKDEV_CON_ID("cpu_clk" , &div4_clks[DIV4_I]), |
269 | CLKDEV_CON_ID("shyway_clk" , &div4_clks[DIV4_SH]), |
270 | CLKDEV_CON_ID("bus_clk" , &div4_clks[DIV4_B]), |
271 | CLKDEV_CON_ID("peripheral_clk" , &div4_clks[DIV4_P]), |
272 | CLKDEV_CON_ID("vpu_clk" , &div4_clks[DIV4_M1]), |
273 | |
274 | /* DIV6 clocks */ |
275 | CLKDEV_CON_ID("video_clk" , &div6_clks[DIV6_V]), |
276 | CLKDEV_CON_ID("fsia_clk" , &div6_clks[DIV6_FA]), |
277 | CLKDEV_CON_ID("fsib_clk" , &div6_clks[DIV6_FB]), |
278 | CLKDEV_CON_ID("irda_clk" , &div6_clks[DIV6_I]), |
279 | CLKDEV_CON_ID("spu_clk" , &div6_clks[DIV6_S]), |
280 | |
281 | /* MSTP clocks */ |
282 | CLKDEV_CON_ID("tlb0" , &mstp_clks[HWBLK_TLB]), |
283 | CLKDEV_CON_ID("ic0" , &mstp_clks[HWBLK_IC]), |
284 | CLKDEV_CON_ID("oc0" , &mstp_clks[HWBLK_OC]), |
285 | CLKDEV_CON_ID("rs0" , &mstp_clks[HWBLK_RSMEM]), |
286 | CLKDEV_CON_ID("ilmem0" , &mstp_clks[HWBLK_ILMEM]), |
287 | CLKDEV_CON_ID("l2c0" , &mstp_clks[HWBLK_L2C]), |
288 | CLKDEV_CON_ID("fpu0" , &mstp_clks[HWBLK_FPU]), |
289 | CLKDEV_CON_ID("intc0" , &mstp_clks[HWBLK_INTC]), |
290 | CLKDEV_DEV_ID("sh-dma-engine.0" , &mstp_clks[HWBLK_DMAC0]), |
291 | CLKDEV_CON_ID("sh0" , &mstp_clks[HWBLK_SHYWAY]), |
292 | CLKDEV_CON_ID("hudi0" , &mstp_clks[HWBLK_HUDI]), |
293 | CLKDEV_CON_ID("ubc0" , &mstp_clks[HWBLK_UBC]), |
294 | |
295 | CLKDEV_ICK_ID("fck" , "sh-tmu.0" , &mstp_clks[HWBLK_TMU0]), |
296 | CLKDEV_ICK_ID("fck" , "sh-tmu.1" , &mstp_clks[HWBLK_TMU1]), |
297 | |
298 | CLKDEV_ICK_ID("fck" , "sh-cmt-32.0" , &mstp_clks[HWBLK_CMT]), |
299 | CLKDEV_DEV_ID("sh-wdt.0" , &mstp_clks[HWBLK_RWDT]), |
300 | CLKDEV_DEV_ID("sh-dma-engine.1" , &mstp_clks[HWBLK_DMAC1]), |
301 | |
302 | CLKDEV_DEV_ID("sh-sci.0" , &mstp_clks[HWBLK_SCIF0]), |
303 | CLKDEV_DEV_ID("sh-sci.1" , &mstp_clks[HWBLK_SCIF1]), |
304 | CLKDEV_DEV_ID("sh-sci.2" , &mstp_clks[HWBLK_SCIF2]), |
305 | CLKDEV_DEV_ID("sh-sci.3" , &mstp_clks[HWBLK_SCIF3]), |
306 | CLKDEV_DEV_ID("sh-sci.4" , &mstp_clks[HWBLK_SCIF4]), |
307 | CLKDEV_DEV_ID("sh-sci.5" , &mstp_clks[HWBLK_SCIF5]), |
308 | |
309 | CLKDEV_DEV_ID("spi_sh_msiof.0" , &mstp_clks[HWBLK_MSIOF0]), |
310 | CLKDEV_DEV_ID("spi_sh_msiof.1" , &mstp_clks[HWBLK_MSIOF1]), |
311 | CLKDEV_DEV_ID("sh_keysc.0" , &mstp_clks[HWBLK_KEYSC]), |
312 | CLKDEV_CON_ID("rtc0" , &mstp_clks[HWBLK_RTC]), |
313 | CLKDEV_DEV_ID("i2c-sh_mobile.0" , &mstp_clks[HWBLK_IIC0]), |
314 | CLKDEV_DEV_ID("i2c-sh_mobile.1" , &mstp_clks[HWBLK_IIC1]), |
315 | CLKDEV_DEV_ID("sh_mmcif.0" , &mstp_clks[HWBLK_MMC]), |
316 | CLKDEV_DEV_ID("sh7724-ether.0" , &mstp_clks[HWBLK_ETHER]), |
317 | CLKDEV_CON_ID("atapi0" , &mstp_clks[HWBLK_ATAPI]), |
318 | CLKDEV_CON_ID("tpu0" , &mstp_clks[HWBLK_TPU]), |
319 | CLKDEV_CON_ID("irda0" , &mstp_clks[HWBLK_IRDA]), |
320 | CLKDEV_CON_ID("tsif0" , &mstp_clks[HWBLK_TSIF]), |
321 | CLKDEV_DEV_ID("renesas_usbhs.1" , &mstp_clks[HWBLK_USB1]), |
322 | CLKDEV_DEV_ID("renesas_usbhs.0" , &mstp_clks[HWBLK_USB0]), |
323 | CLKDEV_CON_ID("usb1" , &mstp_clks[HWBLK_USB1]), |
324 | CLKDEV_CON_ID("usb0" , &mstp_clks[HWBLK_USB0]), |
325 | CLKDEV_CON_ID("2dg0" , &mstp_clks[HWBLK_2DG]), |
326 | CLKDEV_DEV_ID("sh_mobile_sdhi.0" , &mstp_clks[HWBLK_SDHI0]), |
327 | CLKDEV_DEV_ID("sh_mobile_sdhi.1" , &mstp_clks[HWBLK_SDHI1]), |
328 | CLKDEV_CON_ID("veu1" , &mstp_clks[HWBLK_VEU1]), |
329 | CLKDEV_DEV_ID("renesas-ceu.1" , &mstp_clks[HWBLK_CEU1]), |
330 | CLKDEV_CON_ID("beu1" , &mstp_clks[HWBLK_BEU1]), |
331 | CLKDEV_CON_ID("2ddmac0" , &mstp_clks[HWBLK_2DDMAC]), |
332 | CLKDEV_DEV_ID("sh_fsi.0" , &mstp_clks[HWBLK_SPU]), |
333 | CLKDEV_CON_ID("jpu0" , &mstp_clks[HWBLK_JPU]), |
334 | CLKDEV_DEV_ID("sh-vou" , &mstp_clks[HWBLK_VOU]), |
335 | CLKDEV_CON_ID("beu0" , &mstp_clks[HWBLK_BEU0]), |
336 | CLKDEV_DEV_ID("renesas-ceu.0" , &mstp_clks[HWBLK_CEU0]), |
337 | CLKDEV_CON_ID("veu0" , &mstp_clks[HWBLK_VEU0]), |
338 | CLKDEV_CON_ID("vpu0" , &mstp_clks[HWBLK_VPU]), |
339 | CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0" , &mstp_clks[HWBLK_LCDC]), |
340 | }; |
341 | |
342 | int __init arch_clk_init(void) |
343 | { |
344 | int k, ret = 0; |
345 | |
346 | /* autodetect extal or fll configuration */ |
347 | if (__raw_readl(PLLCR) & 0x1000) |
348 | pll_clk.parent = &fll_clk; |
349 | else |
350 | pll_clk.parent = &extal_clk; |
351 | |
352 | for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) |
353 | ret = clk_register(main_clks[k]); |
354 | |
355 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
356 | |
357 | if (!ret) |
358 | ret = sh_clk_div4_register(clks: div4_clks, nr: DIV4_NR, table: &div4_table); |
359 | |
360 | if (!ret) |
361 | ret = sh_clk_div6_reparent_register(clks: div6_clks, nr: DIV6_NR); |
362 | |
363 | if (!ret) |
364 | ret = sh_clk_mstp_register(mstp_clks, HWBLK_NR); |
365 | |
366 | return ret; |
367 | } |
368 | |