1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (C) 1991, 1992 Linus Torvalds |
4 | * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs |
5 | * Copyright (C) 2011 Don Zickus Red Hat, Inc. |
6 | * |
7 | * Pentium III FXSR, SSE support |
8 | * Gareth Hughes <gareth@valinux.com>, May 2000 |
9 | */ |
10 | |
11 | /* |
12 | * Handle hardware traps and faults. |
13 | */ |
14 | #include <linux/spinlock.h> |
15 | #include <linux/kprobes.h> |
16 | #include <linux/kdebug.h> |
17 | #include <linux/sched/debug.h> |
18 | #include <linux/nmi.h> |
19 | #include <linux/debugfs.h> |
20 | #include <linux/delay.h> |
21 | #include <linux/hardirq.h> |
22 | #include <linux/ratelimit.h> |
23 | #include <linux/slab.h> |
24 | #include <linux/export.h> |
25 | #include <linux/atomic.h> |
26 | #include <linux/sched/clock.h> |
27 | |
28 | #include <asm/cpu_entry_area.h> |
29 | #include <asm/traps.h> |
30 | #include <asm/mach_traps.h> |
31 | #include <asm/nmi.h> |
32 | #include <asm/x86_init.h> |
33 | #include <asm/reboot.h> |
34 | #include <asm/cache.h> |
35 | #include <asm/nospec-branch.h> |
36 | #include <asm/microcode.h> |
37 | #include <asm/sev.h> |
38 | |
39 | #define CREATE_TRACE_POINTS |
40 | #include <trace/events/nmi.h> |
41 | |
42 | struct nmi_desc { |
43 | raw_spinlock_t lock; |
44 | struct list_head head; |
45 | }; |
46 | |
47 | static struct nmi_desc nmi_desc[NMI_MAX] = |
48 | { |
49 | { |
50 | .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[0].lock), |
51 | .head = LIST_HEAD_INIT(nmi_desc[0].head), |
52 | }, |
53 | { |
54 | .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[1].lock), |
55 | .head = LIST_HEAD_INIT(nmi_desc[1].head), |
56 | }, |
57 | { |
58 | .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[2].lock), |
59 | .head = LIST_HEAD_INIT(nmi_desc[2].head), |
60 | }, |
61 | { |
62 | .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[3].lock), |
63 | .head = LIST_HEAD_INIT(nmi_desc[3].head), |
64 | }, |
65 | |
66 | }; |
67 | |
68 | struct nmi_stats { |
69 | unsigned int normal; |
70 | unsigned int unknown; |
71 | unsigned int external; |
72 | unsigned int swallow; |
73 | unsigned long recv_jiffies; |
74 | unsigned long idt_seq; |
75 | unsigned long idt_nmi_seq; |
76 | unsigned long idt_ignored; |
77 | atomic_long_t idt_calls; |
78 | unsigned long idt_seq_snap; |
79 | unsigned long idt_nmi_seq_snap; |
80 | unsigned long idt_ignored_snap; |
81 | long idt_calls_snap; |
82 | }; |
83 | |
84 | static DEFINE_PER_CPU(struct nmi_stats, nmi_stats); |
85 | |
86 | static int ignore_nmis __read_mostly; |
87 | |
88 | int unknown_nmi_panic; |
89 | /* |
90 | * Prevent NMI reason port (0x61) being accessed simultaneously, can |
91 | * only be used in NMI handler. |
92 | */ |
93 | static DEFINE_RAW_SPINLOCK(nmi_reason_lock); |
94 | |
95 | static int __init setup_unknown_nmi_panic(char *str) |
96 | { |
97 | unknown_nmi_panic = 1; |
98 | return 1; |
99 | } |
100 | __setup("unknown_nmi_panic" , setup_unknown_nmi_panic); |
101 | |
102 | #define nmi_to_desc(type) (&nmi_desc[type]) |
103 | |
104 | static u64 nmi_longest_ns = 1 * NSEC_PER_MSEC; |
105 | |
106 | static int __init nmi_warning_debugfs(void) |
107 | { |
108 | debugfs_create_u64(name: "nmi_longest_ns" , mode: 0644, |
109 | parent: arch_debugfs_dir, value: &nmi_longest_ns); |
110 | return 0; |
111 | } |
112 | fs_initcall(nmi_warning_debugfs); |
113 | |
114 | static void nmi_check_duration(struct nmiaction *action, u64 duration) |
115 | { |
116 | int remainder_ns, decimal_msecs; |
117 | |
118 | if (duration < nmi_longest_ns || duration < action->max_duration) |
119 | return; |
120 | |
121 | action->max_duration = duration; |
122 | |
123 | remainder_ns = do_div(duration, (1000 * 1000)); |
124 | decimal_msecs = remainder_ns / 1000; |
125 | |
126 | printk_ratelimited(KERN_INFO |
127 | "INFO: NMI handler (%ps) took too long to run: %lld.%03d msecs\n" , |
128 | action->handler, duration, decimal_msecs); |
129 | } |
130 | |
131 | static int nmi_handle(unsigned int type, struct pt_regs *regs) |
132 | { |
133 | struct nmi_desc *desc = nmi_to_desc(type); |
134 | struct nmiaction *a; |
135 | int handled=0; |
136 | |
137 | rcu_read_lock(); |
138 | |
139 | /* |
140 | * NMIs are edge-triggered, which means if you have enough |
141 | * of them concurrently, you can lose some because only one |
142 | * can be latched at any given time. Walk the whole list |
143 | * to handle those situations. |
144 | */ |
145 | list_for_each_entry_rcu(a, &desc->head, list) { |
146 | int thishandled; |
147 | u64 delta; |
148 | |
149 | delta = sched_clock(); |
150 | thishandled = a->handler(type, regs); |
151 | handled += thishandled; |
152 | delta = sched_clock() - delta; |
153 | trace_nmi_handler(handler: a->handler, delta_ns: (int)delta, handled: thishandled); |
154 | |
155 | nmi_check_duration(action: a, duration: delta); |
156 | } |
157 | |
158 | rcu_read_unlock(); |
159 | |
160 | /* return total number of NMI events handled */ |
161 | return handled; |
162 | } |
163 | NOKPROBE_SYMBOL(nmi_handle); |
164 | |
165 | int __register_nmi_handler(unsigned int type, struct nmiaction *action) |
166 | { |
167 | struct nmi_desc *desc = nmi_to_desc(type); |
168 | unsigned long flags; |
169 | |
170 | if (WARN_ON_ONCE(!action->handler || !list_empty(&action->list))) |
171 | return -EINVAL; |
172 | |
173 | raw_spin_lock_irqsave(&desc->lock, flags); |
174 | |
175 | /* |
176 | * Indicate if there are multiple registrations on the |
177 | * internal NMI handler call chains (SERR and IO_CHECK). |
178 | */ |
179 | WARN_ON_ONCE(type == NMI_SERR && !list_empty(&desc->head)); |
180 | WARN_ON_ONCE(type == NMI_IO_CHECK && !list_empty(&desc->head)); |
181 | |
182 | /* |
183 | * some handlers need to be executed first otherwise a fake |
184 | * event confuses some handlers (kdump uses this flag) |
185 | */ |
186 | if (action->flags & NMI_FLAG_FIRST) |
187 | list_add_rcu(new: &action->list, head: &desc->head); |
188 | else |
189 | list_add_tail_rcu(new: &action->list, head: &desc->head); |
190 | |
191 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
192 | return 0; |
193 | } |
194 | EXPORT_SYMBOL(__register_nmi_handler); |
195 | |
196 | void unregister_nmi_handler(unsigned int type, const char *name) |
197 | { |
198 | struct nmi_desc *desc = nmi_to_desc(type); |
199 | struct nmiaction *n, *found = NULL; |
200 | unsigned long flags; |
201 | |
202 | raw_spin_lock_irqsave(&desc->lock, flags); |
203 | |
204 | list_for_each_entry_rcu(n, &desc->head, list) { |
205 | /* |
206 | * the name passed in to describe the nmi handler |
207 | * is used as the lookup key |
208 | */ |
209 | if (!strcmp(n->name, name)) { |
210 | WARN(in_nmi(), |
211 | "Trying to free NMI (%s) from NMI context!\n" , n->name); |
212 | list_del_rcu(entry: &n->list); |
213 | found = n; |
214 | break; |
215 | } |
216 | } |
217 | |
218 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
219 | if (found) { |
220 | synchronize_rcu(); |
221 | INIT_LIST_HEAD(list: &found->list); |
222 | } |
223 | } |
224 | EXPORT_SYMBOL_GPL(unregister_nmi_handler); |
225 | |
226 | static void |
227 | pci_serr_error(unsigned char reason, struct pt_regs *regs) |
228 | { |
229 | /* check to see if anyone registered against these types of errors */ |
230 | if (nmi_handle(type: NMI_SERR, regs)) |
231 | return; |
232 | |
233 | pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n" , |
234 | reason, smp_processor_id()); |
235 | |
236 | if (panic_on_unrecovered_nmi) |
237 | nmi_panic(regs, msg: "NMI: Not continuing" ); |
238 | |
239 | pr_emerg("Dazed and confused, but trying to continue\n" ); |
240 | |
241 | /* Clear and disable the PCI SERR error line. */ |
242 | reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_SERR; |
243 | outb(value: reason, NMI_REASON_PORT); |
244 | } |
245 | NOKPROBE_SYMBOL(pci_serr_error); |
246 | |
247 | static void |
248 | io_check_error(unsigned char reason, struct pt_regs *regs) |
249 | { |
250 | unsigned long i; |
251 | |
252 | /* check to see if anyone registered against these types of errors */ |
253 | if (nmi_handle(type: NMI_IO_CHECK, regs)) |
254 | return; |
255 | |
256 | pr_emerg( |
257 | "NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n" , |
258 | reason, smp_processor_id()); |
259 | show_regs(regs); |
260 | |
261 | if (panic_on_io_nmi) { |
262 | nmi_panic(regs, msg: "NMI IOCK error: Not continuing" ); |
263 | |
264 | /* |
265 | * If we end up here, it means we have received an NMI while |
266 | * processing panic(). Simply return without delaying and |
267 | * re-enabling NMIs. |
268 | */ |
269 | return; |
270 | } |
271 | |
272 | /* Re-enable the IOCK line, wait for a few seconds */ |
273 | reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_IOCHK; |
274 | outb(value: reason, NMI_REASON_PORT); |
275 | |
276 | i = 20000; |
277 | while (--i) { |
278 | touch_nmi_watchdog(); |
279 | udelay(100); |
280 | } |
281 | |
282 | reason &= ~NMI_REASON_CLEAR_IOCHK; |
283 | outb(value: reason, NMI_REASON_PORT); |
284 | } |
285 | NOKPROBE_SYMBOL(io_check_error); |
286 | |
287 | static void |
288 | unknown_nmi_error(unsigned char reason, struct pt_regs *regs) |
289 | { |
290 | int handled; |
291 | |
292 | /* |
293 | * Use 'false' as back-to-back NMIs are dealt with one level up. |
294 | * Of course this makes having multiple 'unknown' handlers useless |
295 | * as only the first one is ever run (unless it can actually determine |
296 | * if it caused the NMI) |
297 | */ |
298 | handled = nmi_handle(type: NMI_UNKNOWN, regs); |
299 | if (handled) { |
300 | __this_cpu_add(nmi_stats.unknown, handled); |
301 | return; |
302 | } |
303 | |
304 | __this_cpu_add(nmi_stats.unknown, 1); |
305 | |
306 | pr_emerg("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n" , |
307 | reason, smp_processor_id()); |
308 | |
309 | if (unknown_nmi_panic || panic_on_unrecovered_nmi) |
310 | nmi_panic(regs, msg: "NMI: Not continuing" ); |
311 | |
312 | pr_emerg("Dazed and confused, but trying to continue\n" ); |
313 | } |
314 | NOKPROBE_SYMBOL(unknown_nmi_error); |
315 | |
316 | static DEFINE_PER_CPU(bool, swallow_nmi); |
317 | static DEFINE_PER_CPU(unsigned long, last_nmi_rip); |
318 | |
319 | static noinstr void default_do_nmi(struct pt_regs *regs) |
320 | { |
321 | unsigned char reason = 0; |
322 | int handled; |
323 | bool b2b = false; |
324 | |
325 | /* |
326 | * CPU-specific NMI must be processed before non-CPU-specific |
327 | * NMI, otherwise we may lose it, because the CPU-specific |
328 | * NMI can not be detected/processed on other CPUs. |
329 | */ |
330 | |
331 | /* |
332 | * Back-to-back NMIs are interesting because they can either |
333 | * be two NMI or more than two NMIs (any thing over two is dropped |
334 | * due to NMI being edge-triggered). If this is the second half |
335 | * of the back-to-back NMI, assume we dropped things and process |
336 | * more handlers. Otherwise reset the 'swallow' NMI behaviour |
337 | */ |
338 | if (regs->ip == __this_cpu_read(last_nmi_rip)) |
339 | b2b = true; |
340 | else |
341 | __this_cpu_write(swallow_nmi, false); |
342 | |
343 | __this_cpu_write(last_nmi_rip, regs->ip); |
344 | |
345 | instrumentation_begin(); |
346 | |
347 | if (microcode_nmi_handler_enabled() && microcode_nmi_handler()) |
348 | goto out; |
349 | |
350 | handled = nmi_handle(type: NMI_LOCAL, regs); |
351 | __this_cpu_add(nmi_stats.normal, handled); |
352 | if (handled) { |
353 | /* |
354 | * There are cases when a NMI handler handles multiple |
355 | * events in the current NMI. One of these events may |
356 | * be queued for in the next NMI. Because the event is |
357 | * already handled, the next NMI will result in an unknown |
358 | * NMI. Instead lets flag this for a potential NMI to |
359 | * swallow. |
360 | */ |
361 | if (handled > 1) |
362 | __this_cpu_write(swallow_nmi, true); |
363 | goto out; |
364 | } |
365 | |
366 | /* |
367 | * Non-CPU-specific NMI: NMI sources can be processed on any CPU. |
368 | * |
369 | * Another CPU may be processing panic routines while holding |
370 | * nmi_reason_lock. Check if the CPU issued the IPI for crash dumping, |
371 | * and if so, call its callback directly. If there is no CPU preparing |
372 | * crash dump, we simply loop here. |
373 | */ |
374 | while (!raw_spin_trylock(&nmi_reason_lock)) { |
375 | run_crash_ipi_callback(regs); |
376 | cpu_relax(); |
377 | } |
378 | |
379 | reason = x86_platform.get_nmi_reason(); |
380 | |
381 | if (reason & NMI_REASON_MASK) { |
382 | if (reason & NMI_REASON_SERR) |
383 | pci_serr_error(reason, regs); |
384 | else if (reason & NMI_REASON_IOCHK) |
385 | io_check_error(reason, regs); |
386 | #ifdef CONFIG_X86_32 |
387 | /* |
388 | * Reassert NMI in case it became active |
389 | * meanwhile as it's edge-triggered: |
390 | */ |
391 | reassert_nmi(); |
392 | #endif |
393 | __this_cpu_add(nmi_stats.external, 1); |
394 | raw_spin_unlock(&nmi_reason_lock); |
395 | goto out; |
396 | } |
397 | raw_spin_unlock(&nmi_reason_lock); |
398 | |
399 | /* |
400 | * Only one NMI can be latched at a time. To handle |
401 | * this we may process multiple nmi handlers at once to |
402 | * cover the case where an NMI is dropped. The downside |
403 | * to this approach is we may process an NMI prematurely, |
404 | * while its real NMI is sitting latched. This will cause |
405 | * an unknown NMI on the next run of the NMI processing. |
406 | * |
407 | * We tried to flag that condition above, by setting the |
408 | * swallow_nmi flag when we process more than one event. |
409 | * This condition is also only present on the second half |
410 | * of a back-to-back NMI, so we flag that condition too. |
411 | * |
412 | * If both are true, we assume we already processed this |
413 | * NMI previously and we swallow it. Otherwise we reset |
414 | * the logic. |
415 | * |
416 | * There are scenarios where we may accidentally swallow |
417 | * a 'real' unknown NMI. For example, while processing |
418 | * a perf NMI another perf NMI comes in along with a |
419 | * 'real' unknown NMI. These two NMIs get combined into |
420 | * one (as described above). When the next NMI gets |
421 | * processed, it will be flagged by perf as handled, but |
422 | * no one will know that there was a 'real' unknown NMI sent |
423 | * also. As a result it gets swallowed. Or if the first |
424 | * perf NMI returns two events handled then the second |
425 | * NMI will get eaten by the logic below, again losing a |
426 | * 'real' unknown NMI. But this is the best we can do |
427 | * for now. |
428 | */ |
429 | if (b2b && __this_cpu_read(swallow_nmi)) |
430 | __this_cpu_add(nmi_stats.swallow, 1); |
431 | else |
432 | unknown_nmi_error(reason, regs); |
433 | |
434 | out: |
435 | instrumentation_end(); |
436 | } |
437 | |
438 | /* |
439 | * NMIs can page fault or hit breakpoints which will cause it to lose |
440 | * its NMI context with the CPU when the breakpoint or page fault does an IRET. |
441 | * |
442 | * As a result, NMIs can nest if NMIs get unmasked due an IRET during |
443 | * NMI processing. On x86_64, the asm glue protects us from nested NMIs |
444 | * if the outer NMI came from kernel mode, but we can still nest if the |
445 | * outer NMI came from user mode. |
446 | * |
447 | * To handle these nested NMIs, we have three states: |
448 | * |
449 | * 1) not running |
450 | * 2) executing |
451 | * 3) latched |
452 | * |
453 | * When no NMI is in progress, it is in the "not running" state. |
454 | * When an NMI comes in, it goes into the "executing" state. |
455 | * Normally, if another NMI is triggered, it does not interrupt |
456 | * the running NMI and the HW will simply latch it so that when |
457 | * the first NMI finishes, it will restart the second NMI. |
458 | * (Note, the latch is binary, thus multiple NMIs triggering, |
459 | * when one is running, are ignored. Only one NMI is restarted.) |
460 | * |
461 | * If an NMI executes an iret, another NMI can preempt it. We do not |
462 | * want to allow this new NMI to run, but we want to execute it when the |
463 | * first one finishes. We set the state to "latched", and the exit of |
464 | * the first NMI will perform a dec_return, if the result is zero |
465 | * (NOT_RUNNING), then it will simply exit the NMI handler. If not, the |
466 | * dec_return would have set the state to NMI_EXECUTING (what we want it |
467 | * to be when we are running). In this case, we simply jump back to |
468 | * rerun the NMI handler again, and restart the 'latched' NMI. |
469 | * |
470 | * No trap (breakpoint or page fault) should be hit before nmi_restart, |
471 | * thus there is no race between the first check of state for NOT_RUNNING |
472 | * and setting it to NMI_EXECUTING. The HW will prevent nested NMIs |
473 | * at this point. |
474 | * |
475 | * In case the NMI takes a page fault, we need to save off the CR2 |
476 | * because the NMI could have preempted another page fault and corrupt |
477 | * the CR2 that is about to be read. As nested NMIs must be restarted |
478 | * and they can not take breakpoints or page faults, the update of the |
479 | * CR2 must be done before converting the nmi state back to NOT_RUNNING. |
480 | * Otherwise, there would be a race of another nested NMI coming in |
481 | * after setting state to NOT_RUNNING but before updating the nmi_cr2. |
482 | */ |
483 | enum nmi_states { |
484 | NMI_NOT_RUNNING = 0, |
485 | NMI_EXECUTING, |
486 | NMI_LATCHED, |
487 | }; |
488 | static DEFINE_PER_CPU(enum nmi_states, nmi_state); |
489 | static DEFINE_PER_CPU(unsigned long, nmi_cr2); |
490 | static DEFINE_PER_CPU(unsigned long, nmi_dr7); |
491 | |
492 | DEFINE_IDTENTRY_RAW(exc_nmi) |
493 | { |
494 | irqentry_state_t irq_state; |
495 | struct nmi_stats *nsp = this_cpu_ptr(&nmi_stats); |
496 | |
497 | /* |
498 | * Re-enable NMIs right here when running as an SEV-ES guest. This might |
499 | * cause nested NMIs, but those can be handled safely. |
500 | */ |
501 | sev_es_nmi_complete(); |
502 | if (IS_ENABLED(CONFIG_NMI_CHECK_CPU)) |
503 | raw_atomic_long_inc(v: &nsp->idt_calls); |
504 | |
505 | if (IS_ENABLED(CONFIG_SMP) && arch_cpu_is_offline(smp_processor_id())) { |
506 | if (microcode_nmi_handler_enabled()) |
507 | microcode_offline_nmi_handler(); |
508 | return; |
509 | } |
510 | |
511 | if (this_cpu_read(nmi_state) != NMI_NOT_RUNNING) { |
512 | this_cpu_write(nmi_state, NMI_LATCHED); |
513 | return; |
514 | } |
515 | this_cpu_write(nmi_state, NMI_EXECUTING); |
516 | this_cpu_write(nmi_cr2, read_cr2()); |
517 | |
518 | nmi_restart: |
519 | if (IS_ENABLED(CONFIG_NMI_CHECK_CPU)) { |
520 | WRITE_ONCE(nsp->idt_seq, nsp->idt_seq + 1); |
521 | WARN_ON_ONCE(!(nsp->idt_seq & 0x1)); |
522 | WRITE_ONCE(nsp->recv_jiffies, jiffies); |
523 | } |
524 | |
525 | /* |
526 | * Needs to happen before DR7 is accessed, because the hypervisor can |
527 | * intercept DR7 reads/writes, turning those into #VC exceptions. |
528 | */ |
529 | sev_es_ist_enter(regs); |
530 | |
531 | this_cpu_write(nmi_dr7, local_db_save()); |
532 | |
533 | irq_state = irqentry_nmi_enter(regs); |
534 | |
535 | inc_irq_stat(__nmi_count); |
536 | |
537 | if (IS_ENABLED(CONFIG_NMI_CHECK_CPU) && ignore_nmis) { |
538 | WRITE_ONCE(nsp->idt_ignored, nsp->idt_ignored + 1); |
539 | } else if (!ignore_nmis) { |
540 | if (IS_ENABLED(CONFIG_NMI_CHECK_CPU)) { |
541 | WRITE_ONCE(nsp->idt_nmi_seq, nsp->idt_nmi_seq + 1); |
542 | WARN_ON_ONCE(!(nsp->idt_nmi_seq & 0x1)); |
543 | } |
544 | default_do_nmi(regs); |
545 | if (IS_ENABLED(CONFIG_NMI_CHECK_CPU)) { |
546 | WRITE_ONCE(nsp->idt_nmi_seq, nsp->idt_nmi_seq + 1); |
547 | WARN_ON_ONCE(nsp->idt_nmi_seq & 0x1); |
548 | } |
549 | } |
550 | |
551 | irqentry_nmi_exit(regs, irq_state); |
552 | |
553 | local_db_restore(this_cpu_read(nmi_dr7)); |
554 | |
555 | sev_es_ist_exit(); |
556 | |
557 | if (unlikely(this_cpu_read(nmi_cr2) != read_cr2())) |
558 | write_cr2(this_cpu_read(nmi_cr2)); |
559 | if (IS_ENABLED(CONFIG_NMI_CHECK_CPU)) { |
560 | WRITE_ONCE(nsp->idt_seq, nsp->idt_seq + 1); |
561 | WARN_ON_ONCE(nsp->idt_seq & 0x1); |
562 | WRITE_ONCE(nsp->recv_jiffies, jiffies); |
563 | } |
564 | if (this_cpu_dec_return(nmi_state)) |
565 | goto nmi_restart; |
566 | |
567 | if (user_mode(regs)) |
568 | mds_user_clear_cpu_buffers(); |
569 | } |
570 | |
571 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
572 | DEFINE_IDTENTRY_RAW(exc_nmi_kvm_vmx) |
573 | { |
574 | exc_nmi(regs); |
575 | } |
576 | #if IS_MODULE(CONFIG_KVM_INTEL) |
577 | EXPORT_SYMBOL_GPL(asm_exc_nmi_kvm_vmx); |
578 | #endif |
579 | #endif |
580 | |
581 | #ifdef CONFIG_NMI_CHECK_CPU |
582 | |
583 | static char *nmi_check_stall_msg[] = { |
584 | /* */ |
585 | /* +--------- nsp->idt_seq_snap & 0x1: CPU is in NMI handler. */ |
586 | /* | +------ cpu_is_offline(cpu) */ |
587 | /* | | +--- nsp->idt_calls_snap != atomic_long_read(&nsp->idt_calls): */ |
588 | /* | | | NMI handler has been invoked. */ |
589 | /* | | | */ |
590 | /* V V V */ |
591 | /* 0 0 0 */ "NMIs are not reaching exc_nmi() handler" , |
592 | /* 0 0 1 */ "exc_nmi() handler is ignoring NMIs" , |
593 | /* 0 1 0 */ "CPU is offline and NMIs are not reaching exc_nmi() handler" , |
594 | /* 0 1 1 */ "CPU is offline and exc_nmi() handler is legitimately ignoring NMIs" , |
595 | /* 1 0 0 */ "CPU is in exc_nmi() handler and no further NMIs are reaching handler" , |
596 | /* 1 0 1 */ "CPU is in exc_nmi() handler which is legitimately ignoring NMIs" , |
597 | /* 1 1 0 */ "CPU is offline in exc_nmi() handler and no more NMIs are reaching exc_nmi() handler" , |
598 | /* 1 1 1 */ "CPU is offline in exc_nmi() handler which is legitimately ignoring NMIs" , |
599 | }; |
600 | |
601 | void nmi_backtrace_stall_snap(const struct cpumask *btp) |
602 | { |
603 | int cpu; |
604 | struct nmi_stats *nsp; |
605 | |
606 | for_each_cpu(cpu, btp) { |
607 | nsp = per_cpu_ptr(&nmi_stats, cpu); |
608 | nsp->idt_seq_snap = READ_ONCE(nsp->idt_seq); |
609 | nsp->idt_nmi_seq_snap = READ_ONCE(nsp->idt_nmi_seq); |
610 | nsp->idt_ignored_snap = READ_ONCE(nsp->idt_ignored); |
611 | nsp->idt_calls_snap = atomic_long_read(v: &nsp->idt_calls); |
612 | } |
613 | } |
614 | |
615 | void nmi_backtrace_stall_check(const struct cpumask *btp) |
616 | { |
617 | int cpu; |
618 | int idx; |
619 | unsigned long nmi_seq; |
620 | unsigned long j = jiffies; |
621 | char *modp; |
622 | char *msgp; |
623 | char *msghp; |
624 | struct nmi_stats *nsp; |
625 | |
626 | for_each_cpu(cpu, btp) { |
627 | nsp = per_cpu_ptr(&nmi_stats, cpu); |
628 | modp = "" ; |
629 | msghp = "" ; |
630 | nmi_seq = READ_ONCE(nsp->idt_nmi_seq); |
631 | if (nsp->idt_nmi_seq_snap + 1 == nmi_seq && (nmi_seq & 0x1)) { |
632 | msgp = "CPU entered NMI handler function, but has not exited" ; |
633 | } else if ((nsp->idt_nmi_seq_snap & 0x1) != (nmi_seq & 0x1)) { |
634 | msgp = "CPU is handling NMIs" ; |
635 | } else { |
636 | idx = ((nsp->idt_seq_snap & 0x1) << 2) | |
637 | (cpu_is_offline(cpu) << 1) | |
638 | (nsp->idt_calls_snap != atomic_long_read(v: &nsp->idt_calls)); |
639 | msgp = nmi_check_stall_msg[idx]; |
640 | if (nsp->idt_ignored_snap != READ_ONCE(nsp->idt_ignored) && (idx & 0x1)) |
641 | modp = ", but OK because ignore_nmis was set" ; |
642 | if (nmi_seq & ~0x1) |
643 | msghp = " (CPU currently in NMI handler function)" ; |
644 | else if (nsp->idt_nmi_seq_snap + 1 == nmi_seq) |
645 | msghp = " (CPU exited one NMI handler function)" ; |
646 | } |
647 | pr_alert("%s: CPU %d: %s%s%s, last activity: %lu jiffies ago.\n" , |
648 | __func__, cpu, msgp, modp, msghp, j - READ_ONCE(nsp->recv_jiffies)); |
649 | } |
650 | } |
651 | |
652 | #endif |
653 | |
654 | void stop_nmi(void) |
655 | { |
656 | ignore_nmis++; |
657 | } |
658 | |
659 | void restart_nmi(void) |
660 | { |
661 | ignore_nmis--; |
662 | } |
663 | |
664 | /* reset the back-to-back NMI logic */ |
665 | void local_touch_nmi(void) |
666 | { |
667 | __this_cpu_write(last_nmi_rip, 0); |
668 | } |
669 | EXPORT_SYMBOL_GPL(local_touch_nmi); |
670 | |