| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /*---------------------------------------------------------------------------+ |
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| 3 | | control_w.h | |
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| 4 | | | |
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| 5 | | Copyright (C) 1992,1993 | |
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| 6 | | W. Metzenthen, 22 Parker St, Ormond, Vic 3163, | |
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| 7 | | Australia. E-mail billm@vaxc.cc.monash.edu.au | |
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| 8 | | | |
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| 9 | +---------------------------------------------------------------------------*/ |
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| 10 | |
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| 11 | #ifndef _CONTROLW_H_ |
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| 12 | #define _CONTROLW_H_ |
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| 13 | |
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| 14 | #ifdef __ASSEMBLY__ |
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| 15 | #define _Const_(x) $##x |
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| 16 | #else |
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| 17 | #define _Const_(x) x |
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| 18 | #endif |
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| 19 | |
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| 20 | #define CW_RC _Const_(0x0C00) /* rounding control */ |
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| 21 | #define CW_PC _Const_(0x0300) /* precision control */ |
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| 22 | |
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| 23 | #define CW_Precision Const_(0x0020) /* loss of precision mask */ |
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| 24 | #define CW_Underflow Const_(0x0010) /* underflow mask */ |
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| 25 | #define CW_Overflow Const_(0x0008) /* overflow mask */ |
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| 26 | #define CW_ZeroDiv Const_(0x0004) /* divide by zero mask */ |
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| 27 | #define CW_Denormal Const_(0x0002) /* denormalized operand mask */ |
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| 28 | #define CW_Invalid Const_(0x0001) /* invalid operation mask */ |
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| 29 | |
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| 30 | #define CW_Exceptions _Const_(0x003f) /* all masks */ |
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| 31 | |
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| 32 | #define RC_RND _Const_(0x0000) |
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| 33 | #define RC_DOWN _Const_(0x0400) |
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| 34 | #define RC_UP _Const_(0x0800) |
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| 35 | #define RC_CHOP _Const_(0x0C00) |
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| 36 | |
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| 37 | /* p 15-5: Precision control bits affect only the following: |
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| 38 | ADD, SUB(R), MUL, DIV(R), and SQRT */ |
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| 39 | #define PR_24_BITS _Const_(0x000) |
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| 40 | #define PR_53_BITS _Const_(0x200) |
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| 41 | #define PR_64_BITS _Const_(0x300) |
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| 42 | #define PR_RESERVED_BITS _Const_(0x100) |
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| 43 | /* FULL_PRECISION simulates all exceptions masked */ |
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| 44 | #define FULL_PRECISION (PR_64_BITS | RC_RND | 0x3f) |
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| 45 | |
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| 46 | #endif /* _CONTROLW_H_ */ |
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| 47 | |
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