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1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 * Copyright (C) 2011 Google, Inc.
4 *
5 * Author:
6 * Jay Cheng <jacheng@nvidia.com>
7 * James Wylder <james.wylder@motorola.com>
8 * Benoit Goby <benoit@android.com>
9 * Colin Cross <ccross@android.com>
10 * Hiroshi DOYU <hdoyu@nvidia.com>
11 *
12 * This software is licensed under the terms of the GNU General Public
13 * License version 2, as published by the Free Software Foundation, and
14 * may be copied, distributed, and modified under those terms.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 */
22
23#include <linux/err.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/io.h>
28#include <linux/of.h>
29
30#include <soc/tegra/ahb.h>
31
32#define DRV_NAME "tegra-ahb"
33
34#define AHB_ARBITRATION_DISABLE 0x04
35#define AHB_ARBITRATION_PRIORITY_CTRL 0x08
36#define AHB_PRIORITY_WEIGHT(x) (((x) & 0x7) << 29)
37#define PRIORITY_SELECT_USB BIT(6)
38#define PRIORITY_SELECT_USB2 BIT(18)
39#define PRIORITY_SELECT_USB3 BIT(17)
40
41#define AHB_GIZMO_AHB_MEM 0x10
42#define ENB_FAST_REARBITRATE BIT(2)
43#define DONT_SPLIT_AHB_WR BIT(7)
44
45#define AHB_GIZMO_APB_DMA 0x14
46#define AHB_GIZMO_IDE 0x1c
47#define AHB_GIZMO_USB 0x20
48#define AHB_GIZMO_AHB_XBAR_BRIDGE 0x24
49#define AHB_GIZMO_CPU_AHB_BRIDGE 0x28
50#define AHB_GIZMO_COP_AHB_BRIDGE 0x2c
51#define AHB_GIZMO_XBAR_APB_CTLR 0x30
52#define AHB_GIZMO_VCP_AHB_BRIDGE 0x34
53#define AHB_GIZMO_NAND 0x40
54#define AHB_GIZMO_SDMMC4 0x48
55#define AHB_GIZMO_XIO 0x4c
56#define AHB_GIZMO_BSEV 0x64
57#define AHB_GIZMO_BSEA 0x74
58#define AHB_GIZMO_NOR 0x78
59#define AHB_GIZMO_USB2 0x7c
60#define AHB_GIZMO_USB3 0x80
61#define IMMEDIATE BIT(18)
62
63#define AHB_GIZMO_SDMMC1 0x84
64#define AHB_GIZMO_SDMMC2 0x88
65#define AHB_GIZMO_SDMMC3 0x8c
66#define AHB_MEM_PREFETCH_CFG_X 0xdc
67#define AHB_ARBITRATION_XBAR_CTRL 0xe0
68#define AHB_MEM_PREFETCH_CFG3 0xe4
69#define AHB_MEM_PREFETCH_CFG4 0xe8
70#define AHB_MEM_PREFETCH_CFG1 0xf0
71#define AHB_MEM_PREFETCH_CFG2 0xf4
72#define PREFETCH_ENB BIT(31)
73#define MST_ID(x) (((x) & 0x1f) << 26)
74#define AHBDMA_MST_ID MST_ID(5)
75#define USB_MST_ID MST_ID(6)
76#define USB2_MST_ID MST_ID(18)
77#define USB3_MST_ID MST_ID(17)
78#define ADDR_BNDRY(x) (((x) & 0xf) << 21)
79#define INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
80
81#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xfc
82
83#define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17)
84
85/*
86 * INCORRECT_BASE_ADDR_LOW_BYTE: Legacy kernel DT files for Tegra SoCs
87 * prior to Tegra124 generally use a physical base address ending in
88 * 0x4 for the AHB IP block. According to the TRM, the low byte
89 * should be 0x0. During device probing, this macro is used to detect
90 * whether the passed-in physical address is incorrect, and if so, to
91 * correct it.
92 */
93#define INCORRECT_BASE_ADDR_LOW_BYTE 0x4
94
95static struct platform_driver tegra_ahb_driver;
96
97static const u32 tegra_ahb_gizmo[] = {
98 AHB_ARBITRATION_DISABLE,
99 AHB_ARBITRATION_PRIORITY_CTRL,
100 AHB_GIZMO_AHB_MEM,
101 AHB_GIZMO_APB_DMA,
102 AHB_GIZMO_IDE,
103 AHB_GIZMO_USB,
104 AHB_GIZMO_AHB_XBAR_BRIDGE,
105 AHB_GIZMO_CPU_AHB_BRIDGE,
106 AHB_GIZMO_COP_AHB_BRIDGE,
107 AHB_GIZMO_XBAR_APB_CTLR,
108 AHB_GIZMO_VCP_AHB_BRIDGE,
109 AHB_GIZMO_NAND,
110 AHB_GIZMO_SDMMC4,
111 AHB_GIZMO_XIO,
112 AHB_GIZMO_BSEV,
113 AHB_GIZMO_BSEA,
114 AHB_GIZMO_NOR,
115 AHB_GIZMO_USB2,
116 AHB_GIZMO_USB3,
117 AHB_GIZMO_SDMMC1,
118 AHB_GIZMO_SDMMC2,
119 AHB_GIZMO_SDMMC3,
120 AHB_MEM_PREFETCH_CFG_X,
121 AHB_ARBITRATION_XBAR_CTRL,
122 AHB_MEM_PREFETCH_CFG3,
123 AHB_MEM_PREFETCH_CFG4,
124 AHB_MEM_PREFETCH_CFG1,
125 AHB_MEM_PREFETCH_CFG2,
126 AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID,
127};
128
129struct tegra_ahb {
130 void __iomem *regs;
131 struct device *dev;
132 u32 ctx[0];
133};
134
135static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)
136{
137 return readl(ahb->regs + offset);
138}
139
140static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset)
141{
142 writel(value, ahb->regs + offset);
143}
144
145#ifdef CONFIG_TEGRA_IOMMU_SMMU
146static int tegra_ahb_match_by_smmu(struct device *dev, void *data)
147{
148 struct tegra_ahb *ahb = dev_get_drvdata(dev);
149 struct device_node *dn = data;
150
151 return (ahb->dev->of_node == dn) ? 1 : 0;
152}
153
154int tegra_ahb_enable_smmu(struct device_node *dn)
155{
156 struct device *dev;
157 u32 val;
158 struct tegra_ahb *ahb;
159
160 dev = driver_find_device(&tegra_ahb_driver.driver, NULL, dn,
161 tegra_ahb_match_by_smmu);
162 if (!dev)
163 return -EPROBE_DEFER;
164 ahb = dev_get_drvdata(dev);
165 val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL);
166 val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE;
167 gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL);
168 return 0;
169}
170EXPORT_SYMBOL(tegra_ahb_enable_smmu);
171#endif
172
173#ifdef CONFIG_PM
174static int tegra_ahb_suspend(struct device *dev)
175{
176 int i;
177 struct tegra_ahb *ahb = dev_get_drvdata(dev);
178
179 for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
180 ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]);
181 return 0;
182}
183
184static int tegra_ahb_resume(struct device *dev)
185{
186 int i;
187 struct tegra_ahb *ahb = dev_get_drvdata(dev);
188
189 for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
190 gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
191 return 0;
192}
193#endif
194
195static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
196 tegra_ahb_suspend,
197 tegra_ahb_resume, NULL);
198
199static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb)
200{
201 u32 val;
202
203 val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM);
204 val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
205 gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM);
206
207 val = gizmo_readl(ahb, AHB_GIZMO_USB);
208 val |= IMMEDIATE;
209 gizmo_writel(ahb, val, AHB_GIZMO_USB);
210
211 val = gizmo_readl(ahb, AHB_GIZMO_USB2);
212 val |= IMMEDIATE;
213 gizmo_writel(ahb, val, AHB_GIZMO_USB2);
214
215 val = gizmo_readl(ahb, AHB_GIZMO_USB3);
216 val |= IMMEDIATE;
217 gizmo_writel(ahb, val, AHB_GIZMO_USB3);
218
219 val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL);
220 val |= PRIORITY_SELECT_USB |
221 PRIORITY_SELECT_USB2 |
222 PRIORITY_SELECT_USB3 |
223 AHB_PRIORITY_WEIGHT(7);
224 gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL);
225
226 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1);
227 val &= ~MST_ID(~0);
228 val |= PREFETCH_ENB |
229 AHBDMA_MST_ID |
230 ADDR_BNDRY(0xc) |
231 INACTIVITY_TIMEOUT(0x1000);
232 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1);
233
234 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2);
235 val &= ~MST_ID(~0);
236 val |= PREFETCH_ENB |
237 USB_MST_ID |
238 ADDR_BNDRY(0xc) |
239 INACTIVITY_TIMEOUT(0x1000);
240 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2);
241
242 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3);
243 val &= ~MST_ID(~0);
244 val |= PREFETCH_ENB |
245 USB3_MST_ID |
246 ADDR_BNDRY(0xc) |
247 INACTIVITY_TIMEOUT(0x1000);
248 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3);
249
250 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4);
251 val &= ~MST_ID(~0);
252 val |= PREFETCH_ENB |
253 USB2_MST_ID |
254 ADDR_BNDRY(0xc) |
255 INACTIVITY_TIMEOUT(0x1000);
256 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4);
257}
258
259static int tegra_ahb_probe(struct platform_device *pdev)
260{
261 struct resource *res;
262 struct tegra_ahb *ahb;
263 size_t bytes;
264
265 bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo);
266 ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
267 if (!ahb)
268 return -ENOMEM;
269
270 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
271
272 /* Correct the IP block base address if necessary */
273 if (res &&
274 (res->start & INCORRECT_BASE_ADDR_LOW_BYTE) ==
275 INCORRECT_BASE_ADDR_LOW_BYTE) {
276 dev_warn(&pdev->dev, "incorrect AHB base address in DT data - enabling workaround\n");
277 res->start -= INCORRECT_BASE_ADDR_LOW_BYTE;
278 }
279
280 ahb->regs = devm_ioremap_resource(&pdev->dev, res);
281 if (IS_ERR(ahb->regs))
282 return PTR_ERR(ahb->regs);
283
284 ahb->dev = &pdev->dev;
285 platform_set_drvdata(pdev, ahb);
286 tegra_ahb_gizmo_init(ahb);
287 return 0;
288}
289
290static const struct of_device_id tegra_ahb_of_match[] = {
291 { .compatible = "nvidia,tegra30-ahb", },
292 { .compatible = "nvidia,tegra20-ahb", },
293 {},
294};
295
296static struct platform_driver tegra_ahb_driver = {
297 .probe = tegra_ahb_probe,
298 .driver = {
299 .name = DRV_NAME,
300 .of_match_table = tegra_ahb_of_match,
301 .pm = &tegra_ahb_pm,
302 },
303};
304module_platform_driver(tegra_ahb_driver);
305
306MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
307MODULE_DESCRIPTION("Tegra AHB driver");
308MODULE_LICENSE("GPL v2");
309MODULE_ALIAS("platform:" DRV_NAME);
310

Warning: That file was not part of the compilation database. It may have many parsing errors.