1/* SPDX-License-Identifier: GPL-2.0 */
2/* drivers/atm/idt77105.h - IDT77105 (PHY) declarations */
3
4/* Written 1999 by Greg Banks, NEC Australia <gnb@linuxfan.com>. Based on suni.h */
5
6
7#ifndef DRIVER_ATM_IDT77105_H
8#define DRIVER_ATM_IDT77105_H
9
10#include <linux/atmdev.h>
11#include <linux/atmioc.h>
12
13
14/* IDT77105 registers */
15
16#define IDT77105_MCR 0x0 /* Master Control Register */
17#define IDT77105_ISTAT 0x1 /* Interrupt Status */
18#define IDT77105_DIAG 0x2 /* Diagnostic Control */
19#define IDT77105_LEDHEC 0x3 /* LED Driver & HEC Status/Control */
20#define IDT77105_CTRLO 0x4 /* Low Byte Counter Register */
21#define IDT77105_CTRHI 0x5 /* High Byte Counter Register */
22#define IDT77105_CTRSEL 0x6 /* Counter Register Read Select */
23
24/* IDT77105 register values */
25
26/* MCR */
27#define IDT77105_MCR_UPLO 0x80 /* R/W, User Prog'le Output Latch */
28#define IDT77105_MCR_DREC 0x40 /* R/W, Discard Receive Error Cells */
29#define IDT77105_MCR_ECEIO 0x20 /* R/W, Enable Cell Error Interrupts
30 * Only */
31#define IDT77105_MCR_TDPC 0x10 /* R/W, Transmit Data Parity Check */
32#define IDT77105_MCR_DRIC 0x08 /* R/W, Discard Received Idle Cells */
33#define IDT77105_MCR_HALTTX 0x04 /* R/W, Halt Tx */
34#define IDT77105_MCR_UMODE 0x02 /* R/W, Utopia (cell/byte) Mode */
35#define IDT77105_MCR_EIP 0x01 /* R/W, Enable Interrupt Pin */
36
37/* ISTAT */
38#define IDT77105_ISTAT_GOODSIG 0x40 /* R, Good Signal Bit */
39#define IDT77105_ISTAT_HECERR 0x20 /* sticky, HEC Error*/
40#define IDT77105_ISTAT_SCR 0x10 /* sticky, Short Cell Received */
41#define IDT77105_ISTAT_TPE 0x08 /* sticky, Transmit Parity Error */
42#define IDT77105_ISTAT_RSCC 0x04 /* sticky, Rx Signal Condition Change */
43#define IDT77105_ISTAT_RSE 0x02 /* sticky, Rx Symbol Error */
44#define IDT77105_ISTAT_RFO 0x01 /* sticky, Rx FIFO Overrun */
45
46/* DIAG */
47#define IDT77105_DIAG_FTD 0x80 /* R/W, Force TxClav deassert */
48#define IDT77105_DIAG_ROS 0x40 /* R/W, RxClav operation select */
49#define IDT77105_DIAG_MPCS 0x20 /* R/W, Multi-PHY config'n select */
50#define IDT77105_DIAG_RFLUSH 0x10 /* R/W, clear receive FIFO */
51#define IDT77105_DIAG_ITPE 0x08 /* R/W, Insert Tx payload error */
52#define IDT77105_DIAG_ITHE 0x04 /* R/W, Insert Tx HEC error */
53#define IDT77105_DIAG_UMODE 0x02 /* R/W, Utopia (cell/byte) Mode */
54#define IDT77105_DIAG_LCMASK 0x03 /* R/W, Loopback Control */
55
56#define IDT77105_DIAG_LC_NORMAL 0x00 /* Receive from network */
57#define IDT77105_DIAG_LC_PHY_LOOPBACK 0x02
58#define IDT77105_DIAG_LC_LINE_LOOPBACK 0x03
59
60/* LEDHEC */
61#define IDT77105_LEDHEC_DRHC 0x40 /* R/W, Disable Rx HEC check */
62#define IDT77105_LEDHEC_DTHC 0x20 /* R/W, Disable Tx HEC calculation */
63#define IDT77105_LEDHEC_RPWMASK 0x18 /* R/W, RxRef pulse width select */
64#define IDT77105_LEDHEC_TFS 0x04 /* R, Tx FIFO Status (1=empty) */
65#define IDT77105_LEDHEC_TLS 0x02 /* R, Tx LED Status (1=lit) */
66#define IDT77105_LEDHEC_RLS 0x01 /* R, Rx LED Status (1=lit) */
67
68#define IDT77105_LEDHEC_RPW_1 0x00 /* RxRef active for 1 RxClk cycle */
69#define IDT77105_LEDHEC_RPW_2 0x08 /* RxRef active for 2 RxClk cycle */
70#define IDT77105_LEDHEC_RPW_4 0x10 /* RxRef active for 4 RxClk cycle */
71#define IDT77105_LEDHEC_RPW_8 0x18 /* RxRef active for 8 RxClk cycle */
72
73/* CTRSEL */
74#define IDT77105_CTRSEL_SEC 0x08 /* W, Symbol Error Counter */
75#define IDT77105_CTRSEL_TCC 0x04 /* W, Tx Cell Counter */
76#define IDT77105_CTRSEL_RCC 0x02 /* W, Rx Cell Counter */
77#define IDT77105_CTRSEL_RHEC 0x01 /* W, Rx HEC Error Counter */
78
79#ifdef __KERNEL__
80int idt77105_init(struct atm_dev *dev);
81#endif
82
83/*
84 * Tunable parameters
85 */
86
87/* Time between samples of the hardware cell counters. Should be <= 1 sec */
88#define IDT77105_STATS_TIMER_PERIOD (HZ)
89/* Time between checks to see if the signal has been found again */
90#define IDT77105_RESTART_TIMER_PERIOD (5 * HZ)
91
92#endif
93