| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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| 2 | /* |
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| 3 | * Amlogic A1 Peripherals Clock Controller internals |
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| 4 | * |
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| 5 | * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
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| 6 | * Author: Jian Hu <jian.hu@amlogic.com> |
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| 7 | * |
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| 8 | * Copyright (c) 2023, SberDevices. All Rights Reserved. |
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| 9 | * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef __A1_PERIPHERALS_H |
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| 13 | #define __A1_PERIPHERALS_H |
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| 14 | |
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| 15 | /* peripherals clock controller register offset */ |
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| 16 | #define SYS_OSCIN_CTRL 0x0 |
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| 17 | #define RTC_BY_OSCIN_CTRL0 0x4 |
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| 18 | #define RTC_BY_OSCIN_CTRL1 0x8 |
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| 19 | #define RTC_CTRL 0xc |
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| 20 | #define SYS_CLK_CTRL0 0x10 |
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| 21 | #define SYS_CLK_EN0 0x1c |
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| 22 | #define SYS_CLK_EN1 0x20 |
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| 23 | #define AXI_CLK_EN 0x24 |
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| 24 | #define DSPA_CLK_EN 0x28 |
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| 25 | #define DSPB_CLK_EN 0x2c |
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| 26 | #define DSPA_CLK_CTRL0 0x30 |
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| 27 | #define DSPB_CLK_CTRL0 0x34 |
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| 28 | #define CLK12_24_CTRL 0x38 |
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| 29 | #define GEN_CLK_CTRL 0x3c |
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| 30 | #define SAR_ADC_CLK_CTRL 0xc0 |
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| 31 | #define PWM_CLK_AB_CTRL 0xc4 |
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| 32 | #define PWM_CLK_CD_CTRL 0xc8 |
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| 33 | #define PWM_CLK_EF_CTRL 0xcc |
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| 34 | #define SPICC_CLK_CTRL 0xd0 |
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| 35 | #define TS_CLK_CTRL 0xd4 |
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| 36 | #define SPIFC_CLK_CTRL 0xd8 |
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| 37 | #define USB_BUSCLK_CTRL 0xdc |
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| 38 | #define SD_EMMC_CLK_CTRL 0xe0 |
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| 39 | #define CECA_CLK_CTRL0 0xe4 |
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| 40 | #define CECA_CLK_CTRL1 0xe8 |
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| 41 | #define CECB_CLK_CTRL0 0xec |
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| 42 | #define CECB_CLK_CTRL1 0xf0 |
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| 43 | #define PSRAM_CLK_CTRL 0xf4 |
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| 44 | #define DMC_CLK_CTRL 0xf8 |
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| 45 | |
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| 46 | #endif /* __A1_PERIPHERALS_H */ |
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| 47 | |
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